Lionel Landwerlin [Sat, 30 Sep 2017 13:43:06 +0000 (14:43 +0100)]
intel: decoder: enable decoding a single field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 30 Sep 2017 13:41:20 +0000 (14:41 +0100)]
intel: decoder: expose missing find_enum()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 30 Sep 2017 12:48:36 +0000 (13:48 +0100)]
intel: decoder: extract field value computation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 30 Sep 2017 11:48:48 +0000 (12:48 +0100)]
intel: decoder: rename field() to field_value()
We would like to avoid collisions with variables named field.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Thu, 28 Sep 2017 01:37:20 +0000 (02:37 +0100)]
intel: decoder: rename internal function to free name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Thu, 28 Sep 2017 01:36:30 +0000 (02:36 +0100)]
intel: decoder: simplify field_is_header()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 27 Sep 2017 19:57:28 +0000 (20:57 +0100)]
intel: common: make intel utils available from C++
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 27 Sep 2017 17:57:58 +0000 (18:57 +0100)]
intel: decoder: remove unused platform field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Thu, 1 Jun 2017 14:23:38 +0000 (15:23 +0100)]
intel: error-decode: implement a rolling window of programs
If we have more programs than what we can store,
aubinator_error_decode will assert. Instead let's have a rolling
window of programs.
v2: Fix overflowing issues (Eric Engestrom)
v3: Go through programs starting at idx_program (Scott)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Brian Paul [Wed, 1 Nov 2017 12:17:03 +0000 (06:17 -0600)]
gallium: increase pipe_sampler_view::target bitfield size for MSVC
MSVC treats enums as being signed. The 4-bit target field isn't large
enough to correctly store the value 8 (for PIPE_TEXTURE_CUBE_ARRAY).
The bitfield value 0x8 was being interpreted as -8 so matching the
target with PIPE_TEXTURE_CUBE_ARRAY in switch statements, etc. was
failing.
To keep the structure size the same, we reduce the format field from
16 bits to 15. There don't appear to be any other enum bitfields
which need to be adjusted.
This fixes a number of Piglit cube map array tests.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Eric Engestrom [Tue, 31 Oct 2017 18:47:00 +0000 (18:47 +0000)]
mapi: fix .so path in ABI-check
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Lionel Landwerlin [Mon, 25 Sep 2017 23:54:49 +0000 (00:54 +0100)]
intel: decoder: extract instruction/structs length
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 23 Sep 2017 23:44:57 +0000 (00:44 +0100)]
intel: decoder: pack iterator variable declarations
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 23 Sep 2017 23:43:09 +0000 (00:43 +0100)]
intel: decoder: simplify creation of struct when 0-allocated
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 23 Sep 2017 20:32:10 +0000 (21:32 +0100)]
intel: decoder: add destructor for gen_spec
This makes use of ralloc to simplify the destruction. We can also
store instructions in hash tables.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Sat, 23 Sep 2017 20:30:56 +0000 (21:30 +0100)]
intel: decoder: expose helper to test header fields
These fields are of little importance as they're used to recognize
instructions.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Thu, 3 Aug 2017 13:50:35 +0000 (14:50 +0100)]
intel: decoder: don't read qword outside instruction/struct limit
We used to print invalid data when the last field was being clamped to
32bits due to Dword Length of the whole instruction. Here is an
example where the decoder read part of the next instruction instead of
stopping at the 32bit limit:
0x000ce0b4: 0x10000002: MI_STORE_DATA_IMM
0x000ce0b4: 0x10000002 : Dword 0
DWord Length: 2
Store Qword: 0
Use Global GTT: false
0x000ce0b8: 0x00045010 : Dword 1
Core Mode Enable: 0
Address: 0x00045010
0x000ce0bc: 0x00000000 : Dword 2
0x000ce0c0: 0x00000000 : Dword 3
Immediate Data:
8791026489807077376
With this change we have the proper value :
0x000ce0b4: 0x10000002: MI_STORE_DATA_IMM (4 Dwords)
0x000ce0b4: 0x10000002 : Dword 0
DWord Length: 2
Store Qword: 0
Use Global GTT: false
0x000ce0b8: 0x00045010 : Dword 1
Core Mode Enable: 0
Address: 0x00045010
0x000ce0bc: 0x00000000 : Dword 2
0x000ce0c0: 0x00000000 : Dword 3
Immediate Data: 0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 21:33:28 +0000 (22:33 +0100)]
intel: decoder: split out getting the next field and decoding it
Due to the new way we handle fields, we need *not* to forget the first
field when decoding instructions. The issue was that the advance
function was called first and skipped the first field.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 21:32:25 +0000 (22:32 +0100)]
intel: decoder: move field name copy
This should be inside the function that actually decodes fields.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 21:30:14 +0000 (22:30 +0100)]
intel: decoder: reorder iterator init function
Making the next change more readable.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 18:33:09 +0000 (19:33 +0100)]
intel: common: print out all dword with field spanning multiple dwords
For example, we were skipping Dword 3 in this PIPE_CONTROL :
0x000ce130: 0x7a000004: PIPE_CONTROL
DWord Length: 4
0x000ce134: 0x00000010 : Dword 1
Flush LLC: false
Destination Address Type: 0 (PPGTT)
LRI Post Sync Operation: 0 (No LRI Operation)
Store Data Index: 0
Command Streamer Stall Enable: false
Global Snapshot Count Reset: false
TLB Invalidate: false
Generic Media State Clear: false
Post Sync Operation: 0 (No Write)
Depth Stall Enable: false
Render Target Cache Flush Enable: false
Instruction Cache Invalidate Enable: false
Texture Cache Invalidation Enable: false
Indirect State Pointers Disable: false
Notify Enable: false
Pipe Control Flush Enable: false
DC Flush Enable: false
VF Cache Invalidation Enable: true
Constant Cache Invalidation Enable: false
State Cache Invalidation Enable: false
Stall At Pixel Scoreboard: false
Depth Cache Flush Enable: false
0x000ce138: 0x00000000 : Dword 2
Address: 0x00000000
0x000ce140: 0x00000000 : Dword 4
Immediate Data: 0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Wed, 2 Aug 2017 18:31:08 +0000 (19:31 +0100)]
intel: decoder: build sorted linked lists of fields
The xml files don't always have fields in order. This might confuse
our parsing of the commands. Let's have the fields in order. To do
this, the easiest way it to use a linked list. It also helps a bit
with the iterator.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Lionel Landwerlin [Fri, 22 Sep 2017 17:00:25 +0000 (18:00 +0100)]
intel: common: expose gen_spec fields
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Eric Engestrom [Tue, 31 Oct 2017 17:35:16 +0000 (17:35 +0000)]
travis: build meson first for quicker feedback
Meson is much quicker to build Mesa, giving quicker feedback if
executed first.
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Tue, 31 Oct 2017 16:25:52 +0000 (16:25 +0000)]
meson: bump libdrm version required by amdgpu
Fixes:
f03b7c9ad92c1656a221 "winsys/amdgpu: Add R600_DEBUG flag to
reserve VMID per ctx."
Cc: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Jordan Justen [Sat, 25 Feb 2017 10:30:06 +0000 (02:30 -0800)]
i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false
(Apologies for the double negative.)
For now, the shader cache is disabled by default on i965 to allow us
to verify its stability.
In other words, to enable the shader cache on i965, set
MESA_GLSL_CACHE_DISABLE to false or 0. If the variable is unset, then
the shader cache will be disabled.
We use the build-id of i965_dri.so for the timestamp, and the pci
device id for the device name.
v2:
* Simplify code by forcing link to include build id sha. (Matt)
v3:
* Don't use a for loop with snprintf for bin to hex. (Matt)
* Assume fixed length render and timestamp string to further simplify
code.
Cc: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 18 Oct 2017 22:04:37 +0000 (15:04 -0700)]
dri drivers: Always add the sha1 build-id
v4:
* Add Android build changes. (Emil)
Cc: Dylan Baker <dylanx.c.baker@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sat, 14 Oct 2017 05:04:52 +0000 (22:04 -0700)]
disk_cache: Fix issue reading GLSL metadata
This would cause the read of the metadata content to fail, which would
prevent the linking from being skipped.
Seen on Rocket League with i965 shader cache.
Fixes:
b86ecea3446e "util/disk_cache: write cache item metadata to disk"
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 28 Mar 2017 18:48:55 +0000 (11:48 -0700)]
glsl/shader_cache: Save fs (BlendSupport) metadata
Fixes many GL 4.5 CTS blend tests, such as:
* GL45-CTS.blend_equation_advanced.extension_directive_enable
* GL45-CTS.blend_equation_advanced.extension_directive_warn
* GL45-CTS.blend_equation_advanced.blend_all.GL_MULTIPLY_KHR_all_qualifier
* GL45-CTS.blend_equation_advanced.blend_specific.GL_COLORBURN_KHR
v2:
* Directly save the BlendSupport field to avoid potentially including
a pointer in the future in the structure is updated. (tarceri)
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Sun, 26 Feb 2017 01:36:28 +0000 (17:36 -0800)]
i965: Initialize sha1 hash of dri config options
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sat, 25 Feb 2017 10:37:57 +0000 (02:37 -0800)]
i965: Don't link when the program was found in the disk cache
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Thu, 19 Oct 2017 02:25:48 +0000 (19:25 -0700)]
i965: add cache fallback support using serialized nir
If the i965 gen program cannot be loaded from the cache, then we
fallback to using a serialized nir program.
This is based on "i965: add cache fallback support" by Timothy Arceri
<timothy.arceri@collabora.com>. Tim's version was written to fallback
to compiling from source, and therefore had to be much more complex.
After Connor and Jason implemented nir serialization, I was able to
rewrite and greatly simplify this patch.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Mon, 23 Jan 2017 21:35:51 +0000 (08:35 +1100)]
i965: add support for cached shaders with xfb qualifiers
For now this disables the shader cache when transform feedback is
enabled via the GL API as we don't currently allow for it when
generating the sha for the shader.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sat, 19 Nov 2016 05:16:08 +0000 (16:16 +1100)]
mesa/glsl: add api_enabled flag to gl_transform_feedback_info
This will be used to disable the shader cache when xfb is enabled
via the api as we don't currently allow for it when generating the
sha for the shader.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Thu, 2 Mar 2017 00:52:23 +0000 (16:52 -0800)]
i965: Add shader cache support for compute
v2:
* Use MAYBE_UNUSED. (Matt)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 29 Nov 2016 01:25:54 +0000 (12:25 +1100)]
i965: add shader cache support for tess stages
v2:
* Use MAYBE_UNUSED. (Matt)
[jordan.l.justen@intel.com: *_cached_program => brw_disk_cache_*_program]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 29 Nov 2016 01:24:54 +0000 (12:24 +1100)]
i965: add shader cache support for geometry shaders
v2:
* Use MAYBE_UNUSED. (Matt)
[jordan.l.justen@intel.com: *_cached_program => brw_disk_cache_*_program]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Mon, 23 Jan 2017 21:41:36 +0000 (08:41 +1100)]
i965: Add shader cache support for vertex and fragment stages
This enables the cache on vertex and fragment shaders only.
v2:
* Use MAYBE_UNUSED. (Matt)
[jordan.l.justen@intel.com: reword subject]
[jordan.l.justen@intel.com: *_cached_program => brw_disk_cache_*_program]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 1 Jul 2016 07:02:57 +0000 (17:02 +1000)]
i965: add initial implementation of on disk shader cache
This uses the Mesa disk_cache support to write out the final linked
binary for vertex and fragment shader programs.
This is based off the initial implementation done by Carl Worth. It
has been significantly reworked, first by Tim Arceri, and then by
Jordan Justen.
v2:
* Squash 'i965: add image param shader cache support'
* Squash 'i965: add shader cache support for pull param pointers'
* Sustantially simplified by a rework on top of Jason's
2975e4c56a7a.
* Rename load_program_data to read_program_data. (Jason)
v3:
* Simplify and align program read/write. (Jason)
v4:
* Don't save prog_data size since we know it from the stage. (Ken)
* Don't save program size, since prog_data includes the size. (Ken)
* Remove `assert` that potentially could be triggered by disk
corruption of the cache entries. (Ken)
* Fix compute shader scratch allocation. (Ken)
* Remove special case mapping for non-LLC. (Ken)
* Remove SET_UPLOAD_PARAMS macro
[jordan.l.justen@intel.com: *_cached_program => brw_disk_cache_*_program]
[jordan.l.justen@intel.com: brw_shader_cache.c => brw_disk_cache.c]
[jordan.l.justen@intel.com: don't map to write program when LLC is present]
[jordan.l.justen@intel.com: set program_written_to_cache on read from cache]
[jordan.l.justen@intel.com: only try cache when status is linking_skipped]
[jordan.l.justen@intel.com: all v2-v4 changes noted above]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 31 Oct 2017 07:34:32 +0000 (00:34 -0700)]
i965: Calculate thread_count in brw_alloc_stage_scratch
Previously, thread_count was sent in from the stage after some stage
specific calculations. Those stage specific calculations were moved
into brw_alloc_stage_scratch, which will allow the shader cache to
also use the same calculations.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sat, 21 Oct 2017 08:30:13 +0000 (01:30 -0700)]
intel/compiler: Add functions to get prog_data and prog_key sizes for a stage
v2:
* Return unsigned instead of size_t. (Ken)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sat, 21 Oct 2017 08:29:16 +0000 (01:29 -0700)]
intel/compiler: Add union types for prog_data and prog_key stages
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Sat, 21 Oct 2017 09:23:30 +0000 (02:23 -0700)]
blob: Don't set overrun if reading 0 bytes at end of data
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Sun, 22 Oct 2017 03:55:45 +0000 (20:55 -0700)]
intel/compiler: Remove final_program_size from brw_compile_*
The caller can now use brw_stage_prog_data::program_size which is set
by the brw_compile_* functions.
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Carl Worth [Thu, 14 Apr 2016 00:59:16 +0000 (10:59 +1000)]
intel/compiler: add new field for storing program size
This will be used by the on disk shader cache.
v2:
* Set in brw_compile_* rather than brw_codegen_*. (Jason)
Signed-off-by: Timothy Arceri <timothy.arceri@collabora.com>
[jordan.l.justen@intel.com: Only add to brw_stage_prog_data]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Fri, 28 Jul 2017 22:46:02 +0000 (15:46 -0700)]
i965: Don't rely on nir for uses_texture_gather
When a program is restored from the shader cache, prog->nir will be
NULL, but prog->info will be restored.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Fri, 13 Oct 2017 20:07:50 +0000 (13:07 -0700)]
i965/link: Serialize program to nir after linking for shader cache
If the shader cache is enabled, after linking the program, we
serialize the program to nir. This will be saved out by the glsl
shader cache support.
Later, if the same program is found in the cache, we can use the nir
for a fallback in the unlikely case that the gen binary program is not
found in the cache.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Fri, 13 Oct 2017 20:02:29 +0000 (13:02 -0700)]
glsl/shader_cache: Save and restore serialized nir in gl_program
v3:
* Rename serialized_nir* to driver_cache_blob*. (Tim)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Fri, 13 Oct 2017 20:00:23 +0000 (13:00 -0700)]
main: Add driver cache blob fields to gl_program
These fields can be used to optionally save off a driver blob with the
program metadata. For example, serialized nir, or tgsi.
v3:
* Rename serialized_nir* to driver_cache_blob*. (Tim)
* Free memory. (Jason)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Thu, 14 Sep 2017 23:49:53 +0000 (16:49 -0700)]
nir: Add hooks for testing serialization
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Connor Abbott [Wed, 13 Sep 2017 03:17:51 +0000 (23:17 -0400)]
nir: add serialization and deserialization
v2 (Jason Ekstrand):
- Various whitespace cleanups
- Add helpers for reading/writing objects
- Rework derefs
- [de]serialize nir_shader::num_*
- Fix uses of blob_reserve_bytes
- Use a bitfield struct for packing tex_instr data
v3:
- Zero nir_variable struct on deserialization. (Jordan)
- Allow nir_serialize.h to be included in C++. (Jordan)
- Handle NULL info.name. (Jason)
- Set info.name to NULL when name is NULL. (Jordan)
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Tue, 31 Oct 2017 23:54:27 +0000 (09:54 +1000)]
mesa/st: implement max combined output resources limiting.
if the driver sets the cap, then use the value it gives us.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 31 Oct 2017 23:40:33 +0000 (09:40 +1000)]
gallium: add cap for driver specified max combined shader resources.
Some hw (evergreen) has a limit on how many combined (images/buffers/mrts)
a fragment shader can access.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Gert Wollny [Mon, 16 Oct 2017 19:06:26 +0000 (21:06 +0200)]
r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling
It is possible that the optimizer ends up in an infinite loop in
post_scheduler::schedule_alu(), because post_scheduler::prepare_alu_group()
does not find a proper scheduling. This can be deducted from
pending.count() being larger than zero and not getting smaller.
This patch works around this problem by signalling this failure so that the
optimizers bails out and the un-optimized shader is used.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103142
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Tue, 31 Oct 2017 03:19:18 +0000 (14:19 +1100)]
radeonsi: fix culldist_writemask in nir path
The shared si_create_shader_selector() code already offsets the mask.
Fixes the following piglit tests:
arb_cull_distance/clip-cull-3.shader_test
arb_cull_distance/clip-cull-4.shader_test
Fixes:
29d7bdd179bb (radeonsi: scan NIR shaders to obtain required info)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Neil Roberts [Tue, 31 Oct 2017 14:05:33 +0000 (15:05 +0100)]
nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB
Previously the values were calculated by just shifting ~0 by the
invocation ID. This would end up including bits that are higher than
gl_SubGroupSizeARB. The corresponding CTS test effectively requires that
these high bits be zero so it was failing. There is a Piglit test as
well but this appears to checking the wrong values so it passes.
For the two greater-than bitmasks, this patch adds an extra mask with
(~0>>(64-gl_SubGroupSizeARB)) to force these bits to zero.
Fixes: KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680#c3
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Neil Roberts <nroberts@igalia.com>
Nanley Chery [Thu, 26 Oct 2017 23:05:52 +0000 (16:05 -0700)]
i965: Check CCS_E compatibility for texture view rendering
Only use CCS_E to render to a texture that is CCS_E-compatible with the
original texture's miptree (linear) format. This prevents render
operations from writing data that can't be decoded with the original
miptree format.
On Gen10, with the new CCS_E-enabled formats handled, this enables the
driver to pass the arb_texture_view-rendering-formats piglit test.
v2. Add a TODO for texturing. (Jason)
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Wed, 23 Aug 2017 17:51:28 +0000 (10:51 -0700)]
intel/isl: Disable some gen10 CCS_E formats for now
CannonLake additionally supports R11G11B10_FLOAT and four 10-10-10-2
formats with CCS_E. None of these formats fit within the current
blorp_copy framework so disable them until support is added.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Mon, 30 Oct 2017 15:46:15 +0000 (15:46 +0000)]
meson: pass correct args to gles2 ABI test
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:46:05 +0000 (15:46 +0000)]
meson: pass correct args to gles1 ABI test
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:45:22 +0000 (15:45 +0000)]
meson: pass correct args to gbm symbol test
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:47:26 +0000 (15:47 +0000)]
meson: pass correct args to wayland-egl symbol test
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:43:10 +0000 (15:43 +0000)]
automake+meson: don't run egl symbol check on libglvnd lib
We might want to add a symbol check for the glvnd variant though.
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:42:16 +0000 (15:42 +0000)]
meson: pass correct env/args to egl tests
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:28:18 +0000 (15:28 +0000)]
gles2: fail symbol check if lib is missing
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:28:08 +0000 (15:28 +0000)]
gles1: fail symbol check if lib is missing
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:27:25 +0000 (15:27 +0000)]
gbm: fail symbol check if lib is missing
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:27:49 +0000 (15:27 +0000)]
wayland-egl: fail symbol check if lib is missing
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 30 Oct 2017 15:27:10 +0000 (15:27 +0000)]
egl: fail symbol check if lib is missing
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Mon, 30 Oct 2017 18:31:45 +0000 (11:31 -0700)]
meson: set visibility flags on gbm
This is done in autotools, and is an oversight in the meson build.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Mon, 30 Oct 2017 18:30:34 +0000 (11:30 -0700)]
meson: Don't link gbm with threads
It's supposed to be linked with pthread-stubs (if the platform needs
pthread-stubs). Pthread stubs support isn't (yet) implemented in the
meson build, so add a TODO.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Mon, 30 Oct 2017 17:27:48 +0000 (10:27 -0700)]
meson: Use true and false instead of yes and no for tristate options
This allows a user to not care whether they're setting a tristate or a
boolean option, which is a nice user facing feature, and something I've
personally run into.
Suggested-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Andrey Grodzovsky [Tue, 31 Oct 2017 15:40:12 +0000 (11:40 -0400)]
winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Wed, 25 Oct 2017 08:02:38 +0000 (10:02 +0200)]
meson: do not search for needless deps
If we don't want to use these deps, there's no good reason to search
for them in the first place. This should shave a bit of time for the
initial build.
Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Samuel Pitoiset [Mon, 30 Oct 2017 18:37:39 +0000 (19:37 +0100)]
radv: bail out when binding the same vertex buffers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 30 Oct 2017 16:12:05 +0000 (17:12 +0100)]
radv: bail out when binding the same index buffer
DOW3 appears to hit this path.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Erik Faye-Lund [Sat, 28 Oct 2017 12:36:04 +0000 (14:36 +0200)]
meson: use dep_m in libgallium
The u_format_other.c users sqrtf, which on some systems require
a math-library. So let's make sure we link with it.
Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Tue, 31 Oct 2017 00:31:19 +0000 (11:31 +1100)]
radv: use correct alloc function when loading from disk
Fixes regression in:
dEQP-VK.api.object_management.alloc_callback_fail.graphics_pipeline
Fixes:
1e84e53712ae "radv: add cache items to in memory cache when reading from disk"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Plamena Manolova [Mon, 30 Oct 2017 21:14:24 +0000 (21:14 +0000)]
i965: Fix ARB_indirect_parameters logic.
This patch modifies the ARB_indirect_parameters logic in
brw_draw_prims, so that our implementation isn't affected if
another application attempts to use predicates. Previously we
were using a predicate with a DELTAS_EQUAL comparison operation
and relying on the MI_PREDICATE_DATA register being 0. Our code
to initialize MI_PREDICATE_DATA to 0 was incorrect, so we were
accidentally using whatever value was written there. Because the
kernel does not initialize the MI_PREDICATE_DATA register on
hardware context creation, we might inherit the value from whatever
context was last running on the GPU (likely another process).
The Haswell command parser also does not currently allow us to write
the MI_PREDICATE_DATA register. Rather than fixing this and requiring
an updated kernel, we switch to a different approach which uses a
SRCS_EQUAL predicate that makes no assumptions about the states of any
of the predicate registers.
Fixes Piglit's spec/arb_indirect_parameters/tf-count-arrays test.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103085
Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Fri, 20 Oct 2017 22:38:52 +0000 (15:38 -0700)]
i965: Don't flag BRW_NEW_SURFACES unless some push constants are dirty.
Due to a gaffe on my part, we were re-emitting all binding table entries
on every single draw call. The push_constant_packets atom listens to
BRW_NEW_DRAW_CALL, but skips emitting 3DSTATE_CONSTANT_XS for each stage
unless stage_state->push_constants_dirty is true. However, it flagged
BRW_NEW_SURFACES unconditionally at the end, by mistake.
Instead, it should only flag it if we actually emit 3DSTATE_CONSTANT_XS
for a stage. We can move it a few lines up, inside the loop - the early
continues will skip over it if push constants aren't dirty for a stage.
With INTEL_NO_HW=1 set, improves performance of GFXBench5 gl_driver_2
on Apollolake at 1280x720 by 1.01122% +/- 0.470723% (n=35).
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Kenneth Graunke [Thu, 26 Oct 2017 03:33:33 +0000 (20:33 -0700)]
intel/genxml: Fix decoding of groups with fields smaller than a DWord.
Groups containing fields smaller than a DWord were not being decoded
correctly. For example:
<group count="32" start="32" size="4">
<field name="Vertex Element Enables" start="0" end="3" type="uint"/>
</group>
gen_field_iterator_next would properly walk over each element of the
array, incrementing group_iter, and calling iter_group_offset_bits()
to advance to the proper DWord. However, the code to print the actual
values only considered iter->field->start/end, which are 0 and 3 in the
above example. So it would always fetch bits 3:0 of the current DWord
when printing values, instead of advancing to each element of the array,
printing bits 0-3, 4-7, 8-11, and so on.
To fix this, we add new iter->start/end tracking, which properly
advances for each instance of a group's field.
Caught by Matt Turner while working on 3DSTATE_VF_COMPONENT_PACKING,
with a patch to convert it to use an array of bitfields (the example
above).
This also fixes the decoding of 3DSTATE_SBE's "Attribute Active
Component Format" fields.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Ian Romanick [Thu, 26 Oct 2017 22:32:09 +0000 (15:32 -0700)]
glsl: Fix bad formatting in a comment
Trivial
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Fri, 27 Oct 2017 22:52:22 +0000 (15:52 -0700)]
broadcom/vc5: Force blending to treat alpha as 1 for formats without alpha.
Fixes fbo-blending-formats on RGB8 and 565. We will still need to demote
blending to shader code in the MRT case to fix it in general, but that can
be added when we start doing 32F blending (which also needs to be done in
the shader).
Eric Anholt [Fri, 27 Oct 2017 21:41:35 +0000 (14:41 -0700)]
broadcom/vc5: Do BGRA vs RGBA swapping for the BLEND_CONSTANT_COLOR.
Fixes many of the fbo-blending-formats tests.
Eric Anholt [Fri, 27 Oct 2017 21:13:46 +0000 (14:13 -0700)]
broadcom/vc5: Pack clear colors according to the TLB internal format/type.
The previous packing I did got us all the R*16F and R*32F formats, where
the pipe format basically matched the TLB's format, but since the clear
color will just be memcpyed to the TLB, we should be looking at its format
for deciding how to pack.
Fixes RGB565, RGB5_A1 and RGBA10 fbo-clear-formats tests and improves
4444.
Eric Anholt [Mon, 30 Oct 2017 17:13:52 +0000 (10:13 -0700)]
broadcom/vc5: Don't do r/b channel swapping on 565.
The HW's format actually matches the gallium format.
Eric Anholt [Fri, 27 Oct 2017 21:08:02 +0000 (14:08 -0700)]
broadcom/vc5: Use the proper gallium format for our RGB10_A2.
This keeps us from needing our own reswizzling of the B vs R fields.
Eric Anholt [Fri, 27 Oct 2017 20:27:22 +0000 (13:27 -0700)]
broadcom/vc5: Add some comments about the texture/output format ordering.
The output formats are consistent with their channels appearing from low
to high in their name. Textures are interpreted the same way, but their
names may have the channels swapped around. I'm retaining the texture
names so that we are consistent with the documentation, but I want to
leave a warning for others.
Eric Anholt [Thu, 26 Oct 2017 23:03:59 +0000 (16:03 -0700)]
broadcom/vc5: Drop duplicated setup of clip_window_height_in_pixels.
Eric Anholt [Thu, 26 Oct 2017 22:59:21 +0000 (15:59 -0700)]
broadcom/vc5: Don't forget to actually turn on stencil testing.
I had the rest of stencil state set up, but forgot to actually enable it
in the higher level configuration bits packet.
Eric Anholt [Thu, 26 Oct 2017 22:40:38 +0000 (15:40 -0700)]
broadcom/vc5: Stop lowering negates to subs.
In the case of fneg(0.0), we were getting back 0.0 instead of -0.0. We
were also needing an immediate 0 value for ineg, when there's an opcode to
do the job properly.
Fixes fs-floatBitsToInt-neg.shader_test.
Eric Anholt [Wed, 25 Oct 2017 20:00:44 +0000 (13:00 -0700)]
broadcom/vc5: Set up MSAA texture type according to the internal format.
It gets most of EXT_framebuffer_multisample-formats passing, but doesn't
really work for texture views.
Eric Anholt [Wed, 25 Oct 2017 19:51:04 +0000 (12:51 -0700)]
broadcom/vc5: Use the sampler view's format, not the resource's.
This should help with texture views, though I just noticed this while
reading the code.
Eric Anholt [Wed, 25 Oct 2017 19:29:51 +0000 (12:29 -0700)]
broadcom/vc5: Emit raw loads for MSAA buffers.
Similar to stores, but we also need to emit dummy stores in between each
load, to flush out the previous queued load.
Eric Anholt [Tue, 24 Oct 2017 20:28:53 +0000 (13:28 -0700)]
broadcom/vc5: Use raw stores for MSAA buffers.
We were storing the resolved pixels in all cases, but nr_samples > 0 means
we should be keeping the per-sample values.
We will probably want to change the job structure at some point, as we'll
want to recognize full-buffer resolves and do the resolved store in the
same job as the original rendering, meaning we'll need to track both the
MSAA and single-sample resources in the job. However, this will be enough
to build the rest of the MSAA support.
Eric Anholt [Tue, 24 Oct 2017 19:16:50 +0000 (12:16 -0700)]
broadcom/vc5: Add lowering for txf_ms to a txf on a 2x2-scaled texture.
The HW has no native sampler support for multisample textures, but since
we only need to support txf_ms and the layout is UIF, we just need to
scale up the texcoords and then add in the sample.
This drops the old TEXTURE_MSAA_ADDR special uniform, since we're treating
MSAA textures as textures, rather than basically texbos like VC4 had to.
Eric Anholt [Wed, 25 Oct 2017 01:45:57 +0000 (18:45 -0700)]
broadcom/vc5: Lay out MSAA textures/renderbuffers as UIF scaled by 4.
We just need to multiply width/height by 2 each, and always set them up as
UIF tiling, since that's how the TLB will store them in raw (per-sample)
mode.
Eric Anholt [Wed, 25 Oct 2017 01:35:00 +0000 (18:35 -0700)]
broadcom/vc5: Keep output height pad out of the store TLB general address.
The equivalent load already had the pad separated out.
Eric Anholt [Wed, 25 Oct 2017 02:14:29 +0000 (19:14 -0700)]
broadcom/vc5: Drop padding bits from the texture shader state's address.
Eric Anholt [Wed, 25 Oct 2017 02:14:08 +0000 (19:14 -0700)]
broadcom/vc5: Drop alignment bits from texture P1's address.