usb: board_usb_init and board_usb_cleanup calls in the fastboot command

Each USB download function command calls board_usb_init before registering the
USB gadget and board_usb_cleanup after de-registering it. On devices currently
using fasboot, musb-new is usually initialized earlier, but some other boards
might need the board_usb_init call to properly initialize musb-new.

This requires adding an argument (the USB controller index) to the fastboot
command, as it is currently done with other USB download gadget functions.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)

usb: Fastboot function config for better consistency with other functions

USB download gadget functions such as thor and dfu have a separate config option
for the USB gadget part of the code, independent from the command part.
This switches the fastboot USB gadget to the same scheme, for better
consistency.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)

usb: USB download gadget and functions config options coherent naming

This introduces a coherent scheme for naming USB download gadget and functions
config options. The download USB gadget config option is moved to
CONFIG_USB_GADGET_DOWNLOAD for better consistency with other gadgets and each
function's config option is moved to a CONFIG_USB_FUNCTION_ prefix.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)

drivers: usb: fsl: Remove LS102XA immap inclusion

Remove LS102XA immap header inclusion from xhci fsl driver.
It removes redefinition warnings when built for platforms
other than LS102XA

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>

include: usb: Map USB controller base addresses for LS2085A

Map USB XHCI controller base addresses for LS2085A SOC

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>

include: usb: Move USB controller base address mapping

Move USB controller Base address mapping from ls102xa immap
to fsl xhci header. This is required to remove any warnings when
controller base addresses are mapped for multiple platforms
in their respective files.

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>

drivers: usb: fsl: Implement Erratum A-009116 for XHCI controller

This adjusts (micro)frame length to appropriate value thus
avoiding USB devices to time out over a longer run

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>

drivers: usb: fsl: Remove warnings for 64-bit architectures

Replace uint32_t with uintptr_t to remove compilation
warnings for 64-bit architectures.

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>

ls1021aqds: Enable USB IP support

Enable USB IP support for both EHCI and XHCI for
ls1021aqds platform

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

ls1021atwr: Enable USB IP support

Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

arch: arm: fsl: Add XHCI support for LS1021A

Add base register address information for USB
XHCI controller on LS1021A

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

usb: fsl: Add XHCI driver support

Add xhci driver support for all FSL socs

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

usb: xhci: keystone: Remove common dwc3 drv functions calls

Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

usb: xhci: omap: Remove common dwc3 drv functions calls

Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

usb: xhci: exynos: Remove common dwc3 drv functions calls

Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

usb: dwc3: Add DWC3 controller driver support

Add support for DWC3 XHCI controller driver

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.

When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

armv8: Fix TCR macros for shareability attribute

For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

armv8/ls2085a/defconfig: Enable FSL_DSPI, OF_CONTROL and DM support

Freescale DSPI driver has been converted to Driver Model.
The new driver depends on OF_CONTROL, DM, DM_SPI.
This patch enable FSL_DSPI and its dependence configure options.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085ardb: Enable DSPI flash support for LS2085ARDB

Enable DSPI flash related configurations for LS2085ARDB.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085aqds: Enable DSPI flash support for LS2085AQDS

Enable DSPI flash related configurations.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLD

DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085aqds: DSPI pin muxing configure through QIXIS

DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085a: Enable DSPI get input clk form 'mxc_get_clock'

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm/dts/ls2085a: Add dts files for LS2085AQDS and LS2085ARDB

Add dts source files for LS2085AQDS and LS2085ARDB boards.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm/dts/ls2085a: Add DSPI dts node

Add DSPI controller dts node in fsl-ls2085a.dtsi

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm/dts/ls2085a: Bring in ls2085a dts files from linux kernel

Bring in required device tree files for ls2085a from Linux. These are
initially unchanged and have a number of pieces not needed by U-Boot.

Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm/ls102xa: Add little-endian mode support for audio IPs

As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm/ls102xa: Add PSCI support for ls102xa

Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.

Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S

timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm: ls1021a: Remove the inappropriate use of the function 'sprintf'

As the function 'sprintf' does not check buffer boundaries but outputs
to the buffer 'enet' of fixed size (16), this patch removes the function
'sprintf', and uses 'strcpy' instead. It will assign the character
arrays 'enet' and 'phy' the corresponding character strings.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>

board/ls2085a: Increase kernel_size value in env variable

Linux itb image size has been increased from 30MB.

So updating kernel_size to 40MB in env variable.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

board/ls2085rdb: Export functions for standalone AQ FW load apps

Export functions required by Aquntia PHY firmware load application.
functions are memset, strcpy, mdelay, mdio_get_current_dev,
phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

driver/ldpaa_eth:Avoid infinite loop in ldpaa_eth_rx

Change infinite loop mechanism to timer based polling for QBMAN release in
ldpaa_eth_rx.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

driver/ldpaa_eth: Avoid TX conf frames

Polling of TX conf frames is not a mandatory option.
Packets can be transferred via WRIOP without TX conf frame.

Configure ldpaa_eth driver to use TX path without confirmation frame

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>

driver/ldpaa_eth: Add timeout handling DQRR entry read

Volatile command does not return frame immidiately, need to wait till a frame
is available in DQRR. Ideally it should be a blocking call.

Add timeout handling for DQRR frame instead of retry counter.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>

driver/ldpaa_eth: Retry enqueue if portal was busy

Do not immediately return if the enqueue function returns -EBUSY; re-try
mulitple times.

if timeout occures, release the buffer.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/fsl-lsch3: device tree fixups for PCI stream IDs

This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree.  Fixups are implemented for PCI controllers
initially.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

drivers/fsl-mc: dynamically create ICID pool in DPC

delete any existing ICID pools in the DPC and create
a new one based on the stream ID partitioning for
the SoC

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/fsl-lsch3: partition stream IDs

Stream IDs on ls2085a devices are not hardwired and are
programmed by sw.  There are a limited number of stream IDs
available, and the partitioning of them is scenario dependent.
This header defines the partitioning between legacy, PCI,
and DPAA2 devices.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

drivers: fsl-mc: Return error for major version mismatch

Management complex major version should match to the firmware present in flash.

Return error during mismatch of major version.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>

drivers: fsl-mc: Update qbman driver

Update qbman driver
 - As per latest available qbman driver
 - Use of atomic APIs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Geoff Thorpe <Geoff.Thorpe@freescale.com>
CC: Haiying Wang <Haiying.Wang@freescale.com>
CC: Roy Pledge <Roy.Pledge@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

drivers: fsl-mc: Update flibs to mc-0.6.0.1

Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects
Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in
dpio_attr. These are now offsets from the SoC QBMan portals base.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

drivers/fsl-mc: Autoload AOIP image from NOR flash

Load AIOP image from NOR flash into DDR so that the MC firmware
the MC fw can start it at boot time

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

driver/ldpaa_eth:Flush buffer before seeding BMAN after TX_conf

Flush buffer before releasing to BMan after TX_conf to ensure, the core does
not have any cachelines that the WRIOP will DMA to.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

drivers/fsl-mc: Make MC boot error messages more readable

Make it easier for the user to notice when the MC firmware
had problems booting.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085a: enable debug server

Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvr

The agreed split of the top of memory is 256M for debug server and 256M
 for MC. This patch implements the split.

 In addition, the MC mem must be 512MB aligned, so the amount of memory
 to hide must be 512MB to achieve that alignment.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm/errata: Update required bits for A57 cores erratas

This patch updates the setting of required bits for A57 cores erratas
- 828024 and 826974

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Dai Haruki <dai.haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

driver/fsl_debug_server: Fix the DDR hide logic for LS2085a

This patch fixes the DDR hide logic for LS2085a, correcting the way
the Debug Server FW and MC FW images are placed on the top of system
DDR and how the rest of the system DDR space is made visibile to Linux.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085a: Update SoC README for DDR layout

Update SoC README to provide details of
 - Memory regions
 - Memory used by MC and Debug server

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085a: Expose all DDR region(s) to Linux

This patch allows u-boot to expose the complete DDR region(s) to Linux
(after subtracting the memory hidden via MEM_TOP_HIDE mechanism).

This allows the u-boot to support the 48-bit VA support provided by
ARM64 Linux in flavors 3.18 and above, by passing the appropriate
'memory' DTS nodes.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085ardb: Fix SPD address error on early boards

Board rev C and earlier has duplicated SPD address on 2nd DDR
controller slots. It is fixed on rev D and later. SPD addresses
need to be updated accordingly.

Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>

driver/ddr/fsl: Add a hook to update SPD address

In case SPD address changes between board revisions, updating SPD
address can be called from board file.

Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>

armv8/ls2085a: Avoid hard-coding for board name print

LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE,
LS2080A, LS2085AE and LS2085A personlities.

Instead of hard-coding, board name should change as per selected
personality.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/fsl-ch3: Add support to print SoC personality

This patch adds support to print out the SoC personality.
Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can
have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A,
LS2085AE and LS2085A

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/fsl-lsch3: Fix DDR speed message

DDR speed should be in MT/s, not MHz.

Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>

armv8/ls2085RDB: Update board version print logic

As per updated board document, no need to substract 1 from arch[BRD]
bit field. Default value + 'A' represents the board revision.

So update board version print logic to reflect the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

board/fsl/common: Fix eeprom system version endianness

SYSTEM ID EPPROM always store SYSTEM version info in big endian format.
SoC with ARM or PowerPC core should read/write version info from eeprom
in BIG endian format.

So use cpu-specific APIs to read SYSTEM version.

Signed-off-by: Jaiprakash Singh <b44839 at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085a: Increase the supported kernel size

Increases the kernel size supported for LS2085A platforms:-
 - Update environment variables
 - Add ramdisk_size in bootargs env variable
 - Define  CONFIG_SYS_BOOTM_LEN to 64MB

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085rdb: Update PCA9547PW slave address

Primary Mux on I2C1 controller has slave address as 0x75.
So update its address.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085qds: Update SFP TX bit as "0" to enable XFI

FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports.

Signed-off-by: Dai Haruki <Dai.Haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085a: call ft_pcie_setup() to change dts status

call ft_pci_setup() to disable PCIe dts node if corresponding
PCIe controller is disabled according to RCW

Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085a: Update LS2085a PCIe compatible

Compatible field "fsl,20851a-pcie" is not correct.
So update it to "fsl,ls2085a-pcie"

Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085aqds: Add support of SerDes protocol 0x49

SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2.

Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of
ls2085aqds platform.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085a: Enable "date" command for QDS and RDB

Enable "date" command for QDS and RDB boards

Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085ardb: add hwconfig setting for eSDHC

Add hwconfig setting for eSDHC since it shares some pins with other
IP block.

Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

armv8/ls2085ardb: Add eth & phy firmware loading support

Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.

Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

libfdt: fix error code of fdt_count_strings()

Currently, this function returns a positive value on error,
so we never know whether this function has succeeded or failed.

For example, if the given property is not found, fdt_getprop()
returns -FDT_ERR_NOTFOUND, and then this function inverts it,
i.e., returns FDT_ERR_NOTFOUND (=1).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: bc4147ab2d69 ("fdt: Add a function to count strings")
Acked-by: Simon Glass <sjg@chromium.org>

libfdt: fix error code of fdt_get_string_index()

As mentioned in the comment block in include/libfdt.h,
fdt_get_string_index() is supposed to return a negative value
on error.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: 5094eb408a5d ("fdt: Add functions to retrieve strings")
Acked-by: Simon Glass <sjg@chromium.org>

libfdt: fix description of fdt_get_string()

Looks like this comment was copied from that of
fdt_get_string_index().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: 5094eb408a5d ("fdt: Add functions to retrieve strings")
Acked-by: Simon Glass <sjg@chromium.org>

cmd_fdt: save fdtaddr in hex format

Commit 90fbee3e4051 ("cmd_fdt: Actually fix fdt command in sandbox")
changed the format(from hex address to unsigned long) in which "fdtaddr"
is saved . However do_fdt continues reads the "fdtaddr" assuming it to
be in hex format. This may lead to fdt being either loaded or attempted
to load at erroneous address generating fault if the address is out of
memory.

This patch changes back the format to hex while saving the "fdtaddr"
as it was done before.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Hua Yanghao <huayanghao@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>

fdt: armv8: Fix build warnings on armv8

Fix below build warnings on armv8,
drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’:
drivers/spi/fsl_dspi.c:667:2:
warning: format ‘%x’ expects argument of type ‘unsigned int’,
but argument 2 has type ‘fdt_addr_t’ [-Wformat=]
debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n",
    ^
lib/fdtdec.c: In function ‘fdtdec_get_addr_size’:
lib/fdtdec.c:105:4:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’,
but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug("addr=%08lx, size=%08lx\n",
    ^

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>

fdt: prevent clearing memory node if there are no banks

Avoid clearing the reg property in the memory DT node if no memory
banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0).
This allows boards to let U-Boot skip the DT memory tinkering in case
other firmware has already setup the node properly before.
This should be safe as all callers of fdt_fixup_memory_banks that use
a computed <banks> value put at least 1 in there.
Add some documentation comments to the header file.

Signed-off-by: Andre Przywara <osp@andrep.de>
Acked-by: Simon Glass <sjg@chromium.org>

Merge git://git.denx.de/u-boot-x86

pci: Disable expansion ROM address decoding when signature check fails

We should not leave the expansion ROM address window open when there
is not a valid ROM.

Suggested-by: Matt Porter <mporter@konsulko.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

pci: Configure expansion ROM during auto config process

Currently PCI expansion ROM address is assigned by a call to
pciauto_setup_rom() outside of the pci auto config process.
This does not work when expansion ROM is on a device behind
PCI bridge where bridge's memory limit register was already
programmed to a value that does not cover the newly assigned
expansion ROM address. To fix this, we should configure the
ROM address during the auto config process.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

drivers: block: Remove the ata_piix driver

This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

x86: Adjust config option order in defconfig for Crown Bay and Minnowmax

Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig'
result so that the config option order matches Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

tools: ifdtool: Write correct offset on 32-bit machine

On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff,
which is wrong for u-boot.rom components like u-boot-x86-16bit.bin.
Change to use strtoll() so that it works on both 32-bit and 64-bit
machines.

Reported-by: Fei Wang <wangfei.jimei@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

x86: Add binary blob checksums for Minnowboard MAX

To try to reduce the pain of confusion of binary blobs, add MD5 checksums
for the current versions. This may worsen the situation as new versions
appear, but it should still be possible to obtain these versions, and thus
get a working setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: x86: baytrail: Correct PCI region 3 when driver model is used

Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: x86: minnowmax: Move PCI to use driver model

Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>

x86: pci: Tidy up the generic x86 PCI driver

This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

x86: Add ROM image description for minnowmax

The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: spi: Enable environment for minnowmax

Enable a SPI environment and store it in a suitable place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

dm: spi: Correct BIOS protection logic for ICH9

The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>

dm: spi: Correct status register access width

The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

x86: Configure VESA parameters before loading Linux kernel

Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>

x86: crownbay: Enable graphics support

Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

x86: Remove MARK_GRAPHICS_MEM_WRCOMB

MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

x86: Move VGA option rom macros to Kconfig

Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

x86: cmd_mtrr: Improve MTRR list information

Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

x86: queensbay: Change CPU_ADDR_BITS to 32

Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

x86: Setup fixed range MTRRs for legacy regions

We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

video: Add 32-bit color depth support for VBE

The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

x86: bios: Allow pci config read/write to host bridge in int1a_handler

We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

x86: bios: Synchronize stack between real and protected mode

PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

video: vesa_fb: Look up VGA device by class instead of id

Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>