Alyssa Rosenzweig [Fri, 30 Jun 2023 15:29:35 +0000 (11:29 -0400)]
nir/opt_preamble: Move phis for movable if's
Add infrastructure to reconstruct if's. Later in the series, this will let us
hoist loads from inside uniform if's without speculating. For now, it lets us
handle phi's in nir_opt_preamble in a straightforward way.
Results on AGX are good:
total instructions in shared programs: 1504730 -> 1499674 (-0.34%)
instructions in affected programs: 153673 -> 148617 (-3.29%)
helped: 496
HURT: 0
Instructions are helped.
total bytes in shared programs:
10287768 ->
10238284 (-0.48%)
bytes in affected programs: 1113724 -> 1064240 (-4.44%)
helped: 496
HURT: 0
Bytes are helped.
total halfregs in shared programs: 452669 -> 452049 (-0.14%)
halfregs in affected programs: 14825 -> 14205 (-4.18%)
helped: 152
HURT: 99
Halfregs are helped.
total threads in shared programs:
16469504 ->
16470784 (<.01%)
threads in affected programs: 8960 -> 10240 (14.29%)
helped: 10
HURT: 0
Threads are helped.
Results on ir3 is a bit more of a wash but still should be a win overall: The
regression in moves seems scary, but the cost model already accounts for them as
evidenced by instruction count coming out ahead.
total instructions in shared programs: 3108750 -> 3105993 (-0.09%)
instructions in affected programs: 317367 -> 314610 (-0.87%)
helped: 675
HURT: 242
Instructions are helped.
total nops in shared programs: 673152 -> 675048 (0.28%)
nops in affected programs: 74551 -> 76447 (2.54%)
helped: 353
HURT: 347
Inconclusive result (%-change mean confidence interval includes 0).
total non-nops in shared programs: 2435598 -> 2430945 (-0.19%)
non-nops in affected programs: 232664 -> 228011 (-2.00%)
helped: 816
HURT: 38
Non-nops are helped.
total mov in shared programs: 78201 -> 84011 (7.43%)
mov in affected programs: 10726 -> 16536 (54.17%)
helped: 60
HURT: 781
Mov are HURT.
total cov in shared programs: 74964 -> 74906 (-0.08%)
cov in affected programs: 273 -> 215 (-21.25%)
helped: 17
HURT: 0
Cov are helped.
total dwords in shared programs: 6716814 -> 6748726 (0.48%)
dwords in affected programs: 879778 -> 911690 (3.63%)
helped: 12
HURT: 948
Dwords are HURT.
total full in shared programs: 193210 -> 193212 (<.01%)
full in affected programs: 278 -> 280 (0.72%)
helped: 12
HURT: 22
Inconclusive result (value mean confidence interval includes 0).
total constlen in shared programs: 493632 -> 494816 (0.24%)
constlen in affected programs: 19904 -> 21088 (5.95%)
helped: 9
HURT: 306
Constlen are HURT.
total cat0 in shared programs: 742476 -> 745046 (0.35%)
cat0 in affected programs: 84455 -> 87025 (3.04%)
helped: 277
HURT: 489
Cat0 are HURT.
total cat1 in shared programs: 153303 -> 159059 (3.75%)
cat1 in affected programs: 17810 -> 23566 (32.32%)
helped: 69
HURT: 780
Cat1 are HURT.
total cat2 in shared programs: 1144508 -> 1140731 (-0.33%)
cat2 in affected programs: 121284 -> 117507 (-3.11%)
helped: 841
HURT: 0
Cat2 are helped.
total cat3 in shared programs: 942098 -> 934804 (-0.77%)
cat3 in affected programs: 87140 -> 79846 (-8.37%)
helped: 855
HURT: 1
Cat3 are helped.
total cat4 in shared programs: 65261 -> 65249 (-0.02%)
cat4 in affected programs: 42 -> 30 (-28.57%)
helped: 12
HURT: 0
Cat4 are helped.
total sstall in shared programs: 237311 -> 241281 (1.67%)
sstall in affected programs: 33755 -> 37725 (11.76%)
helped: 179
HURT: 493
Sstall are HURT.
total (ss) in shared programs: 58166 -> 58795 (1.08%)
(ss) in affected programs: 4535 -> 5164 (13.87%)
helped: 35
HURT: 664
(ss) are HURT.
total systall in shared programs: 503784 -> 503805 (<.01%)
systall in affected programs: 3170 -> 3191 (0.66%)
helped: 16
HURT: 13
Inconclusive result (value mean confidence interval includes 0).
total (sy) in shared programs: 27261 -> 27259 (<.01%)
(sy) in affected programs: 76 -> 74 (-2.63%)
helped: 8
HURT: 5
Inconclusive result (value mean confidence interval includes 0).
total waves in shared programs: 439848 -> 439872 (<.01%)
waves in affected programs: 160 -> 184 (15.00%)
helped: 12
HURT: 0
Waves are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>
Alyssa Rosenzweig [Fri, 30 Jun 2023 17:01:06 +0000 (13:01 -0400)]
nir/opt_preamble: Unify foreach_use logic
Deduplication in prep for reconstructing if's.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>
Alyssa Rosenzweig [Fri, 30 Jun 2023 18:21:29 +0000 (14:21 -0400)]
nir/opt_preamble: Preserve IR when replacing phis
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>
Alyssa Rosenzweig [Mon, 26 Jun 2023 21:38:30 +0000 (17:38 -0400)]
nir/opt_preamble: Walk cf_list manually
The way backends walk NIR when translating. This will make it easy to filter
can_move based on the parent control flow.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>
Alyssa Rosenzweig [Tue, 18 Jul 2023 20:19:03 +0000 (16:19 -0400)]
ir3: Model cost of phi nodes for opt_preamble
It can be beneficial to move phi nodes, even though they can often be coalesced.
Model this cost so nir_opt_preamble can make good decisions about hoisting phi
nodes (and by extension, if-statements) into the preamble.
At this point in the series, this has no effect, but it will avoid certain
shader-db regressions associated with the nir_opt_preamble changes later in the
series.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>
Alyssa Rosenzweig [Fri, 30 Jun 2023 13:46:45 +0000 (09:46 -0400)]
ir3: Set CAN_SPECULATE before opt_preamble
Speculating these loads is safe, but nir_opt_preamble doesn't know that. Set the
ACCESS bits appropriately to let it know.
This will avoid any code gen regression from the nir_opt_preamble change.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>
Alyssa Rosenzweig [Fri, 30 Jun 2023 13:10:56 +0000 (09:10 -0400)]
nir: Add ACCESS_CAN_SPECULATE
Determining whether it is safe to hoist a load instruction out of control flow
depends on complex hardware and driver details. Rather than encoding this as
knobs in every NIR pass that wants to do so (notably nir_opt_preamble and
nir_opt_peephole_select), add a per-load ACCESS flag for backends to set.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>
Jani Nikula [Tue, 10 Oct 2023 07:17:46 +0000 (09:17 +0200)]
docs/vulkan: fixup some typos
The type is called vk_object_base, not vk_vk_objet_base... This should
fix the cross-referencing of this type.
Fixes:
f6d4641433e ("vulkan,docs: Document vk_instance")
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25634>
David Heidelberg [Sun, 8 Oct 2023 21:09:33 +0000 (23:09 +0200)]
ci/traces: rename upload function to reflect it works with S3
Cosmetic change.
Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25606>
David Heidelberg [Sun, 8 Oct 2023 20:34:32 +0000 (22:34 +0200)]
ci/traces: keep images for every job except the performance testing
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8354
Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25606>
David Heidelberg [Sun, 8 Oct 2023 20:01:50 +0000 (22:01 +0200)]
ci/traces: upload only missing trace images
Right now, S3 always returns something, so we need to check
the content-type .
Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25606>
Samuel Pitoiset [Tue, 10 Oct 2023 11:09:43 +0000 (13:09 +0200)]
zink: use warn_missing_feature for missing modifier support
To avoid spamming VKCTS output.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25636>
Erik Faye-Lund [Tue, 10 Oct 2023 10:10:08 +0000 (12:10 +0200)]
ci/etnaviv: allow failure on failing test
This test has been failing every nightly pipeline on the CI for a long,
long time. It seems nobody is currently interested in fixing it, so
let's just allow the failure for now.
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/9967
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25635>
Erik Faye-Lund [Tue, 10 Oct 2023 10:09:47 +0000 (12:09 +0200)]
ci/etnaviv: update ci expectation
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25635>
Danylo Piliaiev [Fri, 6 Oct 2023 14:54:21 +0000 (16:54 +0200)]
tu: Zero init tu_render_pass and tu_subpass for dynamic rendering
The way we init render pass related structures is dangerous with when
structs are not zero initialized - too easy to miss a field. There
were already at least two issues with it.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25592>
Danylo Piliaiev [Fri, 6 Oct 2023 14:46:59 +0000 (16:46 +0200)]
tu: Fix stale tu_render_pass_attachment::store_stencil with dyn rendering
Attachment initialization helpers expect zeroed memory by default.
Fixes a hang when running Subnautica with TU_DEBUG="gmem".
See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8702#note_1932003
Fixes:
ed125e6cca188275631641784fcf3ddcbcfef193
("tu: Initial support for dynamic rendering")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25592>
Alyssa Rosenzweig [Mon, 14 Aug 2023 14:38:03 +0000 (10:38 -0400)]
nir: Use a tagged pointer for nir_src parents
This allows us to pack the is_if boolean into the bottom bit of the parent
pointer, eliminating the boolean and hence shrinking the nir_src by 8 bytes (due
to the extra 63 bits of padding incurred in the old layout).
Because all access is forced through helpers now, this is a local change.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
Alyssa Rosenzweig [Mon, 14 Aug 2023 14:41:23 +0000 (10:41 -0400)]
nir: Assert the nir_src union is used safely
It is undefined behaviour in C to read a different member of a union than was
written. Nothing in-tree should be using this behaviour with the nir_src union:
nir_if should never be read as nir_instr and vice versa. Assert this.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
Alyssa Rosenzweig [Mon, 14 Aug 2023 13:58:47 +0000 (09:58 -0400)]
nir: Use getters for nir_src::parent_*
First, we need to give the parent_instr field a unique name to be able to
replace with a helper. We have parent_instr fields for both nir_src and
nir_def, so let's rename nir_src::parent_instr in preparation for rework.
This was done with a combination of sed and manual fix-ups.
Then we use semantic patches plus manual fixups:
@@
expression s;
@@
-s->renamed_parent_instr
+nir_src_parent_instr(s)
@@
expression s;
@@
-s.renamed_parent_instr
+nir_src_parent_instr(&s)
@@
expression s;
@@
-s->parent_if
+nir_src_parent_if(s)
@@
expression s;
@@
-s.renamed_parent_if
+nir_src_parent_if(&s)
@@
expression s;
@@
-s->is_if
+nir_src_is_if(s)
@@
expression s;
@@
-s.is_if
+nir_src_is_if(&s)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
Alyssa Rosenzweig [Mon, 14 Aug 2023 14:35:43 +0000 (10:35 -0400)]
nir: Use set_parent_instr internally
This properly clears is_if.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
Alyssa Rosenzweig [Mon, 14 Aug 2023 14:33:18 +0000 (10:33 -0400)]
nir: Add trivial nir_src_* getters
These will become nontrivial later in the series. For now these have no smarts
in them, in order to make the conversion completely mechanical.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
Alyssa Rosenzweig [Tue, 15 Aug 2023 13:59:01 +0000 (09:59 -0400)]
lima/pp: Do not use union undefined behaviour
It is invalid to read parent_instr for an if-use (or parent_if for a
non-if-use). Make sure we read the right one when handling if-uses.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>
Samuel Pitoiset [Fri, 6 Oct 2023 10:04:50 +0000 (12:04 +0200)]
radv: fix IB alignment
This re-introduces "radv: fix alignment of DGC command buffers" and
"radv/amdgpu: fix alignment of command buffers" which were valid
changes.
IBs need to be aligned to the IB size requirement, not the number of
padded NOPs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25588>
Dave Airlie [Mon, 9 Oct 2023 04:52:22 +0000 (14:52 +1000)]
lavapipe: expose planar ycbcr formats and new ycbcr features
This enables some extensions and a bunch of formats for ycbcr
support.
dEQP-VK.api.info.format_properties.g8_b8_r8_3plane_420_unorm,Fail
dEQP-VK.api.info.format_properties.g8_b8r8_2plane_420_unorm,Fail
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 06:52:48 +0000 (16:52 +1000)]
lavapipe: handle planes in texture lowering.
This uses the descriptor set info to lower the texture/sampler
handlers properly using the stride.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 06:22:51 +0000 (16:22 +1000)]
lavapipe: add descriptor sets bindings for planar images
This adds strided descriptor bindings that are used to handle
planar image/samplers.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 06:07:38 +0000 (16:07 +1000)]
lavapipe: handle planes in get image sub resource
image sub resources need to take planes into account in the calculations.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 05:53:35 +0000 (15:53 +1000)]
lavapipe: handle planes in copies
This adds plane support to the various copy paths.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 05:37:38 +0000 (15:37 +1000)]
lavapipe: allocate image and image view planes.
This allocate planes and handles disjoint.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 05:15:05 +0000 (15:15 +1000)]
lavapipe: start introducing planes structure.
this just introduces a single plane and refactors code to use it.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Mon, 9 Oct 2023 04:13:36 +0000 (14:13 +1000)]
lavapipe: cleanup copy code to use a local region variable.
This should make no functional difference, except cleanup the code.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 08:21:33 +0000 (18:21 +1000)]
lavapipe: convert sampler to use vk base class.
This just makes things a bit cleaner, and reuses the common code.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Tue, 26 Sep 2023 03:11:53 +0000 (13:11 +1000)]
llvmpipe: don't support planar formats for buffers.
This stops lavapipe exposing incorrect support.
Cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Tue, 26 Sep 2023 02:55:21 +0000 (12:55 +1000)]
lavapipe: don't emit blit src/dst for subsampled formats.
Fixes dEQP-VK.api.info.format_properties.b8g8r8g8_422_unorm
Cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 02:56:39 +0000 (12:56 +1000)]
llvmpipe: don't create texture functions for planar textures.
Since we can't sample from these directly, just don't create the
functions.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 01:22:50 +0000 (11:22 +1000)]
lavapipe: support host image copying on compressed texture formats
dEQP-VK.image.host_image_copy.query.linear.bc5_snorm_block,Fail
dEQP-VK.image.host_image_copy.query.linear.bc7_unorm_block,Fail
dEQP-VK.image.host_image_copy.query.optimal.bc5_snorm_block,Fail
dEQP-VK.image.host_image_copy.query.optimal.bc7_unorm_block,Fail
Fixes:
9e9d90c6c381 ("lavapipe: VK_EXT_host_image_copy")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Fri, 6 Oct 2023 00:49:29 +0000 (10:49 +1000)]
lavapipe: fix subresource layers asserts
dEQP-VK.api.copy_and_blit.copy_commands2.blit_image.simple_tests.array.all_remaining_layers
Fixes:
35c02f79c9b82b5 ("lavapipe: add some asserts for blit region extents")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Dave Airlie [Mon, 9 Oct 2023 05:56:20 +0000 (15:56 +1000)]
lavapipe: fix some whitespace in advance of other changes.
This is just some tab and trailing whitespace removal.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>
Qiang Yu [Thu, 17 Aug 2023 03:11:19 +0000 (11:11 +0800)]
radeonsi: enable aco compile for part mode ps
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Thu, 17 Aug 2023 03:06:11 +0000 (11:06 +0800)]
radeonsi: add ps epilog shader part build
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Fri, 11 Aug 2023 09:26:37 +0000 (17:26 +0800)]
radeonsi: fill aco shader info for ps part
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Fri, 11 Aug 2023 09:21:27 +0000 (17:21 +0800)]
radeonsi: extract si_get_ps_epilog_args to be shared with aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Thu, 10 Aug 2023 02:19:33 +0000 (10:19 +0800)]
radeonsi: add ps prolog shader part build
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Mon, 7 Aug 2023 07:18:12 +0000 (15:18 +0800)]
ac,radeonsi: remove unused ps prolog key fields
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Mon, 7 Aug 2023 06:28:50 +0000 (14:28 +0800)]
radeonsi: extract si_get_ps_prolog_args to be shared with aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Mon, 7 Aug 2023 06:25:14 +0000 (14:25 +0800)]
radeonsi: extract si_prolog_get_internal_binding_slot
To be shared with ps prolog.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Sun, 6 Aug 2023 09:19:46 +0000 (17:19 +0800)]
radeonsi: init spi_ps_input_addr for part mode ps
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Sun, 6 Aug 2023 03:12:17 +0000 (11:12 +0800)]
radeonsi: reduce sgpr count for scratch_offset when aco
aco add scratch_offset to shader args explicitly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
Qiang Yu [Sat, 19 Aug 2023 07:36:00 +0000 (15:36 +0800)]
aco: wait memory ops done before go to next shader part
Next part don't know whether p_end_with_regs args are loaded from
memory ops or not, need to wait it's done here.
Other memory load needs to be waited too like:
a = load_mem()
b = ...
if (...) {
wait_mem(a)
store_mem(a)
}
p_end_with_regs(b)
"a" still needs to be waited, otherwise next shader part regs may
be overwritten by unfinished memory loads.
Memory stores are waited too. When >=gfx10 and last VGT has no
parameter export, we need to wait all memeory stores done before
pos export (see ac_nir_export_position). So when merged shader
(ES+GS or VS+GS) is partially built, first stage needs to wait
all memory stores done, otherwise second stage don't know if
any memory stores pending before.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Signe-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Thu, 24 Aug 2023 02:11:40 +0000 (10:11 +0800)]
aco: create exit block for p_end_with_regs to branch to
To handle ps discard in radeonsi part mode shader.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Mon, 21 Aug 2023 02:44:45 +0000 (10:44 +0800)]
aco: fix assertion fail when program contains empty block
radeonsi may generate empty main shader or an empty exit block
for p_end_with_regs to jump to.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Thu, 17 Aug 2023 07:17:20 +0000 (15:17 +0800)]
aco: do not fix_exports when program has epilog
PS with epilog does not need to fix_exports. And radeonsi use
p_end_with_regs so does not have jump instruction at last.
radeonsi may also have exec restore instruction, so may break
before reach to p_end_with_regs.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Sat, 19 Aug 2023 03:20:00 +0000 (11:20 +0800)]
aco,radv,radeonsi: pass spi ps input ena and addr
radeonsi may pass different ena and addr when part mode shader.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Fri, 25 Aug 2023 08:39:19 +0000 (16:39 +0800)]
aco: compact ps expilog color export for radeonsi
radeonsi need to compact color export for ps epilog while radv does not.
radv will fill empty color slot, so won't affected by this change.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Thu, 17 Aug 2023 02:13:26 +0000 (10:13 +0800)]
aco,radv: add radeonsi spec ps epilog code
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Tue, 15 Aug 2023 09:27:48 +0000 (17:27 +0800)]
aco: simplify export_fs_mrt_color
It's now used by ps epilog only.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Mon, 14 Aug 2023 09:05:32 +0000 (17:05 +0800)]
aco,radv: rename ps epilog info inputs to colors
Will add other mrtz args for radeonsi.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Mon, 14 Aug 2023 01:43:18 +0000 (09:43 +0800)]
aco,radv: remove unused ps epilog info fields
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Fri, 11 Aug 2023 08:58:36 +0000 (16:58 +0800)]
aco: add create_fs_end_for_epilog for radeonsi
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Fri, 11 Aug 2023 01:57:42 +0000 (09:57 +0800)]
aco: handle ps outputs from radeonsi
radeonsi will keep outputs <FRAG_RESULT_DATA0.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Wed, 9 Aug 2023 07:07:39 +0000 (15:07 +0800)]
aco: add ps prolog generation for radeonsi
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Fri, 25 Aug 2023 06:25:20 +0000 (14:25 +0800)]
aco: remove p_end_with_regs from needs_exact()
ps needs to handle wqm:
1. main part may compute with args from prolog in wqm mode, so
prolog need to compute these args in wqm mode too.
2. prolog and main part need to end with exact exec, so next
shader part which inherit previous shader part's exec won't
do valid job for helper threads
1 need p_end_with_regs to operate in wqm mode and itself can't
be exact, otherwise some move instruction added by it won't be
in wqm mode so helper threads' compute result is not passed to
next shader part as args.
2 is done by p_end_wqm added by finish_program automatically
after p_end_with_regs.
Piglit tests can trigger the problem:
1. gl-2.1-polygon-stipple-fs
a. ps prolog call discard_if
b. ps main pass wqm exec to epilog
c. ps epilog export color for discarded pixel
2. fs-fwidth-color.shader_test
a. ps prolog need to pass args computed in wqm mode
b. set p_end_with_regs to exact will end wqm mode before
the move instructions, so helper threads's result is not
passed to next shader part
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Fri, 15 Sep 2023 08:42:25 +0000 (16:42 +0800)]
aco: do not eliminate final exec write when p_end_with_regs block
p_end_with_regs just partially end the program, next part need
exec mask to be set correctly. For example p_end_wqm will generate
a exec restore from WQM mode after p_end_with_regs.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Qiang Yu [Tue, 8 Aug 2023 05:14:19 +0000 (13:14 +0800)]
ac,radeonsi: move ps arg pos_fixed_pt to ac_shader_args
It's a HW init reg, not driver spec user sgpr. radv just
doesn't use it. Move it to amd common for aco ps prolog
usage.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
Yiwei Zhang [Mon, 9 Oct 2023 07:28:17 +0000 (00:28 -0700)]
venus: make device memory alloc async
Add a new perf option NO_ASYNC_MEM_ALLOC. Track the ring seqno of the
memory alloc command, and do async ring wait to ensure:
- memory allocation is before resource creation
- memory import is before resource destroy
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25611>
Yiwei Zhang [Sun, 8 Oct 2023 08:13:08 +0000 (01:13 -0700)]
venus: refactor vn_device_memory to prepare for async alloc
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25611>
Yiwei Zhang [Sat, 9 Sep 2023 08:01:30 +0000 (01:01 -0700)]
venus: track VkPhysicalDeviceMemoryProperties instead
For code simplicity.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25611>
Yiwei Zhang [Thu, 5 Oct 2023 07:33:29 +0000 (00:33 -0700)]
venus: remove redundant bo roundtrip and add more docs
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25611>
Emma Anholt [Mon, 9 Oct 2023 23:57:24 +0000 (16:57 -0700)]
ci/crocus: Disable flaky unvanquished-ultra trace
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25626>
Emma Anholt [Mon, 9 Oct 2023 23:50:51 +0000 (16:50 -0700)]
ci/zink: Skip dmat[34] op tests in general, as well
More "make full-run zink CI take less time". You still get dmat2 to see
if double matrices work at all.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25626>
Emma Anholt [Mon, 9 Oct 2023 23:45:58 +0000 (16:45 -0700)]
ci/zink: Skip 3-minute-long glx-visuals timeouts.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25626>
Emma Anholt [Mon, 9 Oct 2023 23:44:08 +0000 (16:44 -0700)]
ci/crocus: Generalize the drawarrays-vertex-count flakes.
We just got it for triangle fan as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25626>
Iván Briano [Tue, 19 Sep 2023 00:39:40 +0000 (17:39 -0700)]
nir: round f2f16{_rtne/_rtz} correctly for constant expressions
As noted in the previous commit, the intermediate cast to float from
double can produce wrong results.
Fixes upcoming Vulkan CTS tests:
dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp16.input_args.rounding_rte_sconst_conv_from_fp64_up
dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp16.input_args.rounding_rte_sconst_conv_from_fp64_up_nostorage
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp16.input_args.rounding_rte_sconst_conv_from_fp64_up_vert
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp16.input_args.rounding_rte_sconst_conv_from_fp64_up_nostorage_vert
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp16.input_args.rounding_rte_sconst_conv_from_fp64_up_frag
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp16.input_args.rounding_rte_sconst_conv_from_fp64_up_nostorage_frag
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25281>
Iván Briano [Tue, 19 Sep 2023 00:27:56 +0000 (17:27 -0700)]
util: add double_to_float16 helpers
We convert from doubles to half by going through float in between, but
as noted in the comment in this commit, that can give wrong results in
some cases.
Add some helpers to ensure correct results based on rounding mode that
will be used in the next commit.
v2: Use fi/di from u_math.h (Ian)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25281>
Iván Briano [Fri, 15 Sep 2023 01:09:07 +0000 (18:09 -0700)]
intel/compiler: round f2f16 correctly for RTNE case
v2: bcsel -> b2i32 (Ian)
Fixes upcoming Vulkan CTS tests:
dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp16.input_args.rounding_rte_conv_from_fp64_up
dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp16.input_args.rounding_rte_conv_from_fp64_up_nostorage
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp16.input_args.rounding_rte_conv_from_fp64_up_vert
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp16.input_args.rounding_rte_conv_from_fp64_up_nostorage_vert
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp16.input_args.rounding_rte_conv_from_fp64_up_frag
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp16.input_args.rounding_rte_conv_from_fp64_up_nostorage_frag
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25281>
Iván Briano [Thu, 14 Sep 2023 19:15:20 +0000 (12:15 -0700)]
nir/lower_int64: respect rounding mode when casting to float
Appendix A: Vulkan environemtn for SPIR-V says:
Operations described as “correctly rounded” will return the infinitely
precise result, x, rounded so as to be representable in
floating-point. The rounding mode is not specified, unless the entry
point is declared with the RoundingModeRTE or the RoundingModeRTZ
Execution Mode.
Conversion between types are classified as correctly rounded, so let's
do rounding correctly.
v2: check rounding mode for destination bit size (Georg)
Fixes upcoming Vulkan CTS tests:
dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp32.input_args.rounding_rtz_conv_from_uint64_up
dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp32.input_args.rounding_rtz_conv_from_int64_up
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp32.input_args.rounding_rtz_conv_from_uint64_up_vert
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp32.input_args.rounding_rtz_conv_from_int64_up_vert
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp32.input_args.rounding_rtz_conv_from_uint64_up_frag
dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp32.input_args.rounding_rtz_conv_from_int64_up_frag
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25281>
Iván Briano [Fri, 15 Sep 2023 21:34:31 +0000 (14:34 -0700)]
vulkan/runtime: add internal parameter to vk_spirv_to_nir
If used to compile internal shaders, it will lack the flag while running
through all the optimization passes it does.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25281>
José Roberto de Souza [Tue, 3 Oct 2023 19:58:40 +0000 (12:58 -0700)]
iris: Nuke useless flags from iris_fine_fence_new()
Only IRIS_FENCE_TOP_OF_PIPE was changing the PIPE_CONTROL flags but it
was not set in any caller.
So we can remove IRIS_FENCE_* and flags from iris_fine_fence struct.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25571>
José Roberto de Souza [Tue, 3 Oct 2023 15:54:35 +0000 (08:54 -0700)]
iris: Lock bufmgr->lock before call vma_free() in error path
vma_free() requires that bufmgr->lock is held.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25571>
Mike Blumenkrantz [Tue, 3 Oct 2023 14:40:11 +0000 (10:40 -0400)]
gbm: delete some zink handling
this has never been functional and may never be
Fixes:
d760a9151b7 ("gallium: Learn about kopper")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25526>
Mike Blumenkrantz [Tue, 3 Oct 2023 14:37:49 +0000 (10:37 -0400)]
zink: error at handle export on missing EXT_image_drm_format_modifier
this doesn't work anyway
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25526>
Mike Blumenkrantz [Tue, 3 Oct 2023 12:09:02 +0000 (08:09 -0400)]
egl: don't set ForceSoftware for all zink loading
sometimes this is desired, other times it isn't
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25526>
antonino [Mon, 9 Oct 2023 14:51:11 +0000 (16:51 +0200)]
nir: fix several crashes in `nir_lower_tex`
This patch fixes the following issues that lead to crashes in some cases:
* an instruction is inserted to get texture lod that depends on a
texture instruction that hasn't been inserted yet.
* this code tries to read channel 1 of the lod, but lod is scalar
* the code assumed there would only be 2 srcs, this isn't the case when
bindless is used.
Fixes:
b154a4154b4 ("nir/lower_tex: rewrite tex/txb -> txd/txl before saturating srcs")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25621>
Emma Anholt [Tue, 3 Oct 2023 19:56:28 +0000 (12:56 -0700)]
i915: Use nir_group_loads() to reduce texture indirection phases.
total instructions in shared programs: 467049 -> 467040 (<.01%)
instructions in affected programs: 573 -> 564 (-1.57%)
total tex_indirect in shared programs: 14133 -> 14019 (-0.81%)
tex_indirect in affected programs: 491 -> 377 (-23.22%)
total temps in shared programs: 28543 -> 29178 (2.22%)
temps in affected programs: 3307 -> 3942 (19.20%)
LOST: 0
GAINED: 65
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25533>
Emma Anholt [Tue, 3 Oct 2023 18:46:55 +0000 (11:46 -0700)]
i915: Make exceeding tex indirect count fatal.
The HW should fail to run shaders that have too many phases, so do this so
that we get link failures.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25533>
Emma Anholt [Tue, 3 Oct 2023 19:53:24 +0000 (12:53 -0700)]
i915: Do a test compile at glLinkShader() time.
This lets us throw errors back to the app for shaders that are too
complex. The X server would really like to have this instead of guessing
based on renderer strings when shaders might be too complicated.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25533>
Emma Anholt [Tue, 3 Oct 2023 19:25:42 +0000 (12:25 -0700)]
i915: Save fragment program compile error messages in the fragment shader.
We'll want this for doing linking failure messages for shaders that are
too long.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25533>
Emma Anholt [Tue, 3 Oct 2023 19:13:36 +0000 (12:13 -0700)]
i915: Don't log I915_DEBUG=fs output for blit shaders.
Unless you have NIR_DEBUG=print_internal, the rest of the shader debug
pipeline is also hidden. Cleans up output when looking at shader-db
compiles.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25533>
Emma Anholt [Tue, 3 Oct 2023 18:45:22 +0000 (11:45 -0700)]
i915: Print the relevant counts vs limits when throwing errors.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25533>
Emma Anholt [Tue, 3 Oct 2023 18:42:34 +0000 (11:42 -0700)]
i915: Re-clang-format and enforce it in CI.
I want to be able to mash the format button at any point when hacking on
this thing instead of doing bespoke whitespace.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25533>
Karmjit Mahil [Fri, 22 Sep 2023 09:11:09 +0000 (10:11 +0100)]
pvr: Adjust EOT PBE state to account for the iview's base array layer
Fixes various dEQP array tests.
E.g.
dEQP-VK.pipeline.monolithic.framebuffer_attachment
.1d_array_32_64_4
Reported-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25348>
Karmjit Mahil [Thu, 21 Sep 2023 14:16:09 +0000 (15:16 +0100)]
pvr: Use the render passes' attachments array to setup ISP state
`pvr_setup_isp_faces_and_control()` can be called from a secondary
command buffer. The render pass info's `attachments` array is only
populated in the primary command buffer on which the render pass
was started, thus the `ds_aspect` being used always ended up being
`0` leading to incorrect ISP state being setup.
This commit changes the function to use the `attachments` array
from the render pass struct instead of the one from the recording
state.
dEQP tests fixed:
dEQP-VK.renderpass.suballocation.attachment
.{1.13, 1.65, 1.74, 3.219, 3.236, 3.314, 3.385, 4.426}
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25351>
Lionel Landwerlin [Mon, 9 Oct 2023 14:20:12 +0000 (17:20 +0300)]
anv: flag 3DSTATE_RASTER as dirty after simple shader primitive
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9899
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25618>
Lionel Landwerlin [Mon, 9 Oct 2023 14:05:39 +0000 (17:05 +0300)]
anv: fix a couple of missing input for 3DSTATE_RASTER programming
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25618>
Lionel Landwerlin [Mon, 9 Oct 2023 13:50:13 +0000 (16:50 +0300)]
anv: add missing workaround handling in simple shader
It's not going to make any real difference because of the type of
primitive used, but it feels safer to have this everywhere after a
3DPRIMITIVE.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25618>
Lionel Landwerlin [Mon, 9 Oct 2023 10:37:18 +0000 (13:37 +0300)]
anv: implement INTEL_DEBUG=reemit
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25618>
Karmjit Mahil [Tue, 19 Sep 2023 16:08:41 +0000 (17:08 +0100)]
pvr: Fix cubemap layer stride
The hw calculates the layer stride with the assumption of a full
mip chain being there even though certain levels might never be
used.
Fix the `layer_size` by accounting for any missing mip levels.
Fixes:
8991e6464 ("pvr: Add a Vulkan driver for Imagination Technologies PowerVR Rogue GPUs")
Reported-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25344>
SoroushIMG [Sat, 17 Jun 2023 12:59:00 +0000 (13:59 +0100)]
pvr: fix mipmap size calculation for bc formats
The block size given by vk_format_get_blocksize is in blocks, not
texels.
dEQP tests affected:
dEQP-VK.pipeline.monolithic.image_view.view_type*
.format.eac*lod_base_mip_level
Fixes:
8991e6464 ("pvr: Add a Vulkan driver for Imagination Technologies PowerVR Rogue GPUs")
Signed-off-by: SoroushIMG <soroush.kashani@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25344>
Erik Faye-Lund [Fri, 6 Oct 2023 09:03:55 +0000 (11:03 +0200)]
docs: use html_static_path for static files
I'm not sure why I picked html_extra_path instead, as it's meant for
slightly less directly related files than what html_static_path is for.
So let's switch. It shouldn't make much of a real-world difference, but
should make it a bit easier to understand what this is about.
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25585>
Erik Faye-Lund [Fri, 6 Oct 2023 09:29:46 +0000 (11:29 +0200)]
docs: only link to old docs from html
Only the HTML builder knows about these files, so we can't really link
to them when using other builders. This only matter to the link-checker
right now, because that's the only other builder we use.
It's a bit sad that we can't linkcheck files like these, but it doesn't
work either way. Another way of making it work could be to use the
download-role for these files. I'm not sure I think that's any better,
as that makes the code read a bit more confusingly to me; the intent
isn't to *download* the files, but to view them as raw-text.
I could go either way here, though. Neither is fantastic IMO, but
neither is a disaster either.
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25585>
projects / platform / upstream / mesa.git / log