Kadir Cetinkaya [Fri, 18 Oct 2019 12:57:11 +0000 (14:57 +0200)]
[clangd] Store Index in Tweak::Selection
Summary:
Incoming define out-of-line tweak requires access to index.
This patch simply propogates the index in ClangdServer to Tweak::Selection while
passing the AST. Also updates TweakTest to accommodate this change.
Reviewers: ilya-biryukov
Subscribers: MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69165
Kadir Cetinkaya [Wed, 25 Sep 2019 09:35:38 +0000 (11:35 +0200)]
[clangd] Implement GetEligiblePoints
Summary:
This is an helper for incoming move definition out-of-line action to
figure out possible insertion locations for definition of a qualified name.
Reviewers: hokein, ilya-biryukov
Subscribers: MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D68024
LLVM GN Syncbot [Fri, 25 Oct 2019 10:01:34 +0000 (10:01 +0000)]
gn build: Merge
74d39a42f10
Kadir Cetinkaya [Fri, 6 Sep 2019 07:49:40 +0000 (09:49 +0200)]
[clangd] DefineInline action apply logic with fully qualified names
Summary:
Initial version of DefineInline action that will fully qualify every
name inside function body.
Reviewers: sammccall, ilya-biryukov, hokein
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66647
Kadir Cetinkaya [Thu, 5 Sep 2019 12:10:43 +0000 (14:10 +0200)]
[clangd] DefineInline action availability checks
Summary:
Introduces DefineInline action and initial version of
availability checks.
Reviewers: sammccall, ilya-biryukov, hokein
Tags: #clang
Differential Revision: https://reviews.llvm.org/D65433
georgerim [Fri, 25 Oct 2019 09:28:33 +0000 (12:28 +0300)]
[obj2yaml] - Better dumping for relocations without symbols associated.
This just reorders the code and removes an assignment
of an empty string for the case when a relocation has
no symbol associated. With this our output becomes
cleaner and shorter.
Differential revision: https://reviews.llvm.org/D69255
georgerim [Fri, 25 Oct 2019 08:55:11 +0000 (11:55 +0300)]
[llvm/Object] - Fix the error message reported for a broken SHT_SYMTAB_SHNDX section.
SHT_SYMTAB_SHNDX should have the same number of entries as the symbol table
associated (https://www.sco.com/developers/gabi/latest/ch4.sheader.html)
We currently can report the following message:
"SHT_SYMTAB_SHNDX section has sh_size (24) which is not equal to the number of symbols (2)"
It is just broken. This patch refines/fixes it.
Differential revision: https://reviews.llvm.org/D69305
David Stenberg [Fri, 25 Oct 2019 09:21:11 +0000 (11:21 +0200)]
Fix a variable typo in LiveDebugValues [NFC]
Simon Atanasyan [Fri, 25 Oct 2019 09:16:22 +0000 (12:16 +0300)]
[docs] Update Mips feature table in CodeGenerator.rst
Patch by Miloš Stojanović
Differential Revision: https://reviews.llvm.org/D69381
Simon Tatham [Fri, 25 Oct 2019 08:14:14 +0000 (09:14 +0100)]
Fix file-ordering nit in D67161.
Re-sorted the module names in clang/utils/TableGen/CMakeLists.txt back
into alphabetical order.
czhengsz [Fri, 25 Oct 2019 08:13:30 +0000 (04:13 -0400)]
[PowerPC] [Peephole] fold frame offset by using index form to save add.
renamable $x6 = ADDI8 $x1, -80 ;;; 0 is replaced with -80
renamable $x6 = ADD8 killed renamable $x6, renamable $x5
STW killed renamable $r3, 4, killed renamable $x6 :: (store 4 into %ir.14, !tbaa !2)
After PEI there is a peephole opt opportunity to combine above -80 in ADDI8 with 4 in the STW to eliminate unnecessary ADD8.
Expected result:
renamable $x6 = ADDI8 $x1, -76
STWX killed renamable $r3, renamable $x5, killed renamable $x6 :: (store 4 into %ir.6, !tbaa !2)
Reviewed by: stefanp
Differential Revision: https://reviews.llvm.org/D66329
Michał Górny [Thu, 24 Oct 2019 17:47:49 +0000 (19:47 +0200)]
[lldb] [Host/netbsd] Set Arg0 for 'platform process list -v'
Differential Revision: https://reviews.llvm.org/D69400
Djordje Todorovic [Thu, 24 Oct 2019 08:08:43 +0000 (10:08 +0200)]
[LiveDebugValues] Small code clean up; NFC
Tom Stellard [Fri, 25 Oct 2019 07:04:31 +0000 (00:04 -0700)]
git-llvm: Drop dependency on github module
This was required for blocking merge commits, but now that we have
branch protections, we don't need this.
Tom Stellard [Fri, 25 Oct 2019 06:53:59 +0000 (23:53 -0700)]
git-llvm: Push to master branch by default
This allows pushing without specifying a branch, which is what the
documentations says to do.
LLVM GN Syncbot [Fri, 25 Oct 2019 06:36:53 +0000 (06:36 +0000)]
gn build: Merge
ffa214ef228
LLVM GN Syncbot [Fri, 25 Oct 2019 06:36:53 +0000 (06:36 +0000)]
gn build: Merge
d0bd3fc88be
LLVM GN Syncbot [Fri, 25 Oct 2019 06:36:52 +0000 (06:36 +0000)]
gn build: Merge
bb6a27fc257
Nico Weber [Fri, 25 Oct 2019 06:35:14 +0000 (02:35 -0400)]
gn build: (manually) merge
08074cc9
Michael Liao [Fri, 25 Oct 2019 05:05:34 +0000 (01:05 -0400)]
Fix compilation warning. NFC.
Michael Liao [Thu, 24 Oct 2019 15:41:11 +0000 (11:41 -0400)]
[hip] Allow the declaration of functions with variadic arguments in HIP.
Summary:
- As variadic parameters have the lowest rank in overload resolution,
without real usage of `va_arg`, they are commonly used as the
catch-all fallbacks in SFINAE. As the front-end still reports errors
on calls to `va_arg`, the declaration of functions with variadic
arguments should be allowed in general.
Reviewers: jlebar, tra, yaxunl
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69389
Craig Topper [Fri, 25 Oct 2019 03:29:45 +0000 (20:29 -0700)]
[X86][GISel] Remove unneeded custom selection code for handling shifts.
Tom Stellard [Thu, 24 Oct 2019 22:46:08 +0000 (15:46 -0700)]
docs: Update instructions for requesting commit access
Philip Reames [Fri, 25 Oct 2019 01:58:26 +0000 (18:58 -0700)]
[SCEV] Expose and use maximum constant exit counts for individual loop exits
We were already going to all of the trouble of computing maximum constant exit counts for each loop exit, we might as well expose them through the API. The change in IndVars is mostly to demonstrate that the wired up code works, but it als very slightly strengthens the transform. The strengthened case is rather narrow though: it requires one exactly analyzeable exit, one imprecisely analyzeable exit (with the upper bound less than the precise one), and one unanalyzeable exit. I coudn't construct a reasonably stable test case.
This does increase the memory usage of the BackedgeTakenCount by a factor of 2 in the worst case.
I also noticed the loop in IndVars is O(#Exits ^ 2). This doesn't change with this patch. A future patch will cache this result inside of SCEV to avoid requering.
David Blaikie [Fri, 25 Oct 2019 01:45:49 +0000 (18:45 -0700)]
Fix Clang -Wcovered-switch-default warning by moving llvm_unreachable default to after the switch
Kai Luo [Fri, 25 Oct 2019 01:36:55 +0000 (01:36 +0000)]
Test commit via git.
Michael Spencer [Fri, 25 Oct 2019 01:25:28 +0000 (18:25 -0700)]
[clang][DependencyScanning] clang-format.
Philip Reames [Fri, 25 Oct 2019 01:19:41 +0000 (18:19 -0700)]
[SCEV] Start reworking backedge taken count APIs to unify max handling [NFC]
This is a first step in figuring out a proper API for maximum (non constant) exit counts. This may evolve a bit as we get experience with the API needs; suggestions very welcome. This patch just tried to provide a framework that we can later add maximum too in a clean and obvious way.
Yuanfang Chen [Thu, 24 Oct 2019 19:31:40 +0000 (12:31 -0700)]
[clang][ThinLTO] Promote cc1 -fthin_link_bitcode to driver -fthinlto_link_bitcode
Summary:
A necessary step to let build system caching work for its output.
Reviewers: tejohnson, steven_wu
Reviewed by: tejohnson
Subscribers: mehdi_amini, inglorion, dexonsmith, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69406
Jordan Rupprecht [Thu, 24 Oct 2019 23:17:19 +0000 (16:17 -0700)]
Revert "Recommit "[Clang] Pragma vectorize_width() implies vectorize(enable)""
This reverts commit
80371c74ae63d2f260bcc75408be9c6f81e38465.
Given the following source:
```
void a() {
for (;;)
;
}
```
It incorrectly enables vectorization (with vector width 1), as well as generating a warning that vectorization could not be performed.
Petr Hosek [Thu, 24 Oct 2019 23:24:00 +0000 (16:24 -0700)]
[CMake] Update Fuchsia build configuration
This includes several changes to our toolchain build:
- Switch from RelWithDebInfo to Release as we don't currently use the
debug info and therefore don't need to produce it.
- Disable unwind tables since we don't need them.
- Disable Clang static analyzer and ARCMT since we don't use it.
- Disable Go tests since we don't distribute Go bindings.
- Set the deployment target for macOS to 10.7 to make the toolchain
usable on older systems.
- Restrict the targets we build runtimes for on Darwin only the ones
we actually need.
- Drop llc and opt from the distribution since we don't need them.
Differential Revision: https://reviews.llvm.org/D69415
Philip Reames [Thu, 24 Oct 2019 23:34:39 +0000 (16:34 -0700)]
[SCEV] Delete unused code from header
Michael Spencer [Thu, 10 Oct 2019 21:40:17 +0000 (14:40 -0700)]
[clang-scan-deps] Add basic support for modules.
This fixes two issues that prevent simple uses of modules from working.
* We would previously minimize _every_ file opened by clang, even module maps
and module pcm files. Now we only minimize files with known extensions. It
would be better if we knew which files clang intended to open as a source
file, but this works for now.
* We previously cached every lookup, even failed lookups. This is a problem
because clang stats the module cache directory before building a module and
creating that directory. If we cache that failure then the subsequent pcm
load doesn't see the module cache and fails.
Overall this still leaves us building minmized modules on disk during scanning.
This will need to be improved eventually for performance, but this is correct,
and works for now.
Differential Revision: https://reviews.llvm.org/D68835
Jinsong Ji [Thu, 24 Oct 2019 22:07:53 +0000 (22:07 +0000)]
[clang]Fixup clang -Werror,,-Wcovered-switch-default build failures
llvm/clang/lib/CodeGen/CGBuiltin.cpp:6877:3: error: default label in
switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
Similar to
https://reviews.llvm.org/rG7b3de1e811972b874d91554642ccb2ef5b32eed6
Joerg Sonnenberger [Wed, 23 Oct 2019 13:39:10 +0000 (15:39 +0200)]
Always flush pending errors in MCAsmParser
This has become visible with the --fatal-warnings support.
Puyan Lotfi [Thu, 24 Oct 2019 22:36:10 +0000 (18:36 -0400)]
[compiler-rt] cmake: add include(BuiltinTests) to CompilerRTDarwinUtils
In cmake, if TEST_COMPILE_ONLY is set
compiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake invokes try_compile_only()
but try_compile_only() is defined in BuiltinTests.cmake and is not included in
CompilerRTDarwinUtils.cmake. This patch simply includes it BuiltinTests.
Differential Revision: https://reviews.llvm.org/D69410
Philip Reames [Thu, 24 Oct 2019 22:09:57 +0000 (15:09 -0700)]
Test commit access via git
Richard Smith [Thu, 24 Oct 2019 00:54:10 +0000 (17:54 -0700)]
When diagnosing an ambiguity, only note the candidates that contribute
to the ambiguity, rather than noting all viable candidates.
Jonas Devlieghere [Thu, 24 Oct 2019 20:19:00 +0000 (13:19 -0700)]
[CMake] Move LLDB_TEST_BUILD_DIRECTORY into test/CMakeLists.txt
The LLDB_TEST_BUILD_DIRECTORY variable only matters to the different
test suites. Therefore they belong in test/CMakeLists.txt rather than
the top-level CMakeLists.txt.
Jonas Devlieghere [Thu, 24 Oct 2019 20:15:17 +0000 (13:15 -0700)]
[CMake] Move test dependency tracking into test/CMakeLists.txt
As the name suggests, the LLDB test dependencies only matter to the
different test suites. Therefore they belong in test/CMakeLists.txt
rather than the top-level CMakeLists.txt.
Jonas Devlieghere [Thu, 24 Oct 2019 20:09:23 +0000 (13:09 -0700)]
[CMake] Don't set LLDB_TEST_* in the top-level CMakeLists
All these variables only affect the API tests. Therefore they belong in
test/API/CMakeLists.txt rather than the top-level CMakeLists.txt.
Jonas Devlieghere [Thu, 24 Oct 2019 19:49:47 +0000 (12:49 -0700)]
[CMake] Remove unused variable LLDB_TEST_CXX_COMPILER
CMake allows you to set a custom CXX compiler for the API test suite.
However, this variable is never used, because dotest uses the same
compiler to build C and CXX sources.
I'm not sure if this variable was added with the intention of supporting
a different compiler or if this is just a remnant of old functionality.
Given that this hasn't been working for a while, I assume it's safe to
remove.
Differential revision: https://reviews.llvm.org/D69401
Evgenii Stepanov [Thu, 24 Oct 2019 20:14:03 +0000 (13:14 -0700)]
Fix lld detection in standalone compiler-rt.
Summary:
Right now all hwasan tests on Android are silently disabled because they
require "has_lld" and standalone compiler-rt can not (and AFAIK was
never able to) set it.
Reviewers: pcc
Subscribers: dberris, mgorny, #sanitizers, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D69405
Hans Wennborg [Thu, 24 Oct 2019 21:42:01 +0000 (23:42 +0200)]
Try harder to fix GCC 5.3 build
(This time verified locally.)
It was failing with:
llvm/lib/MC/XCOFFObjectWriter.cpp:168:56: error: array must be initialized with a brace-enclosed initializer
std::array<Section *const, 2> Sections = {&Text, &BSS};
^
Scott Linder [Thu, 24 Oct 2019 20:02:26 +0000 (16:02 -0400)]
[AMDGPU] Clean up update_llc_test_checks CodeGen tests
Summary:
Some tests have been hand edited without removing the
update_llc_test_checks header, some have slightly outdated CHECK lines
which still pass, and some have additional comments which
update_llc_test_checks pushes towards the function body.
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69402
Saar Raz [Thu, 24 Oct 2019 21:09:37 +0000 (00:09 +0300)]
[Concepts] Constraint Enforcement & Diagnostics
Part of the C++20 concepts implementation effort.
- Associated constraints (requires clauses, currently) are now enforced when instantiating/specializing templates and when considering partial specializations and function overloads.
- Elaborated diagnostics give helpful insight as to why the constraints were not satisfied.
Phabricator: D41569
Simon Pilgrim [Thu, 24 Oct 2019 21:13:55 +0000 (22:13 +0100)]
Fix cppcheck shadow variable warning. NFCI.
jasonliu [Thu, 24 Oct 2019 21:03:16 +0000 (21:03 +0000)]
Follow up on D69112, fix build break for skipping field initialization
Clang emit warning for skipping field initialization. Add {} to fix it.
This is a patch that fixes issue introduced in https://reviews.llvm.org/D69112
David Tenty [Thu, 24 Oct 2019 21:01:17 +0000 (17:01 -0400)]
Follow on to Namespace fixup for D68340
remove using directive that can make lookup ambiguous.
Simon Pilgrim [Thu, 24 Oct 2019 20:39:56 +0000 (13:39 -0700)]
Fix MSVC "switch statement contains 'default' but no 'case' labels" warning. NFCI.
Simon Pilgrim [Thu, 24 Oct 2019 20:36:34 +0000 (13:36 -0700)]
Fix MSVC "not all control paths return a value" warnings. NFCI.
Stephan T. Lavavej [Wed, 23 Oct 2019 23:42:47 +0000 (16:42 -0700)]
[www] Change URLs to HTTPS.
This changes most URLs in llvm's html files to HTTPS. Most changes were
search-and-replace with manual verification; some changes were manual.
For a few URLs, the websites were performing redirects or had changed
their anchors; I fixed those up manually. This consistently uses the
official https://wg21.link redirector. This also strips trailing
whitespace and fixes a couple of typos.
Fixes D69363.
There are a very small number of dead links for which I don't know any
replacements (they are equally dead as HTTP or HTTPS):
https://llvm.org/cmds/llvm2cpp.html
https://llvm.org/devmtg/2010-11/videos/Grosser_Polly-desktop.mp4
https://llvm.org/devmtg/2010-11/videos/Grosser_Polly-mobile.mp4
https://llvm.org/devmtg/2011-11/videos/Grosser_PollyOptimizations-desktop.mov
https://llvm.org/devmtg/2011-11/videos/Grosser_PollyOptimizations-mobile.mp4
https://llvm.org/perf/db_default/v4/nts/22463
https://polly.llvm.org/documentation/memaccess.html
Vedant Kumar [Thu, 24 Oct 2019 19:08:24 +0000 (12:08 -0700)]
Revert "Disable exit-on-SIGPIPE in lldb"
This reverts commit
32ce14e55e5a99dd99c3b4fd4bd0ccaaf2948c30.
In post-commit review, Pavel pointed out that there's a simpler way to
ignore SIGPIPE in lldb that doesn't rely on llvm's handlers.
paulhoad [Thu, 24 Oct 2019 20:08:57 +0000 (21:08 +0100)]
[clang-format] update documentation
Summary:
- Added example code for BreakStringLiterals;
Reviewers: MyDeveloperDay
Reviewed By: MyDeveloperDay
Patch By: mrexodia
Subscribers: cfe-commits, MyDeveloperDay
Tags: #clang-tools-extra, #clang-format, #clang
Differential Revision: https://reviews.llvm.org/D31574
Akira Hatanaka [Wed, 23 Oct 2019 14:38:52 +0000 (07:38 -0700)]
[ObjC][ARC] Check whether the return and parameter types of the old and
new functions are compatible before upgrading a function call to an
intrinsic call.
Sometimes users insert calls to ARC runtime functions that are not
compatible with the corresponding intrinsic functions (for example,
'i8* @objc_storeStrong' instead of 'void @objc_storeStrong'). Don't
upgrade those calls.
rdar://problem/
56447127
Craig Topper [Thu, 24 Oct 2019 19:08:02 +0000 (12:08 -0700)]
[GlobalISel][AArch64][AMDGPU][X86] Teach LegalizationArtifactCombiner to combine trunc(g_constant).
This allows X86 to properly form shift by immediate instructions
since we require an 8-bit constant to match the imported
SelectionDAG patterns.
David Tenty [Thu, 24 Oct 2019 19:47:08 +0000 (15:47 -0400)]
Namespace fixup for D68340 build on MSVC
we seem to run into issues with nested namespace lookups in recently landed
D68340 so just make them explicit.
paulhoad [Thu, 24 Oct 2019 19:24:03 +0000 (20:24 +0100)]
[clang-format] Remove duplciate code from Invalid BOM detection
Summary:
Review comments on {D68767} asked that this duplicated code in clang-format was moved to one central location that being SourceManager (where it had originally be copied from I assume)
Moved function into static function ContentCache::getInvalidBOM(...) - (closest class to where it was defined before)
Updated clang-format to call this static function
Added unit tests for said new function in BasicTests
Sorry not my normal code area so may have the wrong reviewers. (but your names were on the recent history)
Reviewers: bruno, arphaman, klimek, owenpan, mitchell-stellar, dexonsmith
Reviewed By: owenpan
Subscribers: cfe-commits
Tags: #clang, #clang-format, #clang-tools-extra
Differential Revision: https://reviews.llvm.org/D68914
David Green [Thu, 24 Oct 2019 18:56:08 +0000 (19:56 +0100)]
[ARM] Fixup MVE intrinsic tests with no assert builds
The labels will be missing, so -fno-discard-value-names is added to the tests.
stevewan [Thu, 24 Oct 2019 18:47:32 +0000 (14:47 -0400)]
Add AIX toolchain and basic linker functionality
Summary:
This patch adds AIX toolchain infrastructure into driver, and enables AIX
system linker invocation with some basic functionality support
Reviewers: daltenty, hubert.reinterpretcast, jasonliu, Xiangling_L
Reviewed By: jasonliu
Subscribers: Xiangling_L, jasonliu, ormris, wuzish, nemanjai, mgorny, kbarton, jfb, jsji, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D68340
David Green [Thu, 24 Oct 2019 18:35:34 +0000 (19:35 +0100)]
[ARM] Attempt to fixup MveEmitter warnings
Change-Id: I3fb06de2202c3b7a9ce511a40e758d0971ef9fdb
Fangrui Song [Thu, 24 Oct 2019 17:52:19 +0000 (10:52 -0700)]
[ELF] -r: fix crash when processing a SHT_REL[A] that relocates a SHF_MERGE after D67504/r372734
Fix PR43767
In -r mode, when processing a SHT_REL[A] that relocates a SHF_MERGE, sec->getRelocatedSection() is a
MergeInputSection and its parent is an OutputSection but is asserted to
be a SyntheticSection (MergeSyntheticSection) in LinkerScript.cpp:addInputSec().
##
The code path is not exercised in non -r mode because the relocated
section changed from MergeInputSection to InputSection.
Reorder the code to make the non -r logic apply to -r as well, thus fix
the crash.
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D69364
Michal Gorny [Wed, 23 Oct 2019 13:17:25 +0000 (06:17 -0700)]
[lldb] [Python] Do not attempt to flush() a read-only fd
Summary:
When creating a FileSP object, do not flush() the underlying file unless
it is open for writing. Attempting to flush() a read-only fd results
in EBADF on NetBSD.
Reviewers: lawrence_danna, labath, krytarowski
Reviewed By: lawrence_danna, labath
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D69320
paulhoad [Thu, 24 Oct 2019 18:01:47 +0000 (19:01 +0100)]
[clang-format] Remove the dependency on frontend
Summary:
Address review comments from {D68554} by trying to drop the dependency again on Frontend whilst keeping the same format diagnostic messages
Not completely happy with having to do a split in order to get the StringRef for the Line the error occurred on, but could see a way to use SourceManager and SourceLocation to give me a single line?
But this removes the dependency on frontend which should keep the binary size down.
Reviewers: thakis, klimek, mitchell-stellar
Reviewed By: klimek
Subscribers: mgorny, cfe-commits
Tags: #clang, #clang-format
Differential Revision: https://reviews.llvm.org/D68969
Stanislav Mekhanoshin [Thu, 24 Oct 2019 17:34:47 +0000 (10:34 -0700)]
[AMDGPU] Fix mfma scheduling crash
An SUnit can be neither intruction not SDNode. It is all
null if represents a nop. Fixed a crash on using SU->getInstr().
Differential Revision: https://reviews.llvm.org/D69395
Hans Wennborg [Thu, 24 Oct 2019 17:57:35 +0000 (19:57 +0200)]
Speculative build fix for GCC 5.3.0
It was failing with
llvm/lib/MC/XCOFFObjectWriter.cpp:168:53: error: array must be initialized with a brace-enclosed initializer
std::array<Section *const, 2> Sections{&Text, &BSS};
^
Jonas Devlieghere [Thu, 24 Oct 2019 17:54:48 +0000 (10:54 -0700)]
[CMake] Split logic across test suite subdirectories (NFC)
The top-level CMake file in the test directory can be simplified by
moving relevant configuration options into the corresponding
subdirectories. Doing so makes it easier to understand what CMake
options are needed by the different test suites.
Differential revision: https://reviews.llvm.org/D69394
Puyan Lotfi [Tue, 22 Oct 2019 16:47:10 +0000 (09:47 -0700)]
[llvm-ifs][NFC] Adds TODO comment for dropping ObjectFileFormat on yaml format.
dfukalov [Wed, 23 Oct 2019 17:01:14 +0000 (20:01 +0300)]
[NFC] Remove redundant lines
Reviewers: rampitec
Reviewed By: rampitec
Subscribers: arsenm, jvesely, nhaehnle, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69375
Benjamin Kramer [Thu, 24 Oct 2019 15:57:24 +0000 (17:57 +0200)]
[InstCombine] Fold one-use variable into assert
Avoids warnings in Release builds. NFC.
jasonliu [Thu, 24 Oct 2019 15:19:12 +0000 (15:19 +0000)]
[NFC][XCOFF][AIX] Serialize object file writing for each CsectGroup
Summary:
Right now we handle each CsectGroup(ProgramCodeCsects, BSSCsects)
individually when assigning indices, writing symbol table, and
writing section raw data. However, there is already a pattern there,
and we could common up those actions for every CsectGroup. This will
make adding new CsectGroup(Read Write data, Read only data, TC/TOC,
mergeable string) easier, and less error prone.
Reviewed by: sfertile, daltenty, DiggerLin
Approved by: daltenty
Differential Revision: https://reviews.llvm.org/D69112
Simon Tatham [Wed, 11 Sep 2019 09:29:56 +0000 (10:29 +0100)]
[InstCombine] Known-bits optimization for ARM MVE VADC.
The MVE VADC instruction reads and writes the carry bit at bit 29 of
the FPSCR register. The corresponding ACLE intrinsic is specified to
work with an integer in which the carry bit is stored at bit 0. So if
a user writes a code sequence in C that passes the carry from one VADC
to the next, like this,
s0 = vadcq_u32(a0, b0, &carry);
s1 = vadcq_u32(a1, b1, &carry);
then clang will generate IR for each of those operations that shifts
the carry bit up into bit 29 before the VADC, and after it, shifts it
back down and masks off all but the low bit. But in this situation
what you really wanted was two consecutive VADC instructions, so that
the second one directly reads the value left in FPSCR by the first,
without wasting several instructions on pointlessly clearing the other
flag bits in between.
This commit explains to InstCombine that the other bits of the flags
operand don't matter, and adds a test that demonstrates that all the
code between the two VADC instructions can be optimized away as a
result.
Reviewers: dmgreen, miyuki, ostannard
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67162
Simon Tatham [Mon, 2 Sep 2019 14:50:50 +0000 (15:50 +0100)]
[clang,ARM] Initial ACLE intrinsics for MVE.
This commit sets up the infrastructure for auto-generating <arm_mve.h>
and doing clang-side code generation for the builtins it relies on,
and demonstrates that it works by implementing a representative sample
of the ACLE intrinsics, more or less matching the ones introduced in
LLVM IR by D67158,D68699,D68700.
Like NEON, that header file will provide a set of vector types like
uint16x8_t and C functions with names like vaddq_u32(). Unlike NEON,
the ACLE spec for <arm_mve.h> includes a polymorphism system, so that
you can write plain vaddq() and disambiguate by the vector types you
pass to it.
Unlike the corresponding NEON code, I've arranged to make every user-
facing ACLE intrinsic into a clang builtin, and implement all the code
generation inside clang. So <arm_mve.h> itself contains nothing but
typedefs and function declarations, with the latter all using the new
`__attribute__((__clang_builtin))` system to arrange that the user-
facing function names correspond to the right internal BuiltinIDs.
So the new MveEmitter tablegen system specifies the full sequence of
IRBuilder operations that each user-facing ACLE intrinsic should
translate into. Where possible, the ACLE intrinsics map to standard IR
operations such as vector-typed `add` and `fadd`; where no standard
representation exists, I call down to the sample IR intrinsics
introduced in an earlier commit.
Doing it like this means that you get the polymorphism for free just
by using __attribute__((overloadable)): the clang overload resolution
decides which function declaration is the relevant one, and _then_ its
BuiltinID is looked up, so by the time we're doing code generation,
that's all been resolved by the standard system. It also means that
you get really nice error messages if the user passes the wrong
combination of types: clang will show the declarations from the header
file and explain why each one doesn't match.
(The obvious alternative approach would be to have wrapper functions
in <arm_mve.h> which pass their arguments to the underlying builtins.
But that doesn't work in the case where one of the arguments has to be
a constant integer: the wrapper function can't pass the constantness
through. So you'd have to do that case using a macro instead, and then
use C11 `_Generic` to handle the polymorphism. Then you have to add
horrible workarounds because `_Generic` requires even the untaken
branches to type-check successfully, and //then// if the user gets the
types wrong, the error message is totally unreadable!)
Reviewers: dmgreen, miyuki, ostannard
Subscribers: mgorny, javed.absar, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67161
Simon Tatham [Mon, 2 Sep 2019 14:35:09 +0000 (15:35 +0100)]
[clang] New __attribute__((__clang_arm_mve_alias)).
This allows you to declare a function with a name of your choice (say
`foo`), but have clang treat it as if it were a builtin function (say
`__builtin_foo`), by writing
static __inline__ __attribute__((__clang_arm_mve_alias(__builtin_foo)))
int foo(args);
I'm intending to use this for the ACLE intrinsics for MVE, which have
to be polymorphic on their argument types and also need to be
implemented by builtins. To avoid having to implement the polymorphism
with several layers of nested _Generic and make error reporting
hideous, I want to make all the user-facing intrinsics correspond
directly to clang builtins, so that after clang resolves
__attribute__((overloadable)) polymorphism it's already holding the
right BuiltinID for the intrinsic it selected.
However, this commit itself just introduces the new attribute, and
doesn't use it for anything.
To avoid unanticipated side effects if this attribute is used to make
aliases to other builtins, there's a restriction mechanism: only
(BuiltinID, alias) pairs that are approved by the function
ArmMveAliasValid() will be permitted. At present, that function
doesn't permit anything, because the Tablegen that will generate its
list of valid pairs isn't yet implemented. So the only test of this
facility is one that checks that an unapproved builtin _can't_ be
aliased.
Reviewers: dmgreen, miyuki, ostannard
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67159
Simon Tatham [Mon, 7 Oct 2019 16:03:46 +0000 (17:03 +0100)]
[ARM] Add IR intrinsics for MVE VLD[24] and VST[24].
The VST2 and VST4 instructions take two or four vector registers as
input, and store part of each register to memory in an interleaved
pattern. They come in variants indicating which part of each register
they store (VST20 and VST21; VST40 to VST43 inclusive); the intention
is that issuing each of those variants in turn has the combined effect
of loading or storing the whole set of registers to a memory block of
equal size. The corresponding VLD2 and VLD4 instructions load from
memory in the same interleaved format: each one overwrites only part
of its output register set, and again, the idea is that if you use
VLD4{0,1,2,3} or VLD2{0,1} together, you end up having written to the
whole of each register.
I've implemented the stores and loads quite differently. The loads
were easiest to implement as a single intrinsic that expands to all
four VLD4x instructions or both VLD2x, delivering four complete output
registers. (Implementing each individual load as a separate
instruction taking four input registers to partially overwrite is
possible in theory, but pointless, and when I tried it, I found it
would need extra work to get the register allocation not to be
horrible.) Since that intrinsic delivers multiple outputs, it has to
be instruction-selected in custom C++.
But the store instructions are easier to model individually, because
they don't overwrite any register at all and you can write a DAG Isel
pattern in Tablegen for each one.
Hence, my new intrinsic `int_arm_mve_vld4q` expands to four load
instructions, delivers four full output vectors, and is handled by C++
code, whereas `int_arm_mve_vst4q` expands to just one store
instruction, takes four input vectors and a constant indicating which
lanes to store, and is handled entirely in Tablegen. (And similarly
for vld2q/vst2q.) This is asymmetric, but it was the easiest way to do
each one.
Reviewers: dmgreen, miyuki, ostannard
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68700
Simon Tatham [Mon, 7 Oct 2019 16:05:48 +0000 (17:05 +0100)]
[ARM] Add some sample IR MVE intrinsics with C++ isel.
This adds some initial example IR intrinsics for MVE instructions that
deliver multiple output values, and hence, have to be instruction-
selected by custom C++ code instead of Tablegen patterns.
I've added the writeback gather load instructions (taking a vector of
base addresses and a single common offset, returning a vector of
loaded values and an updated vector of base addresses); one example
from the long shift family (taking and returning a 64-bit value in two
GPRs); and the VADC instruction (which propagates a carry bit from
each vector-lane addition to the next, taking an input carry flag in
FPSCR and outputting the final one in FPSCR as well).
To support the VPT-predicated forms of these instructions, I've
written some helper functions to add the cluster of MVE predicate
operands to the end of a MachineInstr. `AddMVEPredicateToOps` is used
when the instruction actually is predicated (so it takes a predicate
mask argument), and `AddEmptyMVEPredicateToOps` is for when the
instruction is unpredicated (so it fills in $noreg for the mask). Each
one comes in a form suitable for `vpred_n`, and one for `vpred_r`
which takes the extra 'inactive' parameter.
For VADC, the representation of the carry flag in the IR intrinsic is
a word intended to be moved directly to and from `FPSCR_nzcvqc`, i.e.
with the carry flag in bit 29 of the word. (The user-facing ACLE
intrinsic will want it to be in bit 0, but I'll do that on the clang
side.)
Reviewers: dmgreen, miyuki, ostannard
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68699
Simon Tatham [Mon, 7 Oct 2019 16:00:51 +0000 (17:00 +0100)]
[ARM] Begin adding IR intrinsics for MVE instructions.
This commit, together with the next few, will add a representative
sample of the kind of IR intrinsics that we'll need in order to
implement the user-facing ACLE intrinsics for MVE. Supporting all of
them will take more work; the intention of this initial series of
commits is to implement an intrinsic or two from lots of different
categories, as examples and proofs of concept.
This initial commit introduces a small number of IR intrinsics for
instructions simple enough that they can use Tablegen ISel patterns:
the predicated versions of the VADD and VSUB instructions (both
integer and FP), VMIN and VMAX, and the float->half VCVT instruction
(predicated and unpredicated).
When using VPT-predicated instructions in automatic code generation,
it will be convenient to specify the predicate value as a vector of
the appropriate number of i1. To make it easy to specify all sizes of
an instruction in one go and give each one the matching predicate
vector type, I've added a system of Tablegen informational records
describing MVE's vector types: each one gives the underlying LLVM IR
ValueType (which may not be the same if the MVE vector is of
explicitly signed or unsigned integers) and an appropriate vNi1 to use
as the predicate vector.
(Also, those info records include the usual encoding for the types, so
that as we add associations between each instruction encoding and one
of the new `MVEVectorVTInfo` records, we can remove some of the
existing template parameters and replace them with references to the
vector type info's fields.)
The user-facing ACLE intrinsics will receive a predicate mask as a
16-bit integer, so I've also provided a pair of intrinsics i2v and
v2i, to convert between an integer and a vector of i1 by just changing
the register class.
Reviewers: dmgreen, miyuki, ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67158
Michael Liao [Wed, 23 Oct 2019 19:19:06 +0000 (15:19 -0400)]
[AMDGPU] Skip additional folding on the same operand.
Reviewers: rampitec, arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69355
Michael Liao [Thu, 24 Oct 2019 13:54:08 +0000 (09:54 -0400)]
Fix compilation warning on the trailing whitespace. NFC.
Ilya Biryukov [Thu, 24 Oct 2019 13:40:23 +0000 (15:40 +0200)]
[clangd] Fix case of variables and functions in code complete tests. NFC
Simon Atanasyan [Thu, 24 Oct 2019 12:54:58 +0000 (15:54 +0300)]
[docs] Add Mips as a supported architecture in GettingStarted.rst
Patch by Miloš Stojanović
Differential Revision: https://reviews.llvm.org/D69380
Simon Atanasyan [Thu, 24 Oct 2019 12:52:19 +0000 (15:52 +0300)]
[docs] Update link to the MIPS 64-bit ELF object file specification
Patch by Miloš Stojanović
Differential Revision: https://reviews.llvm.org/D69377
Petar Avramovic [Thu, 24 Oct 2019 11:45:26 +0000 (13:45 +0200)]
[MIPS GlobalISel] Select MSA vector generic and builtin fabs
selectImpl is able to select G_FABS when we set bank for vector
operands to fprb. Add detailed tests.
Note: G_FABS is generated from llvm-ir intrinsics llvm.fabs.*,
and at the moment MIPS is not able to generate this intrinsic for
vector type (some targets generate vector llvm.fabs.* from calls
to a builtin function).
We can handle fabs using __builtin_msa_fmax_a_<format> and passing
same vector as both arguments. __builtin_msa_fmax_a_<format> will
be directly selected into FMAX_A_<format> in legalizeIntrinsic.
Differential Revision: https://reviews.llvm.org/D69346
evgeny [Thu, 24 Oct 2019 11:10:03 +0000 (14:10 +0300)]
Don't add -fsplit-lto-unit for thin LTO builds with PS4 and Darwin toolchains
These toolchains use legacy thin LTO API, which is not capable of unit splitting
Differential revision: https://reviews.llvm.org/D69173
David Tellenbach [Thu, 24 Oct 2019 10:16:06 +0000 (11:16 +0100)]
[compiler-rt] Expose __hwasan_tag_mismatch_stub
Summary:
GCC would like to emit a function call to report a tag mismatch
rather than hard-code the `brk` instruction directly.
__hwasan_tag_mismatch_stub contains most of the functionality to do
this already, but requires exposure in the dynamic library.
This patch moves __hwasan_tag_mismatch_stub outside of the anonymous
namespace that it was defined in and declares it in
hwasan_interface_internal.h.
We also add the ability to pass sizes larger than 16 bytes to this
reporting function by providing a fourth parameter that is only looked
at when the size provided is not in the original accepted range.
This does not change the behaviour where it is already being called,
since the previous definition only accepted sizes up to 16 bytes and
hence the change in behaviour is not seen by existing users.
The change in declaration does not matter, since the only existing use
is in the __hwasan_tag_mismatch function written in assembly.
Reviewers: eugenis, kcc, pcc, #sanitizers
Reviewed By: eugenis, #sanitizers
Subscribers: kristof.beyls, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D69113
Patch by Matthew Malcomson <matthew.malcomson@arm.com>
David Tellenbach [Thu, 24 Oct 2019 10:11:05 +0000 (11:11 +0100)]
Revert "Expose __hwasan_tag_mismatch_stub"
Attribution to author of patch got lost.
This reverts commit
612eadb7bc06b8f1a094976e06155f46ebd70d7c.
David Tellenbach [Thu, 24 Oct 2019 10:04:21 +0000 (11:04 +0100)]
Expose __hwasan_tag_mismatch_stub
Summary:
GCC would like to emit a function call to report a tag mismatch
rather than hard-code the `brk` instruction directly.
__hwasan_tag_mismatch_stub contains most of the functionality to do
this already, but requires exposure in the dynamic library.
This patch moves __hwasan_tag_mismatch_stub outside of the anonymous
namespace that it was defined in and declares it in
hwasan_interface_internal.h.
We also add the ability to pass sizes larger than 16 bytes to this
reporting function by providing a fourth parameter that is only looked
at when the size provided is not in the original accepted range.
This does not change the behaviour where it is already being called,
since the previous definition only accepted sizes up to 16 bytes and
hence the change in behaviour is not seen by existing users.
The change in declaration does not matter, since the only existing use
is in the __hwasan_tag_mismatch function written in assembly.
Tested with gcc and clang on an AArch64 vm.
Reviewers: eugenis, kcc, pcc, #sanitizers
Reviewed By: eugenis, #sanitizers
Subscribers: kristof.beyls, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D69113
Marek Kurdej [Thu, 24 Oct 2019 10:04:12 +0000 (12:04 +0200)]
[libFuzzer] docs: update note to include REDUCE event.
Benjamin Kramer [Thu, 24 Oct 2019 08:43:37 +0000 (10:43 +0200)]
Hide implementation details in anonymous namespaces. NFC.
Haojian Wu [Mon, 21 Oct 2019 08:11:30 +0000 (10:11 +0200)]
[clangd] Handle the missing constructor initializers in findExplicitReferences.
Reviewers: ilya-biryukov
Subscribers: MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69241
Haojian Wu [Wed, 23 Oct 2019 10:35:33 +0000 (12:35 +0200)]
[clangd] Collect name references in the index.
Summary:
This is used for cross-file rename. When renaming a class, we expect to
rename all related constructors/destructors.
Reviewers: kadircet, ilya-biryukov
Subscribers: MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69338
Petar Avramovic [Thu, 24 Oct 2019 08:15:07 +0000 (10:15 +0200)]
[MIPS GlobalISel] MSA vector generic and builtin fadd, fsub, fmul, fdiv
Select vector G_FADD, G_FSUB, G_FMUL and G_FDIV for MIPS32 with MSA. We
have to set bank for vector operands to fprb and selectImpl will do the
rest. __builtin_msa_fadd_<format>, __builtin_msa_fsub_<format>,
__builtin_msa_fmul_<format> and __builtin_msa_fdiv_<format> will be
transformed into G_FADD, G_FSUB, G_FMUL and G_FDIV in legalizeIntrinsic
respectively and selected in the same way.
Differential Revision: https://reviews.llvm.org/D69340
Petar Avramovic [Thu, 24 Oct 2019 08:03:36 +0000 (10:03 +0200)]
[MIPS GlobalISel] MSA vector generic and builtin sdiv, srem, udiv, urem
Select vector G_SDIV, G_SREM, G_UDIV and G_UREM for MIPS32 with MSA. We
have to set bank for vector operands to fprb and selectImpl will do the
rest. __builtin_msa_div_s_<format>, __builtin_msa_mod_s_<format>,
__builtin_msa_div_u_<format> and __builtin_msa_mod_u_<format> will be
transformed into G_SDIV, G_SREM, G_UDIV and G_UREM in legalizeIntrinsic
respectively and selected in the same way.
Differential Revision: https://reviews.llvm.org/D69333
Craig Topper [Thu, 24 Oct 2019 06:04:35 +0000 (23:04 -0700)]
[X86] Replace some regular expressions in xray tests with explicit checks to show bad assembly.
We're print 16-bit or 32-bit registers in copy instructions to
64-bit registers. This code will not assemble if it were to be
parsed back in. Emitting to binary works because we'll encode
the register the same way no matter what the size is.
Stanislav Mekhanoshin [Mon, 21 Oct 2019 20:43:01 +0000 (13:43 -0700)]
[AMDGPU] Allow folding of sgpr to vgpr copy
Potentially sgpr to sgpr copy should also be possible.
That is however trickier because we may end up with a
wrong register class at use because of xm0/xexec permutations.
Differential Revision: https://reviews.llvm.org/D69280
Shoaib Meenai [Thu, 24 Oct 2019 01:06:28 +0000 (18:06 -0700)]
[Hexagon] Fix typo. NFC
Testing git push access.
Meike Baumgärtner [Thu, 24 Oct 2019 01:03:37 +0000 (18:03 -0700)]
Add beginning of LLVM's GettingStarted to GitHub readme
Reviewed and approved by chandlerc.
As GitHub is the canonical LLVM repository now, embrace GitHub's way of displaying basic build instructions in the top-level readme.md.
Chandler Carruth [Wed, 23 Oct 2019 19:14:04 +0000 (12:14 -0700)]
Improve Clang's getting involved document and make it more inclusive in wording.
Summary: Working with Meike and others to improve the wording in this document.
Reviewers: klimek
Subscribers: mcrosier, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69351
David Tenty [Wed, 23 Oct 2019 20:48:02 +0000 (16:48 -0400)]
Use portable flag with nm in extract_symbols.py
Summary:
nm is one of the tools that extract_symbols.py can use to extract
symbols from llvm libraries as part of the build process. This patch
updates the invocation of nm to use the -P POSIX option for "portable
output" so we get a consistently parsable output format on all
platforms.
A link to the relevant nm format: https://pubs.opengroup.org/onlinepubs/
9699919799/utilities/nm.html
Reviewers: hubert.reinterpretcast, stevewan, sfertile
Reviewed By: stevewan
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69004
Meike Baumgärtner [Wed, 23 Oct 2019 19:32:57 +0000 (12:32 -0700)]
Improve language in GettingStarted.rst
This patch was reviewed and approved by chandlerc.
"Getting Started with the LLVM System" is the first point of contact for many newcomers in the LLVM community.
* Make the first two paragraphs more welcoming
* Use more inclusive language