Patrick Delaunay [Mon, 6 Jun 2022 14:04:16 +0000 (16:04 +0200)]
ARM: stm32: activate OF_LIVE for DHSOM
Activate the live DT with CONFIG_OF_LIVE to reduce the DT parsing
time.
Tested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Mon, 6 Jun 2022 14:04:15 +0000 (16:04 +0200)]
board: dhelectronics: stm32mp1: convert to livetree
Replace call to fdt_*() functions and access to gd->fdt_blob
with call to ofnode_*() functions to support a live tree.
Tested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Thu, 19 May 2022 07:07:30 +0000 (09:07 +0200)]
board: engicam: stm32mp1: convert to livetree
Replace gd->fdt_blob access with fdt_getprop() function to the
function ofnode_get_property() to support a live tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Thu, 19 May 2022 07:07:29 +0000 (09:07 +0200)]
board: stm32mp1: convert to livetree
Replace gd->fdt_blob access with fdt_getprop() function to the
function ofnode_get_property() to support a live tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Thu, 19 May 2022 15:56:46 +0000 (17:56 +0200)]
misc: stm32mp13: introduce STM32MP13 RCC driver
Add the MISC RCC driver for STM32MP13, and bind it to the RCC reset
driver, required for initial support.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Change-Id: Ida11c15462caf140f87b1e3239efa2b8a689acb9
Patrick Delaunay [Thu, 19 May 2022 15:56:45 +0000 (17:56 +0200)]
clk: Add directory for STM32 clock drivers
Add a directory in drivers/clk to regroup the clock drivers for all
STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or
CONFIG_ARCH_STM32MP (MPUs with cortex A).
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Acked-by: Sean Anderson <seanga2@gmail.com>
Change-Id: I955af307963f732167396f0157a30cf2fc91f150
Patrick Delaunay [Mon, 9 May 2022 15:13:22 +0000 (17:13 +0200)]
stm32mp: fdt: update etzpc for STM32MP13x
Add support of STM32MP13x the ETZPC part of fdt.c
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: If2777fbf66b8525a2a447056780aaa04e6b0a9a0
Patrick Delaunay [Mon, 9 May 2022 15:13:21 +0000 (17:13 +0200)]
stm32mp: fdt: update etzpc for STM32MP15x
Introduce STM32MP15 function and defines to prepare the
STM32MP13 introduction.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I909b205e73dcf207e0216aae5905c3c52472020e
Patrick Delaunay [Fri, 20 May 2022 16:24:54 +0000 (18:24 +0200)]
doc: st: stm32mp1: add STM32MP13x support
Add in U-Boot documentation the quick instruction to
setup the STMicroelectronics STM32MP13x boards.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:53 +0000 (18:24 +0200)]
configs: add stm32mp13 defconfig
Add a initial config for STM32M13x SOC family, using the stm32mp135f-dk
device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:52 +0000 (18:24 +0200)]
arm: dts: stm32mp: add stm32mp13 device tree for U-Boot
Compile the device tree of STM32MP13x boards and add the needed
U-Boot add-on.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:51 +0000 (18:24 +0200)]
mmc: stm32_sdmmc2: make reset property optional
Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:50 +0000 (18:24 +0200)]
ram: stm32mp1: add support of STM32MP13x
Add support for new compatible "st,stm32mp13-ddr" to manage the
DDR sub system (Controller and PHY) in STM32MP13x SOC:
- only one AXI port
- support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)
The STM32MP15x SOC have 2 AXI ports and 32 bits support.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:49 +0000 (18:24 +0200)]
board: stm32pm1: add stm32mp13 board support
Add stm32mp15x prefix to all STM32MP15x board specific functions,
this patch is a preliminary step for STM32MP13x support.
This patch also adds the RCC probe to avoid circular access with
usbphyc probe as clk provider.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:48 +0000 (18:24 +0200)]
pinctrl: stm32: add support of STM32MP135
Add support for "st,stm32mp135-pinctrl" for STM32MP13x
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:47 +0000 (18:24 +0200)]
arm: stm32mp: support 2 MAC address for STM32MP13
Add support of several MAC address in OTP (3 32bits OTP word for
2 MAC address) for SOCs in STM32MP13x family: STM32MP133 and STM32MP135.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:46 +0000 (18:24 +0200)]
arm: stm32mp: add support of STM32MP13x
Introduce the code in mach-stm32mp and the configuration file
stm32mp13_defconfig for the new STM32MP family.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:45 +0000 (18:24 +0200)]
arm: stm32mp: add CONFIG_STM32MP15_PWR
Add config CONFIG_STM32MP15_PWR to handle the
access to regulators managed by the PWR driver defined in
pwr_regulator.c
This driver is only used in U-Boot by STM32MP15x family.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:44 +0000 (18:24 +0200)]
arm: stm32mp: add sub config Kconfig.15x
Add sub Kconfig for each SOC in the STM32 CPU family.
It is a preliminary step to introduce a new SOC in the STM32MP family.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:43 +0000 (18:24 +0200)]
arm: stm32mp: add choice for STM32MP SOC family
Add mandatory choice for SOC support in ARCH_STM32MP.
This patch is a preliminary step for new SOC introduction
in STM32MP family.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:42 +0000 (18:24 +0200)]
arm: stm32mp: move code for STM32MP15x
Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c
when low level init without TFABOOT is supported.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:41 +0000 (18:24 +0200)]
arm: stm32mp: move the get_otp helper function in bsec
As the get_otp() helper function in bsec are common for all STM32MP family,
move this function in bsec driver
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:40 +0000 (18:24 +0200)]
configs: stm32mp1: move SUPPORT_SPL in STM32MP15x
The SPL is only supported by STM32MP15x not by all the
SOC with STM32MP arch.
Only TFABOOT is supported in next products.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrick Delaunay [Fri, 20 May 2022 16:24:39 +0000 (18:24 +0200)]
ARM: dts: stm32: add STM32MP13 SoCs support
Add initial support of STM32MP13 family based on v5.18-rc2
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tom Rini [Thu, 16 Jun 2022 13:27:43 +0000 (09:27 -0400)]
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
Peng Fan [Sat, 11 Jun 2022 12:21:10 +0000 (20:21 +0800)]
imx: phycore_imx8mm/p: clean up board watchdog code
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
Peng Fan [Sat, 11 Jun 2022 12:21:09 +0000 (20:21 +0800)]
imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Peng Fan [Sat, 11 Jun 2022 12:21:08 +0000 (20:21 +0800)]
imx: imx8mp_rsb7320a1: enable wdog driver model in SPL
Mark wdog1/pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 11 Jun 2022 12:21:07 +0000 (20:21 +0800)]
imx: imx8mn_var_som: clean up board watchdog code
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Peng Fan [Sat, 11 Jun 2022 12:21:06 +0000 (20:21 +0800)]
imx: imx8mn-beacon: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 11 Jun 2022 12:21:05 +0000 (20:21 +0800)]
imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 11 Jun 2022 12:21:04 +0000 (20:21 +0800)]
imx: engicam-imx8mm: drop unused macro
Drop unused WDOG macro
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Peng Fan [Sat, 11 Jun 2022 12:21:03 +0000 (20:21 +0800)]
imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 11 Jun 2022 12:21:02 +0000 (20:21 +0800)]
imx: imx8mm_beacon: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 11 Jun 2022 12:21:01 +0000 (20:21 +0800)]
configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE
CONFIG_SPL_RAW_IMAGE_SUPPORT default y has been used to replace
CONFIG_SPL_ABORT_ON_RAW_IMAGE for quite some time, so drop
CONFIG_SPL_ABORT_ON_RAW_IMAGE.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 11 Jun 2022 12:21:00 +0000 (20:21 +0800)]
imx: kontron-sl-mx8mm: enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Peng Fan [Sat, 11 Jun 2022 12:20:59 +0000 (20:20 +0800)]
imx: imx8mn_var_som: enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Sat, 11 Jun 2022 12:20:58 +0000 (20:20 +0800)]
imx: imx8m[m/p]_phycore: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Sat, 11 Jun 2022 12:20:57 +0000 (20:20 +0800)]
imx: imx8mm_icore: Enable SPL_DM_SERIAL
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Sat, 11 Jun 2022 12:20:56 +0000 (20:20 +0800)]
imx: imx8mm-cl-iot-gate: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Sat, 11 Jun 2022 12:20:55 +0000 (20:20 +0800)]
imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mn_beacon
Peng Fan [Sat, 11 Jun 2022 12:20:54 +0000 (20:20 +0800)]
imx: drop CONFIG_MXC_UART_BASE
Since these boards has CONFIG_DM_SERIAL and/or CONFIG_SPL_DM_SERIAL,
the legacy macro no need to be defined.
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Soeren Moch <smoch@web.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tom Rini [Fri, 10 Jun 2022 20:02:42 +0000 (16:02 -0400)]
Merge branch '2022-06-10-assorted-platform-updates' into next
- TI J721E hyperflash support, TI OMAP3 updates, TI AM654 updates,
TI AM62 initial support, Broadcom bcmbca 47622 SoC support, NPCM7xx
pinctrl and rng drivers, Synquacer updates
Vignesh Raghavendra [Wed, 25 May 2022 08:08:50 +0000 (13:38 +0530)]
doc: ti: Add readme for AM62x SK
Add info of boot flow and build steps for AM62x SK.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Vignesh Raghavendra [Wed, 25 May 2022 08:08:49 +0000 (13:38 +0530)]
configs: Add configs for AM62x SK
Add am62x_evm_r5_defconfig for R5 SPL and am62x_evm_a53_defconfig for
A53 SPL and U-Boot support.
To keep the changes to minimum. Only UART And SD boot related configs
are included. This should serve as good starting point for new board
bringup with AM62x.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
[trini: Migrate a number of CONFIG symbols, have re-tested]
Tested-by: Georgi Vlaev <g-vlaev@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Wed, 25 May 2022 08:08:48 +0000 (13:38 +0530)]
arm: dts: Add support for AM62-SK
AM62 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM625 SoC. It supports the following interfaces:
* 2 GB DDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode
* x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display
* x1 Headphone Jack
* x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x4 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin User Expansion Connector
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 20-pin header for Programmable Realtime Unit (PRU) IO pins
* 15-pin CSI header
Add basic support for AM62-SK.
To keep the changes to minimum. Only UART And SD are supported at the
moment. This should serve as good example for adding new board support
based on AM62x SoC
Schematics: https://www.ti.com/lit/zip/sprr448
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Suman Anna [Wed, 25 May 2022 08:08:47 +0000 (13:38 +0530)]
board: ti: Introduce the basic files to support AM62 SK board
Add basic support for AM62 SK. This has 2GB DDR.
Note that stack for R5 SPL is in OCRAM @ 0x7000ffff so that is away from
BSS and does not step on BSS section
Add only the bare minimum required to support UART and SD.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Suman Anna [Wed, 25 May 2022 08:08:46 +0000 (13:38 +0530)]
arm: dts: Introduce base AM62 SoC dtsi files
Introduce the basic AM62 SoC description dtsi files describing most
peripherals as per kernel dts.
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vignesh Raghavendra [Wed, 25 May 2022 08:08:45 +0000 (13:38 +0530)]
firmware: ti_sci_static_data: add static DMA chan data
Add range of DMA channels available for R5 SPL usage before DM firmware
is loaded.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vignesh Raghavendra [Wed, 25 May 2022 08:08:44 +0000 (13:38 +0530)]
dma: ti: Add PSIL data for AM62x DMASS
Add PSIL data for AM62x SoC.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Suman Anna [Wed, 25 May 2022 08:08:43 +0000 (13:38 +0530)]
arm: mach-k3: am62: Introduce autogenerated SoC data
Introduce autogenerated SoC data support clk and device data for the
AM62. Hook it upto to power-domain and clk frameworks of U-Boot.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Suman Anna [Wed, 25 May 2022 08:08:42 +0000 (13:38 +0530)]
arm: mach-k3: Introduce the basic files to support AM62
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
architecture platform, providing ultra-low-power modes, dual display,
multi-sensor edge compute, security and other BOM-saving integration.
The AM62 SoC targets broad market to enable applications such as
Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
Automation, Appliances and more.
Some highlights of this SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
Pin-to-pin compatible options for single and quad core are available.
* Cortex-M4F for general-purpose or safety usage.
* Dual display support, providing 24-bit RBG parallel interface and
OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
resolution.
* Selectable GPUsupport, up to 8GFLOPS, providing better user experience
in 3D graphic display case and Android.
* PRU(Programmable Realtime Unit) support for customized programmable
interfaces/IOs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized System Controller for Security, Power, and
Resource Management.
* Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
enabling battery powered system design.
AM625 is the first device of the family. Add DT bindings for the same.
More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Suman Anna [Wed, 25 May 2022 08:08:41 +0000 (13:38 +0530)]
soc: ti: k3-socinfo: Add entry for AM62X SoC family
Add support for AM62x SoC identification.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Suman Anna [Wed, 25 May 2022 08:08:40 +0000 (13:38 +0530)]
dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62
Add pinctrl macros for AM62x SoCs. These macro definitions are similar
to that of previous platforms, but adding new definitions to avoid any
naming confusions in the SoC dts files.
checkpatch insists the following error exists:
ERROR: Macros with complex values should be enclosed in parentheses
However, we do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
done for other similar platforms.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Aswath Govindraju [Wed, 25 May 2022 08:08:39 +0000 (13:38 +0530)]
drivers: mmc: am654_sdhci: Add new compatible for AM62 SoC
The phy used in the 8 bit instance has been changed to the phy used in 4
bit instance on AM62 SoC. This implies the phy configuration required for
both the instances of mmc are similar. Therefore, add a new compatible
for AM62 SoC using the driver data of am64 4 bit instance.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Jim Liu [Tue, 24 May 2022 08:56:57 +0000 (16:56 +0800)]
rng: nuvoton: Add NPCM7xx rng driver
Add Nuvoton BMC NPCM750 rng driver.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Aswath Govindraju [Wed, 18 May 2022 11:19:14 +0000 (16:49 +0530)]
configs: am65_evm_r5_usb*_defconfig: Sync the checks for size of image and stack from generic r5 defconfig
Sync the configs required for enabling checks for size of image and stack
from generic r5 defconfig file.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Wed, 18 May 2022 11:19:13 +0000 (16:49 +0530)]
arm: mach-k3: am6_init: Fix the path and value's length in the fixup performed for usb boot
The node name of the bus in the device tree has changed. Also, the length
argument to be passed should be the length of new value. Therefore, fix the
path to usb device tree node as well as the length argument passed.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Wed, 18 May 2022 11:19:12 +0000 (16:49 +0530)]
arm: dts: k3-am654-r5-base-board: Fix the dt properties in usb0 instance
For dfu boot mode, the clocks property needs to be deleted and dr_mode
needs to be set to peripheral. Therefore, add the required fixes for the
same.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Masahisa Kojima [Tue, 17 May 2022 08:41:39 +0000 (17:41 +0900)]
spi: synquacer: simplify tx completion checking
There is a TX-FIFO and Shift Register empty(TFES) status
bit in spi controller. This commit checks the TFES bit
to wait the TX transfer completes.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Masahisa Kojima [Tue, 17 May 2022 08:41:38 +0000 (17:41 +0900)]
spi: synquacer: DMSTART bit must not be set while transferring
DMSTART bit must not be set while there is active transfer.
This commit sets the DMSTART bit only when the transfer begins.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Masahisa Kojima [Tue, 17 May 2022 08:41:37 +0000 (17:41 +0900)]
spi: synquacer: wait until slave is deselected
synquacer_cs_set() function does not wait the chip select
is deasserted when the driver sets the DMSTOP to deselect
the slave.
This commit checks the Slave Select Released(SRS) bit to wait
until the slave is deselected.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Masahisa Kojima [Tue, 17 May 2022 08:41:36 +0000 (17:41 +0900)]
spi: synquacer: busy variable must be initialized before use
"busy" variable is ORed without being initialized,
must be zeroed before use.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Jim Liu [Tue, 17 May 2022 08:30:32 +0000 (16:30 +0800)]
pinctrl: nuvoton: Add NPCM7xx pinctrl driver
Add Nuvoton BMC NPCM750 Pinmux and Pinconf support.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Derald D. Woods [Mon, 16 May 2022 03:25:05 +0000 (22:25 -0500)]
ARM: omap3: evm: Fix 'fitImage' booting
This commit sets two additional variables in the default BOOTCOMMAND.
Adding 'boot=mmc' and 'addr_fit=0x8b000000' removes the need for a
special 'uEnv.txt' to be created. The 'addr_fit' variable is the key
piece here. It is normally defined as 0x90000000, in the macro
DEFAULT_FIT_TI_ARGS. For this OMAP34XX board, 0x8b000000 works without
touching other varibles. This was tested with a 'fitImage' created
using the following FIT source:
----------------------------------------------------------------------
/dts-v1/;
/ {
description = "Simple image with single Linux kernel and FDT blob";
#address-cells = <1>;
images {
kernel {
description = "Linux kernel: omap2plus";
data = /incbin/("./zImage");
type = "kernel";
arch = "arm";
os = "linux";
compression = "none";
load = <0x80008000>;
entry = <0x80008000>;
hash-1 {
algo = "sha256";
};
};
fdt-omap3-evm.dtb {
description = "FDT: omap3-evm.dtb";
data = /incbin/("./omap3-evm.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
load = <0x8ff00000>;
hash-1 {
algo = "sha256";
};
};
};
configurations {
default = "conf-omap3-evm.dtb";
conf-omap3-evm.dtb {
description = "Boot Linux kernel with FDT blob";
kernel = "kernel";
fdt = "fdt-omap3-evm.dtb";
};
};
};
----------------------------------------------------------------------
Additionally, the default environment is now stored in "uboot.env" on
the FAT partition of MMC '0'.
Fixes:
11e2ab3f0b ("ARM: omap3: evm: Enable booting 'fitImage' with DEFAULT_FIT_TI_ARGS")
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Derald D. Woods [Mon, 16 May 2022 03:25:04 +0000 (22:25 -0500)]
ARM: omap3: evm: Complete DM_I2C migration
This commits enables DM_I2C and sets the default bus to 0.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Derald D. Woods [Mon, 16 May 2022 03:25:03 +0000 (22:25 -0500)]
ARM: omap3: evm: Power on MMC when setting up PMIC
This commit copies the related code changes from the BeagleBoard.
Reference:
- https://source.denx.de/u-boot/u-boot/-/commit/
848cfe098f59c47a2542385513fb554430b874d6
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
William Zhang [Mon, 9 May 2022 16:28:02 +0000 (09:28 -0700)]
arm: bcmbca: introduce the bcmbca architecture and 47622 SOC
This is the initial support for Broadcom's ARM-based 47622 SOC.
In this change, our first SOC is an armv7 platform called 47622. The
initial support includes a bare-bone implementation and dts with ARM
PL011 uart.
The SOC-specific code resides in arch/arm/mach-bcmbca/<soc> and board
related code is in board/broadcom/bcmba.
The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Signed-off-by: Anand Gore <anand.gore@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Vaishnav Achath [Mon, 9 May 2022 06:20:17 +0000 (11:50 +0530)]
configs: j721e_evm_defconfig: Add HBMC related configs
Enable HBMC and HyperFlash in R5SPL, A72 SPL and A72 U-Boot
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
[trini: Update j721e_hs_evm_a72 as well]
Signed-off-by: Tom Rini <trini@konsulko.com>
Vaishnav Achath [Mon, 9 May 2022 06:20:16 +0000 (11:50 +0530)]
ti: j721e: enable hyperflash spl fixup for j721e
On j721e, its not possible to use OSPI0 and HBMC simultaneously as they
are muxed within the Flash Subsystem hence disable HBMC by default and
keep OSPI enabled. Bootloader will fixup DT when it detects HyperFlash
mux selection instead of OSPI.
Also updated detect_enable_hyperflash to use correct GPIO when checking
hypermux selection state:
* J7200 - hypermux sel connected to WKUP_GPIO0_6
* J721E - hypermux·sel·connected·to·WKUP_GPIO0_8
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Vaishnav Achath [Mon, 9 May 2022 06:20:15 +0000 (11:50 +0530)]
configs: j721e_evm.h: define CONFIG_SYS_FLASH_BASE
Define CONFIG_SYS_FLASH_BASE to indicate start address of
Flash memory
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Vaishnav Achath [Mon, 9 May 2022 06:20:14 +0000 (11:50 +0530)]
arm: k3: sysfw-loader: add hyperflash support
add support for loading system firmware from hyperflash.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Vaishnav Achath [Mon, 9 May 2022 06:20:13 +0000 (11:50 +0530)]
arm: dts: k3-j721e-common-proc-board: enable hyperflash mux sel GPIO
Add wkup_gpio pinmux setting which will be used for performing the
DT fixup for hbmc node according to mux selection state, on J721E
EVM, hypermux sel is tied to ·WKUP_GPIO0_8.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Vaishnav Achath [Mon, 9 May 2022 06:20:12 +0000 (11:50 +0530)]
arm: dts: k3-j721e-common-proc-board-u-boot: enable HyperFlash in SPL
add u-boot,dm-spl pre-relocation property to enable hbmc in SPL.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Vaishnav Achath [Mon, 9 May 2022 06:20:11 +0000 (11:50 +0530)]
arm: dts: k3-j721e-r5-common-proc-board: Add HyperFlash node
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node
for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Vaishnav Achath [Mon, 9 May 2022 06:20:10 +0000 (11:50 +0530)]
arm: dts: k3-j721e-som-p0: Add HyperFlash node
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node
for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Vaishnav Achath [Mon, 9 May 2022 06:20:09 +0000 (11:50 +0530)]
arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node
Add DT node for HyperBus Memory Controller and hbmc-mux in the
FSS. hbmc-am654 driver uses syscon_get_regmap() call which fails
with current compatible setting.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Tom Rini [Thu, 9 Jun 2022 19:20:11 +0000 (15:20 -0400)]
Merge branch '2022-06-09-add-support-for-nvmem-api' into next
To quote the author:
This adds support for the nvmem-cells properties cropping up in manyb
device trees. This is an easy way to load configuration, version
information, or calibration data from a non-volatile memory source. For
more information, refer to patch 6 ("misc: Add support for nvmem
cells").
For the moment I have only added some integration tests using the
ethernet addresses. This hits the main code paths (looking up nvmem
cells) but doesn't test writing. I can add a few stand-alone tests if
desired.
Sean Anderson [Thu, 5 May 2022 17:11:44 +0000 (13:11 -0400)]
test: Load mac address using misc device
This loads a mac address using a misc device using the nvmem interface.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Thu, 5 May 2022 17:11:43 +0000 (13:11 -0400)]
test: Load mac address using RTC
This uses the nvmem API to load a mac address from an RTC.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:42 +0000 (13:11 -0400)]
test: Load mac address with i2c eeprom
This uses an i2c eeprom to load a mac address using the nvmem interface.
Enable I2C_EEPROM for sandbox SPL since it is the only sandbox config
which doesn't enable it eeprom.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:41 +0000 (13:11 -0400)]
net: Add support for reading mac addresses from nvmem cells
This adds support for reading mac addresses from the "mac-address" nvmem
cell. If there is no (local-)mac-address property, then we will try
reading from an nvmem cell.
For some existing examples of this property, refer to imx8mn.dtsi and
imx8mp.dtsi. Unfortunately, fuse drivers have not yet been converted
to DM.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:40 +0000 (13:11 -0400)]
sandbox: Enable NVMEM
This enables NVMEM for all sandbox defconfigs, enabling it to be used in
unit tests in the next few commits.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:39 +0000 (13:11 -0400)]
misc: Add support for nvmem cells
This adds support for "nvmem cells" as seen in Linux. The nvmem device
class in Linux is used for various assorted ROMs and EEPROMs. In this
sense, it is similar to UCLASS_MISC, but also includes
UCLASS_I2C_EEPROM, UCLASS_RTC, and UCLASS_MTD. New drivers corresponding
to a Linux-style nvmem device should be implemented as one of the
previously-mentioned uclasses. The nvmem API acts as a compatibility
layer to adapt the (slightly different) APIs of these uclasses. It also
handles the lookup of nvmem cells.
While nvmem devices can be accessed directly, they are most often used
by reading/writing contiguous values called "cells". Cells typically
hold information like calibration, versions, or configuration (such as
mac addresses).
nvmem devices can specify "cells" in their device tree:
qfprom: eeprom@700000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00700000 0x100000>;
/* ... */
tsens_calibration: calib@404 {
reg = <0x404 0x10>;
};
};
which can then be referenced like:
tsens {
/* ... */
nvmem-cells = <&tsens_calibration>;
nvmem-cell-names = "calibration";
};
The tsens driver could then read the calibration value like:
struct nvmem_cell cal_cell;
u8 cal[16];
nvmem_cell_get_by_name(dev, "calibration", &cal_cell);
nvmem_cell_read(&cal_cell, cal, sizeof(cal));
Because nvmem devices are not all of the same uclass, supported uclasses
must register a nvmem_interface struct. This allows CONFIG_NVMEM to be
enabled without depending on specific uclasses. At the moment,
nvmem_interface is very bare-bones, and assumes that no initialization
is necessary. However, this could be amended in the future.
Although I2C_EEPROM and MISC are quite similar (and could likely be
unified), they present different read/write function signatures. To
abstract over this, NVMEM uses the same read/write signature as Linux.
In particular, short read/writes are not allowed, which is allowed by
MISC.
The functionality implemented by nvmem cells is very similar to that
provided by i2c_eeprom_partition. "fixed-partition"s for eeproms does
not seem to have made its way into Linux or into any device tree other
than sandbox. It is possible that with the introduction of this API it
would be possible to remove it.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Thu, 5 May 2022 17:11:38 +0000 (13:11 -0400)]
misc: i2c_eeprom: Add fallbacks
Add some fallback functions for when i2c_eeprom is disabled. This allows
code to reference i2c_eeprom_* functions without needing to check
whether support has been compiled in.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Thu, 5 May 2022 17:11:37 +0000 (13:11 -0400)]
misc: i2c_eeprom: Make i2c_eeprom_write use a const buf
i2c_eeprom_ops->write uses a const buf, so use one for the wrapper
function as well.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:36 +0000 (13:11 -0400)]
net: dsa: Fix segmentation fault if master fails to probe
If the DSA master fails to probe for whatever reason, then DSA devices
will continue on as if nothing is wrong. This can cause incorrect
behavior. In particular, on sandbox, dsa_sandbox_probe attempts to
access the master's private data. This is only safe to do if the master
has been probed first. Fix this by probing the master after we look it
up, and bailing out if we get an error.
Fixes:
fc054d563b ("net: Introduce DSA class for Ethernet switches")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Sean Anderson [Thu, 5 May 2022 17:11:35 +0000 (13:11 -0400)]
sandbox: Move some mac addresses to device tree
This prevents some conflicts when running sandbox with -D, since the
"rom" mac address will be random and won't match the environment. We
still need to keep addresses for eth1 and eth6 in the environment,
because dm_test_eth_rotate expects to be able to disable them by
removing their envaddr variables. This can likely be fixed in a future
series by adding a function to cause sandbox eth_opts callback for a
particular mac to fail immediately.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:34 +0000 (13:11 -0400)]
sandbox: Remove eth2addr from environment
DSA interfaces use the same mac address for each interface, unless
instructed otherwise. Just set eth4addr and let eth2addr and eth7addr be
set automatically.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:33 +0000 (13:11 -0400)]
sandbox: net: Remove fake-host-hwaddr
Instead of reading a pseudo-rom mac address from the device tree, just use
whatever we get from write_hwaddr. This has the effect of using the mac
address from the environment (or from the device tree, if it is
specified).
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ramon Fried <rfried.dev@gmail.com>
Sean Anderson [Thu, 5 May 2022 17:11:32 +0000 (13:11 -0400)]
test: eth: Add test for ethernet addresses
This adds a test to make sure that all the ethernet interfaces have
their addresses read properly. At the moment everything is read from the
environment, but the next few commits will add additional sources.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:31 +0000 (13:11 -0400)]
sandbox: net: Add mac address for eth8 to environment
The phy_eth0 interface introduced in commit
f3dd213e15 ("net: introduce
helpers to get PHY ofnode from MAC") uses a globally-administered
address. Switch to using a locally-administered address, and add it to
the sandbox environment, like the others.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Thu, 5 May 2022 17:11:30 +0000 (13:11 -0400)]
sandbox: net: Add aliases for ethernet devices
Commit
f3dd213e15 ("net: introduce helpers to get PHY ofnode from MAC")
changed the ethernet sequence assignment from
uclass 36: ethernet
0 * eth@
10002000 @
05813460, seq 0
1 * eth@
10003000 @
05813550, seq 5
2 * sbe5 @
05813640, seq 3
3 * eth@
10004000 @
05813730, seq 6
4 * dsa-test-eth @
05813820, seq 4
5 * lan0 @
05813a30, seq 2
6 * lan1 @
05813b50, seq 7
to
uclass 36: ethernet
0 * eth@
10002000 @
03813630, seq 0
1 * eth@
10003000 @
03813720, seq 5
2 * sbe5 @
03813810, seq 3
3 * eth@
10004000 @
03813900, seq 6
4 phy-test-eth @
038139f0, seq 7
5 * dsa-test-eth @
03813ae0, seq 4
6 * lan0 @
03813cf0, seq 2
7 * lan1 @
03813e10, seq 8
This caused the mac address assignment to switch around. Avoid this in
the future by assigning aliases for all ethernet devices. This reverts
the sequence to what it was before the aformentioned commit (with
phy-test-eth as seq 8). There is no ethernet1 for whatever reason.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Tom Rini [Wed, 8 Jun 2022 15:15:28 +0000 (11:15 -0400)]
Merge branch '2022-06-08-virtio-harden-and-test-vring' into next
To quote the author:
Make the virtio ring code resilient against corruption of the buffers
shared with the device.
It follows the example of Linux by keeping a private copy of the
descriptors and metadata for state tracking and only ever writing to the
descriptors that are shared with the device. I was able to test these
hardening steps in the sandbox by simulating device writes to the
queues.
Andrew Scull [Mon, 16 May 2022 10:41:40 +0000 (10:41 +0000)]
test: dm: virtio_rng: Test virtio-rng with faked device
Add a regression test for virtio-rng reading beyond the end of its
buffer if the virtio device provides an invalid length.
Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andrew Scull [Mon, 16 May 2022 10:41:39 +0000 (10:41 +0000)]
virtio: rng: Check length before copying
Check the length of data written by the device is consistent with the
size of the buffers to avoid out-of-bounds memory accesses in case
values aren't consistent.
Signed-off-by: Andrew Scull <ascull@google.com>
Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andrew Scull [Mon, 16 May 2022 10:41:38 +0000 (10:41 +0000)]
test: dm: virtio: Test virtio device driver probing
Once the virtio-rng driver has been bound, probe it to trigger the pre
and post child probe hooks of the virtio uclass driver. Check the status
of the virtio device to confirm it reached the expected state.
Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andrew Scull [Mon, 16 May 2022 10:41:37 +0000 (10:41 +0000)]
virtio: sandbox: Bind RNG rather than block device
The virtio-rng driver is extremely simple, making it suitable for
testing more of the virtio uclass logic. Have the sandbox driver bind
the virtio-rng driver rather than the virtio-blk driver so it can be
used in tests.
Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andrew Scull [Mon, 16 May 2022 10:41:36 +0000 (10:41 +0000)]
test: dm: virtio: Split out virtio device tests
Virtio tests that find a child device require the virtio device driver
to be included in the build so it can probe. The sandbox virtio
transport driver currently reports a virtio-blk device so make sure the
corresponding driver is built before running tests that need it.
Signed-off-by: Andrew Scull <ascull@google.com>
Andrew Scull [Mon, 16 May 2022 10:41:35 +0000 (10:41 +0000)]
test: dm: virtio: Test notify before del_vqs
The virtqueue is passed to virtio_notify() so move the virtqueue
deletion to the end of the test when it's no longer needed. This wasn't
causing any problems because the sandbox virtio transport driver doesn't
do anything for notifications, but it could cause problems if things
change and it was a bad example.
Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>