platform/kernel/u-boot.git
4 years agoMerge tag 'u-boot-amlogic-20201105' of https://gitlab.denx.de/u-boot/custodians/u...
Tom Rini [Fri, 6 Nov 2020 13:42:11 +0000 (08:42 -0500)]
Merge tag 'u-boot-amlogic-20201105' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- meson64_android: don't show logo on ROM USB boot
- doc: update support matrix and fix vim3/l build instructions
- meson64: relocate config_distro_bootcmmd header

4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
Tom Rini [Fri, 6 Nov 2020 13:41:49 +0000 (08:41 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- Add a new SMBIOS parser and enable it when booting from coreboot
- Fix up various driver names to avoid dtoc warnings
- Fully enable ACPI support on Google Chromebook Coral
- Add a way to set SMBIOS properties using the devicetree
- Update existing boards to use devicetree for SMBIOS using a new
  default sysinfo driver

4 years agoMakefile: Fix calling make with V=1
Pali Rohár [Wed, 4 Nov 2020 09:34:35 +0000 (10:34 +0100)]
Makefile: Fix calling make with V=1

Calling 'make V=1 all' on Ubuntu 18.04 with gcc version 9.2.1 and GNU Make
version 4.1 fails on error:

    scripts/Kbuild.include:220: *** Recursive variable 'echo-cmd' references itself (eventually).  Stop.

As a workaround expand 'echo-cmd' variable via 'call' construction instead
of expanding it directly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reported-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Fixes: ae897022d7bd ("Makefile: Fix u-boot-nodtb.bin target")
4 years agosmbios: Drop the unused Kconfig options
Simon Glass [Thu, 5 Nov 2020 13:32:18 +0000 (06:32 -0700)]
smbios: Drop the unused Kconfig options

Now that we can use devicetree to specify this information, drop the old
CONFIG options.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Provide default SMBIOS manufacturer/product
Simon Glass [Thu, 5 Nov 2020 13:32:17 +0000 (06:32 -0700)]
x86: Provide default SMBIOS manufacturer/product

Add a file containing defaults for these, using the existing CONFIG
options. This file must be included with #include since it needs to
be passed through the C preprocessor.

Enable the driver for all x86 boards that generate SMBIOS tables.
Disable it for coral since it has its own driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: reword the commit message a little bit]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: galileo: Use devicetree for SMBIOS settings
Simon Glass [Thu, 5 Nov 2020 13:32:16 +0000 (06:32 -0700)]
x86: galileo: Use devicetree for SMBIOS settings

Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoarm64: mvebu: Use devicetree for SMBIOS settings on uDPU
Simon Glass [Thu, 5 Nov 2020 13:32:15 +0000 (06:32 -0700)]
arm64: mvebu: Use devicetree for SMBIOS settings on uDPU

Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoodroid-c2: Use devicetree for SMBIOS settings
Simon Glass [Thu, 5 Nov 2020 13:32:14 +0000 (06:32 -0700)]
odroid-c2: Use devicetree for SMBIOS settings

Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoimx: Use devicetree for SMBIOS settings on MYiR MYS-6ULX
Simon Glass [Thu, 5 Nov 2020 13:32:13 +0000 (06:32 -0700)]
imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULX

Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agorockchip: Use devicetree for SMBIOS settings
Simon Glass [Thu, 5 Nov 2020 13:32:12 +0000 (06:32 -0700)]
rockchip: Use devicetree for SMBIOS settings

Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agosysinfo: Provide a default driver to set SMBIOS values
Simon Glass [Thu, 5 Nov 2020 13:32:11 +0000 (06:32 -0700)]
sysinfo: Provide a default driver to set SMBIOS values

Some boards want to specify the manufacturer or product name but do not
need to have their own sysinfo driver.

Add a default driver which provides a way to specify this SMBIOS
information in the devicetree, without needing any board-specific
functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agosmbios: Add documentation and devicetree binding
Simon Glass [Thu, 5 Nov 2020 13:32:10 +0000 (06:32 -0700)]
smbios: Add documentation and devicetree binding

Add information about how to set SMBIOS properties using the devicetree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agosmbios: Add more properties
Simon Glass [Thu, 5 Nov 2020 13:32:09 +0000 (06:32 -0700)]
smbios: Add more properties

The current tables only support a subset of the available fields defined
by the SMBIOS spec. Add a few more.

We could use CONFIG_SYS_CPU or CONFIG_SYS_SOC as a default for family, but
the meaning of that value relates more to the whole system rather than
just the SoC.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agosmbios: Allow properties to come from the device tree
Simon Glass [Thu, 5 Nov 2020 13:32:08 +0000 (06:32 -0700)]
smbios: Allow properties to come from the device tree

Support a way to put SMBIOS properties in the device tree. These can be
placed in a 'board' device in an 'smbios' subnode.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Pass an ofnode into each SMBIOS function
Simon Glass [Thu, 5 Nov 2020 13:32:07 +0000 (06:32 -0700)]
x86: Pass an ofnode into each SMBIOS function

As a first step to obtaining SMBIOS information from the devicetree, add
an ofnode parameter to the writing functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agodoc: Add a binding for sysinfo
Simon Glass [Thu, 5 Nov 2020 13:32:06 +0000 (06:32 -0700)]
doc: Add a binding for sysinfo

Add a simple binding file for this, so that it is clear what this binding
directory is for.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoboard: Rename uclass to sysinfo
Simon Glass [Thu, 5 Nov 2020 13:32:05 +0000 (06:32 -0700)]
board: Rename uclass to sysinfo

This uclass is intended to provide a way to obtain information about a
U-Boot board. But the concept of a U-Boot 'board' is the whole system,
not just one circuit board, meaning that 'board' is something of a
misnomer for this uclass.

In addition, the name 'board' is a bit overused in U-Boot and we want to
use the same uclass to provide SMBIOS information.

The obvious name is 'system' but that is so vague as to be meaningless.
Use 'sysinfo' instead, since this uclass is aimed at providing information
on the system.

Rename everything accordingly.

Note: Due to the patch delta caused by the symbol renames, this patch
shows some renamed files as being deleted in one place and created in
another.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: zimage: Quieten down the zimage boot process
Simon Glass [Wed, 4 Nov 2020 16:59:15 +0000 (09:59 -0700)]
x86: zimage: Quieten down the zimage boot process

Much of the output is not very useful. The bootm command is quite a bit
quieter. Convert some output to use log_debug().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
4 years agox86: zimage: Sanity-check the kernel version before printing it
Simon Glass [Wed, 4 Nov 2020 16:59:14 +0000 (09:59 -0700)]
x86: zimage: Sanity-check the kernel version before printing it

With Chrome OS the kernel setup block is stored in a separate place from
the kernel, so it is not possible to access the kernel version string.
At present, garbage is printed.

Add a sanity check to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: zimage: Add a little more logging
Simon Glass [Wed, 4 Nov 2020 16:59:13 +0000 (09:59 -0700)]
x86: zimage: Add a little more logging

Add logging for each part of the boot process, using a new

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
4 years agox86: fsp: Adjust calculations for MTRR range and DRAM top
Simon Glass [Wed, 4 Nov 2020 16:57:43 +0000 (09:57 -0700)]
x86: fsp: Adjust calculations for MTRR range and DRAM top

At present the top of available DRAM is the same as the top of the range
of the low-memory MTRR.

In fact, U-Boot is allowed to use memory up until the start of the FSP
reserved memory. Use that value for low_end, since it makes more memory
available.

Keep the same calculation as before for mtrr_top, i.e. the top of
reserved memory.

A side-effect of this change is that the E820 tables have a single entry
that extends from the bottom of the memory used by U-Boot to the bottom
of the FSP reserved memory. This includes the bloblist, if ACPI tables
are placed there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: pinctrl: Silence the warning when a pin is not found
Simon Glass [Wed, 4 Nov 2020 16:57:42 +0000 (09:57 -0700)]
x86: pinctrl: Silence the warning when a pin is not found

This does not necessarily indicate a problem, since some pins are
optional. Let the caller show an error if necessary.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agox86: acpi: Don't show the UART address by default
Simon Glass [Wed, 4 Nov 2020 16:57:41 +0000 (09:57 -0700)]
x86: acpi: Don't show the UART address by default

This is useful when using Linux's earlycon since the MMIO address must be
provided on some platforms, e.g.:

   earlycon=uart8250,mmio32,0xddffc000,115200n8

However this is only for debugging, so don't show it by default.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: acpi: Include the TPMv1 table only if needed
Simon Glass [Wed, 4 Nov 2020 16:57:40 +0000 (09:57 -0700)]
x86: acpi: Include the TPMv1 table only if needed

This table is not needed if a v2 TPM is in use. Add a condition to avoid
adding it when not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Silence some logging statements
Simon Glass [Wed, 4 Nov 2020 16:57:39 +0000 (09:57 -0700)]
x86: Silence some logging statements

Quite a few log_info() calls are included in the x86 code which should use
log_debug() instead. Convert them to reduce unwanted output.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: fsp: Convert fsp_dram to use log_debug()
Simon Glass [Wed, 4 Nov 2020 16:57:38 +0000 (09:57 -0700)]
x86: fsp: Convert fsp_dram to use log_debug()

Use log_debug() instead of debug() in this file, to enable the extra
features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Boot coral into Chrome OS by default
Simon Glass [Wed, 4 Nov 2020 16:57:37 +0000 (09:57 -0700)]
x86: Boot coral into Chrome OS by default

Add a script to boot Chrome OS from the internal MMC. This involved adding
a few commands and options.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Set up Chrome OS to boot into developer mode
Simon Glass [Wed, 4 Nov 2020 16:57:36 +0000 (09:57 -0700)]
x86: Set up Chrome OS to boot into developer mode

Set up a few fields necessarily to make Chrome OS boot without showing a
firmware error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Use CONFIG_CHROMEOS_VBOOT for verified boot
Simon Glass [Wed, 4 Nov 2020 16:57:35 +0000 (09:57 -0700)]
x86: Use CONFIG_CHROMEOS_VBOOT for verified boot

At present CONFIG_CHROMEOS is used to determine whether verified boot is
in use. The code to implement that is not in U-Boot mainline.

However, it is useful to be able to boot a Chromebook in developer mode
in U-Boot mainline without needing the verified boot code.

To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot
should be used, and CONFIG_CHROMEOS to indicate that the board supports
Chrome OS. That allows us to define CONFIG_CHROMEOS on coral.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Define the Chrome OS GNVS region
Simon Glass [Wed, 4 Nov 2020 16:57:34 +0000 (09:57 -0700)]
x86: Define the Chrome OS GNVS region

It is not possible to boot Chrome OS properly without passing some basic
information from U-Boot. This applies even if verified boot is not being
used. Add a structure definition for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoacpi: Don't reset the tables with every new generation
Simon Glass [Wed, 4 Nov 2020 16:57:33 +0000 (09:57 -0700)]
acpi: Don't reset the tables with every new generation

At present if SSDT and DSDT code is created, only the latter is retained
for examination by the 'acpi items' command. Fix this by only resetting
the list when explicitly requested.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: acpi: Put the generated code first in DSDT
Simon Glass [Wed, 4 Nov 2020 16:57:32 +0000 (09:57 -0700)]
x86: acpi: Put the generated code first in DSDT

The current implementation for DSDT tables is not correct for the case
where there is generated code, as the length ends up being incorrect.
Also, we want the generated code to go first in the table.

Rewrite this piece to correct these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: acpi: Allow the SSDT to be empty
Simon Glass [Wed, 4 Nov 2020 16:57:31 +0000 (09:57 -0700)]
x86: acpi: Allow the SSDT to be empty

If there is nothing in the SSDT we should not include it in the tables.
Update the implementation to check this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoacpi: Correct reset handling in acpi_device_add_power_res()
Simon Glass [Wed, 4 Nov 2020 16:57:30 +0000 (09:57 -0700)]
acpi: Correct reset handling in acpi_device_add_power_res()

If there is no reset line, this still emits ACPI code for the reset GPIO.
Fix it by updating the check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: sound: Correct error handling
Simon Glass [Wed, 4 Nov 2020 16:57:29 +0000 (09:57 -0700)]
x86: sound: Correct error handling

A few functions have changed to return pin numbers or I2C addresses. The
error checking for some of the callers is therefore wrong. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Show the interrupt pointer with 'irqinfo'
Simon Glass [Wed, 4 Nov 2020 16:57:28 +0000 (09:57 -0700)]
x86: Show the interrupt pointer with 'irqinfo'

It is useful for this command to show the address of the interrupt table.
Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: nhlt: Fix a few bugs in the table generation
Simon Glass [Wed, 4 Nov 2020 16:57:27 +0000 (09:57 -0700)]
x86: nhlt: Fix a few bugs in the table generation

At present these tables do not have the correct header, and there is an
occasional incorrect value due to uninited data. Fix these bugs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: nhlt: Correct output of bytes and 16-bit data
Simon Glass [Wed, 4 Nov 2020 16:57:26 +0000 (09:57 -0700)]
x86: nhlt: Correct output of bytes and 16-bit data

At present these functions are incorrect. Fix them and add some logging
and checking to avoid future problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Allow putting some tables in the bloblist
Simon Glass [Wed, 4 Nov 2020 16:57:25 +0000 (09:57 -0700)]
x86: Allow putting some tables in the bloblist

At present all tables are placed starting at address f0000 in memory, and
can be up to 64KB in size. If the tables are very large, this may not
provide enough space.

Also if the tables point to other tables (such as console log or a ramoops
area) then we must allocate other memory anyway.

The bloblist is a nice place to put these tables since it is contiguous,
which makes it easy to reserve this memory for linux using the 820 tables.

Add an option to put some of the tables in the bloblist. For SMBIOS and
ACPI, create suitable pointers from the f0000 region to the new location
of the tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed in http://patchwork.ozlabs.org/project/uboot/patch/
 20201105062407.1.I8091ad931cbbb5e3b6f6ababdf3f8d5db0d17bb9@changeid/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoMerge tag 'u-boot-imx-20201105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Tom Rini [Thu, 5 Nov 2020 16:57:50 +0000 (11:57 -0500)]
Merge tag 'u-boot-imx-20201105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx for 2021.1
---------------------

- new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM
- converted doc to reST
- fixes for verdin-imx8mm (Toradex)
- fixes for i.MX thermal driver
- mx7ulp: Align the PLL_USB frequency
- mx53: primary/secondary bmode

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284

4 years agoconfigs: meson64: relocate config_distro_bootcmmd header
Jaehoon Chung [Mon, 2 Nov 2020 03:07:06 +0000 (12:07 +0900)]
configs: meson64: relocate config_distro_bootcmmd header

Relocate a config_distro_bootcmd header before defined
CONFIG_EXTRA_ENV_SETTINGS. Otherwise it can't change to specific
environment.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agodoc: board: vim3: Fix build instructions
Neil Armstrong [Thu, 5 Nov 2020 15:18:57 +0000 (16:18 +0100)]
doc: board: vim3: Fix build instructions

The build instructions were buggy and changed a little since they
were written.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agodoc: board: amlogic: Update support matrix
Neil Armstrong [Thu, 5 Nov 2020 15:18:56 +0000 (16:18 +0100)]
doc: board: amlogic: Update support matrix

Update the matrix table with new supported features and
new SoC features to support.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agox86: Use if instead of #ifdef in write_tables()
Simon Glass [Wed, 4 Nov 2020 16:57:24 +0000 (09:57 -0700)]
x86: Use if instead of #ifdef in write_tables()

Use if() to remove the extra build path in this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add SMBIOS info for Coral
Simon Glass [Wed, 4 Nov 2020 16:57:22 +0000 (09:57 -0700)]
x86: Add SMBIOS info for Coral

This is required by Chrome OS so that the audio and other unibuild
features work correctly. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: coral: Drop the duplicate PCIe settings
Simon Glass [Wed, 4 Nov 2020 16:57:21 +0000 (09:57 -0700)]
x86: coral: Drop the duplicate PCIe settings

These settings are included twice. The second lot are correct, so drop the
others.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Don't bother clearing global NVS
Simon Glass [Wed, 4 Nov 2020 16:57:20 +0000 (09:57 -0700)]
x86: Don't bother clearing global NVS

The bloblist guarantees that blobs are zeroed so there is no need to do
an additional memset(). Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: acpi: Store the ACPI context in global_data
Simon Glass [Wed, 4 Nov 2020 16:57:19 +0000 (09:57 -0700)]
x86: acpi: Store the ACPI context in global_data

At present we create the ACPI context but then drop it after generation of
tables is complete. This is annoying because we have to then search for
tables later.

To fix this, allocate the context and store it in global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Allow writing tables to fail
Simon Glass [Wed, 4 Nov 2020 16:57:18 +0000 (09:57 -0700)]
x86: Allow writing tables to fail

At present write_tables() can fail but does not report this problem to its
caller. Fix this by changing the return type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add support for private files
Simon Glass [Wed, 4 Nov 2020 16:57:17 +0000 (09:57 -0700)]
x86: Add support for private files

Some boards need to include binary data into the image for use during the
boot process. Add a node for these.

An example is the audio-codec configuration used by some audio drivers on
Intel platforms. If no private files are provided, they will be omitted.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add a layout for Chrome OS verified boot
Simon Glass [Wed, 4 Nov 2020 16:57:16 +0000 (09:57 -0700)]
x86: Add a layout for Chrome OS verified boot

Add definitions for part of the vboot context used with verified boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add core init for the SoC
Simon Glass [Wed, 4 Nov 2020 16:57:15 +0000 (09:57 -0700)]
x86: apl: Add core init for the SoC

Set up MSRs required for Apollo Lake. This enables Linux to use the
timers correctly. Also write the fixed MSRs for this platform.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoAdd an assembly guard around linux/bitops.h
Simon Glass [Wed, 4 Nov 2020 16:57:14 +0000 (09:57 -0700)]
Add an assembly guard around linux/bitops.h

This file can be included by any header but it includes C code. Guard it
to avoid errors when compiling ASL, etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agocoreboot: make use of smbios parser
Christian Gmeiner [Tue, 3 Nov 2020 14:34:52 +0000 (15:34 +0100)]
coreboot: make use of smbios parser

If u-boot gets used as coreboot payload it might be nice to get
vendor, model and bios version from smbios. I am not sure about
the output of all the read information.

With qemu target for coreboot this could look this:

CBFS: Found @ offset 14f40 size 3b188
Checking segment from ROM address 0xffc15178
Checking segment from ROM address 0xffc15194
Loading segment from ROM address 0xffc15178
  code (compression=1)
  New segment dstaddr 0x01110000 memsize 0x889ef srcaddr 0xffc151b0 filesize 0x3b150
Loading Segment: addr: 0x01110000 memsz: 0x00000000000889ef filesz: 0x000000000003b150
using LZMA
Loading segment from ROM address 0xffc15194
  Entry Point 0x01110000
BS: BS_PAYLOAD_LOAD run times (exec / console): 77 / 1 ms
Jumping to boot code at 0x01110000(0x07fa7000)

U-Boot 2020.10-00536-g5dcf7cc590-dirty (Oct 07 2020 - 14:21:51 +0200)

CPU: x86_64, vendor AMD, device 663h
DRAM:  127.1 MiB
MMC:
Video: No video mode configured in coreboot!
Video: No video mode configured in coreboot!
Vendor: QEMU
Model: Standard PC (i440FX + PIIX, 1996)
Bios Version: 4.12-3152-g326a499f6f-dirty
Net:   e1000: 52:54:00:12:34:56
       eth0: e1000#0
No working controllers found
Finalizing coreboot
Hit any key to stop autoboot:  0

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agosmbios: add parsing API
Christian Gmeiner [Tue, 3 Nov 2020 14:34:51 +0000 (15:34 +0100)]
smbios: add parsing API

Add a very simple API to be able to access SMBIOS strings
like vendor, model and bios version.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Fix up driver names to avoid dtoc warnings
Simon Glass [Mon, 5 Oct 2020 11:27:01 +0000 (05:27 -0600)]
x86: Fix up driver names to avoid dtoc warnings

At present there are a lot of dtoc warnings reported when building
chromebook_coral, of the form:

   WARNING: the driver intel_apl_lpc was not found in the driver list

Correct these by using driver names that matches their compatible string.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agocros_ec: Fix up driver names to avoid dtoc warnings
Simon Glass [Mon, 5 Oct 2020 11:27:00 +0000 (05:27 -0600)]
cros_ec: Fix up driver names to avoid dtoc warnings

Fix the dtoc warning in these file by using a driver name that matches the
compatible string.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoboard: ge: b1x5v2: Add MAINTAINERS
Sebastian Reichel [Wed, 4 Nov 2020 16:18:37 +0000 (17:18 +0100)]
board: ge: b1x5v2: Add MAINTAINERS

Introduce maintainers file for the GE B1x5 board.

Cc: Huan 'Kitty' Wang <HuanWang@ge.com>
Cc: Ian Ray <ian.ray@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agoboard: ge: ppd: Update MAINTAINERS
Sebastian Reichel [Wed, 4 Nov 2020 16:18:36 +0000 (17:18 +0100)]
board: ge: ppd: Update MAINTAINERS

This updates the PPD MAINTAINERS file doing a couple of changes:

 * Replace Martyn with myself, since he no longer has the hardware
   available and add Ian Ray as maintainer
 * Fix the board directory path, which was still listing freescale/
   instead of ge/
 * Order the list of files alphabetically
 * Add board specific device tree files to the file list

Cc: Martyn Welch <martyn.welch@collabora.com>
Cc: Ian Ray <ian.ray@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agoboard: ge: bx50v3: Update MAINTAINERS
Sebastian Reichel [Wed, 4 Nov 2020 16:18:35 +0000 (17:18 +0100)]
board: ge: bx50v3: Update MAINTAINERS

This updates the Bx50v3 MAINTAINERS file, so that it also catches
changes to the related device tree files. Additionally the list of
files has been sorted alphabetically and I added myself as maintainer.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agoarch: Move NEEDS_MANUAL_RELOC symbol to Kconfig
Michal Simek [Wed, 4 Nov 2020 14:33:20 +0000 (15:33 +0100)]
arch: Move NEEDS_MANUAL_RELOC symbol to Kconfig

CONFIG_NEEDS_MANUAL_RELOC macro was out of Kconfig. Move it there to be
able to use compile-time checks to reduce the number of build paths.

Fixes: f9a882438966 ("dm: core: Convert #ifdef to if() in root.c") for Microblaze
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
4 years agoenv: sf: fix init function behaviour
Heiko Schocher [Tue, 3 Nov 2020 14:22:36 +0000 (15:22 +0100)]
env: sf: fix init function behaviour

Michael wrote:
commit 92765f45bb95 ("env: Access Environment in SPI flashes before
relocation") at least breaks the Kontron sl28 board. I guess it also
breaks others which use a (late) SPI environment.

reason is, that env_init() sets the init bit, if there
is no init function defined in an environment driver,
and use default return value -ENOENT in this case
later for setting the default environment.

Change:
Environment driver can now implement an init
function and return, if this function does nothing,
simply -ENOENT.

env_init() now handles -ENOENT correct by setting the
inited bit for the environment driver. And if there
is no other environment driver whose init function
returns 0, load than the default environment.

This prevents that each environment driver needs to set the
default environment.

Fixes: 92765f45bb95 ("env: Access Environment in SPI flashes before relocation")
Reported-by: Michael Walle <michael@walle.cc>
Tested-by: Michael Walle <michael@walle.cc> [For the SF environment]
Signed-off-by: Heiko Schocher <hs@denx.de>
4 years agoMerge tag 'u-boot-atmel-fixes-2021.01-a' of https://gitlab.denx.de/u-boot/custodians...
Tom Rini [Mon, 2 Nov 2020 14:01:28 +0000 (09:01 -0500)]
Merge tag 'u-boot-atmel-fixes-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel fixes for 2021.01 cycle:

This specific feature set includes the patches for DT required to fix
the warnings for newer DTC version (1.6.0+), i2c and spi bus unit
address.

4 years agoARM: dts: at91: sama5d3xmb_cmp: fix SPI bus unit address
Eugen Hristev [Mon, 26 Oct 2020 08:39:54 +0000 (10:39 +0200)]
ARM: dts: at91: sama5d3xmb_cmp: fix SPI bus unit address

w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
4 years agoARM: dts: at91: sam9260ek: fix SPI bus unit address
Eugen Hristev [Mon, 26 Oct 2020 08:39:53 +0000 (10:39 +0200)]
ARM: dts: at91: sam9260ek: fix SPI bus unit address

w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
4 years agoARM: dts: at91: sama5d3xmb: fix I2C bus unit address
Eugen Hristev [Mon, 26 Oct 2020 08:39:52 +0000 (10:39 +0200)]
ARM: dts: at91: sama5d3xmb: fix I2C bus unit address

w+arch/arm/dts/sama5d3xmb.dtsi:64.25-83.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/camera@0x30: I2C bus unit address format error, expected "30"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
4 years agoARM: dts: at91: gurnard: fix SPI bus unit address
Eugen Hristev [Mon, 26 Oct 2020 08:39:51 +0000 (10:39 +0200)]
ARM: dts: at91: gurnard: fix SPI bus unit address

w+arch/arm/dts/.at91sam9g45-gurnard.dtb.pre.tmp:118.21-122.7: Warning (spi_bus_reg): /ahb/apb/spi@fffa4000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
4 years agoARM: dts: at91: at91sam9g25ek: fix I2C bus unit address
Eugen Hristev [Mon, 26 Oct 2020 08:39:50 +0000 (10:39 +0200)]
ARM: dts: at91: at91sam9g25ek: fix I2C bus unit address

w+arch/arm/dts/.at91sam9g25ek.dtb.pre.tmp:28.25-47.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8010000/camera@0x30: I2C bus unit address format error, expected "30"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
4 years agoARM: dts: at91: at91sam9g20ek_common: fix SPI bus unit address
Eugen Hristev [Mon, 26 Oct 2020 08:39:49 +0000 (10:39 +0200)]
ARM: dts: at91: at91sam9g20ek_common: fix SPI bus unit address

w+arch/arm/dts/at91sam9g20ek_common.dtsi:100.21-104.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
4 years agoARM: dts: at91: at91sam9g20-taurus: fix SPI bus unit address
Eugen Hristev [Mon, 26 Oct 2020 08:39:48 +0000 (10:39 +0200)]
ARM: dts: at91: at91sam9g20-taurus: fix SPI bus unit address

w+arch/arm/dts/.at91sam9g20-taurus.dtb.pre.tmp:79.18-83.4: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
4 years agoARM: dts: at91: at91sam9261ek: fix SPI unit address warning
Eugen Hristev [Mon, 26 Oct 2020 08:39:47 +0000 (10:39 +0200)]
ARM: dts: at91: at91sam9261ek: fix SPI unit address warning

w+arch/arm/dts/.at91sam9261ek.dtb.pre.tmp:124.15-144.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/tsc2046@0: SPI bus unit address format error, expected "2"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
4 years agoARM: dts: at91: vinco: fix I2C warning bus unit address
Eugen Hristev [Mon, 26 Oct 2020 08:39:46 +0000 (10:39 +0200)]
ARM: dts: at91: vinco: fix I2C warning bus unit address

w+arch/arm/dts/.at91-vinco.dtb.pre.tmp:131.18-134.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8024000/rtc@64: I2C bus unit address format error, expected "32"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
4 years agoMerge tag 'efi-2020-01-rc2-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Sun, 1 Nov 2020 15:56:37 +0000 (10:56 -0500)]
Merge tag 'efi-2020-01-rc2-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2021-01-rc2 (2)

The series contains the following enhancements

* preparatory patches for UEFI capsule updates
* initialization of the emulated RTC using an environment variable

and a bug fix

* If DisconnectController() is called for a child controller that is the
  only child of the driver, the driver must be disconnected.

4 years agoboard: ge: b1x5v2: Add GE B1x5v2 and B1x5Pv2
Sebastian Reichel [Wed, 2 Sep 2020 17:31:46 +0000 (19:31 +0200)]
board: ge: b1x5v2: Add GE B1x5v2 and B1x5Pv2

GE B1x5v2 patient monitor series is similar to the CARESCAPE Monitor
series (GE Bx50). It consists of a carrier PCB used in combination
with a Congatec QMX6 SoM. This adds U-Boot support using device model
everywhere and SPL for memory initialization.

Proper configuration is provided as 'ge_b1x5v2_defconfig' and the
combined image u-boot-with-spi.imx can be flashed directly to 1024
byte offset to /dev/mtdblock0. Alternatively SPL and u-boot.imx can
be loaded separately via USB-OTG using e.g. imx_usb.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoboard: ge: common: vpd: separate I2C specific code
Sebastian Reichel [Wed, 2 Sep 2020 17:31:45 +0000 (19:31 +0200)]
board: ge: common: vpd: separate I2C specific code

This separates the I2C specific code from the generic
GE vital product data code, so that the generic parts
can be used on hardware with VPD stored in SPI flash
memory.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agoboard: ge: common: add config option for RTC and VPD feature
Sebastian Reichel [Wed, 2 Sep 2020 17:31:44 +0000 (19:31 +0200)]
board: ge: common: add config option for RTC and VPD feature

While this code is being used by all GE platforms its useful
to have it behind a config option for hardware bringup of
new platforms.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agoboard: ge: common: rename ge_common.c to ge_rtc.c
Sebastian Reichel [Wed, 2 Sep 2020 17:31:43 +0000 (19:31 +0200)]
board: ge: common: rename ge_common.c to ge_rtc.c

The file only contains RTC related code, so let's name
it accordingly.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agosysreset: Add poweroff-gpio driver
Sebastian Reichel [Wed, 2 Sep 2020 17:31:42 +0000 (19:31 +0200)]
sysreset: Add poweroff-gpio driver

Add GPIO poweroff driver, which is based on the Linux
driver and uses the same DT binding.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agoimx6: allow usage of disable_ldb_di_clock_sources for CONFIG_MX6QDL
Sebastian Reichel [Wed, 2 Sep 2020 17:31:41 +0000 (19:31 +0200)]
imx6: allow usage of disable_ldb_di_clock_sources for CONFIG_MX6QDL

Allow using disable_ldb_di_clock_sources with just the combined
CONFIG_MX6QDL being enabled.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agortc: m41t62: add oscillator fail bit reset support
Sebastian Reichel [Wed, 2 Sep 2020 17:31:40 +0000 (19:31 +0200)]
rtc: m41t62: add oscillator fail bit reset support

In case of empty battery or glitches the oscillator fail
bit might be set. This will reset the bit in the reset
routine.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agortc: m41t62: reset SQW in m41t62_rtc_reset
Sebastian Reichel [Wed, 2 Sep 2020 17:31:39 +0000 (19:31 +0200)]
rtc: m41t62: reset SQW in m41t62_rtc_reset

This takes care of resetting the 32kHz square wave, which is
used by some boards as clock source for the SoC.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agobootcount: add a DM SPI flash backing store for bootcount
Sebastian Reichel [Wed, 2 Sep 2020 17:31:38 +0000 (19:31 +0200)]
bootcount: add a DM SPI flash backing store for bootcount

This driver allows to use SPI flash as backing store for
boot counter values with DM enabled.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
4 years agoboard: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support
Teresa Remmet [Fri, 21 Aug 2020 07:55:53 +0000 (09:55 +0200)]
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support

Add support PHYTEC phyCORE-i.MX8MM SOM.

Supported features:
 - 2GB LPDDR4 RAM
 - 1x 1Gbit Ethernet
 - eMMC
 - external SD
 - debug UART3
 - watchdog
 - i2c eeprom

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
4 years agoARM: imx: Add support for the primary/secondary bmode to MX53
Marek Vasut [Fri, 4 Sep 2020 22:53:01 +0000 (00:53 +0200)]
ARM: imx: Add support for the primary/secondary bmode to MX53

Implement the 'getprisec' subcommand of 'bmode' command for i.MX53 and
also the primary/secondary bootmode switching.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
4 years agowatchdog: Hide WATCHDOG_RESET_DISABLE
Michael Walle [Thu, 24 Sep 2020 08:09:15 +0000 (10:09 +0200)]
watchdog: Hide WATCHDOG_RESET_DISABLE

This option is only supported by the IMX watchdog and seems to be
similar to CONFIG_WATCHDOG.

Move it below the IMX watchdog and make it dependent on IMX_WATCHDOG.

Signed-off-by: Michael Walle <michael@walle.cc>
4 years agodefconfig: Enable CONFIG_SHOW_BOOT_PROGRESS for imx53's HSC and DDC devices
Lukasz Majewski [Fri, 25 Sep 2020 15:13:11 +0000 (17:13 +0200)]
defconfig: Enable CONFIG_SHOW_BOOT_PROGRESS for imx53's HSC and DDC devices

This option allows using show_boot_progress to visualize the state of
boot process.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
4 years agodts: Provide LED DTS description for HSC and DDC imx53 devices
Lukasz Majewski [Fri, 25 Sep 2020 15:13:10 +0000 (17:13 +0200)]
dts: Provide LED DTS description for HSC and DDC imx53 devices

Those two LEDs are used to indicate U-Boot's boot stage.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
4 years agoarm: Implement show_boot_progress() for imx53's HSC and DDC devices
Lukasz Majewski [Fri, 25 Sep 2020 15:13:09 +0000 (17:13 +0200)]
arm: Implement show_boot_progress() for imx53's HSC and DDC devices

This patch provides information regarding the boot stage with using LEDs.
On the very beginning of U-Boot execution the GREEN LED is turned on.
When the execution is passed to Linux kernel the GREEN LED is off and
RED one is ON.

Afterwards, when Linux takes over the execution, the "heartbeat" driver
provides indication if the board is still alive.

Please also note that this patch uses {set|clr}bits_le32 macros as turning
ON GREEN LED is performed in a _very_ early stage of U-Boot execution
before DM_GPIOs are initialized.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
4 years agomx7ulp: clock: Align the PLL_USB frequency
Fabio Estevam [Wed, 7 Oct 2020 11:09:32 +0000 (08:09 -0300)]
mx7ulp: clock: Align the PLL_USB frequency

The command 'clocks' shows the following output:

=> clocks
PLL_A7_SPLL         528 MHz
PLL_A7_APLL         529 MHz
PLL_USB           0 MHz

Add some extra spaces so that the PLL_USB information gets aligned with
the previous reported frequencies.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
4 years agomx7ulp: clock: Remove unuseful information
Fabio Estevam [Wed, 7 Oct 2020 11:09:31 +0000 (08:09 -0300)]
mx7ulp: clock: Remove unuseful information

The command 'clocks' shows the following output:

=> clocks
PLL_A7_SPLL         528 MHz
PLL_A7_APLL         529 MHz
PLL_USB           0 MHz

....

[do_mx7_showclocks] addr = 0x9FFB61F1

The last line is not useful at all, so just remove it.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
4 years agothermal: imx_tmu: fix missing include
Tim Harvey [Mon, 12 Oct 2020 19:21:54 +0000 (12:21 -0700)]
thermal: imx_tmu: fix missing include

commit c05ed00afb dropped linux/delay.h from common header

add linux/delay.h to avoid compile warning here

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
4 years agoimx: cpu: terminate line with CR if invalid temp sensor
Tim Harvey [Mon, 12 Oct 2020 19:26:41 +0000 (12:26 -0700)]
imx: cpu: terminate line with CR if invalid temp sensor

Ensure we terminate the line with a CR if we get an invalid sensor device
or reading.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
4 years agomx6: peripheral clock from oscillator
Jorge Ramirez-Ortiz [Fri, 23 Oct 2020 19:18:41 +0000 (21:18 +0200)]
mx6: peripheral clock from oscillator

In order to be able to run the I2C bus at 400Khz, the chip errata[1]
recommends that the peripheral clock runs out of the 24MHz oscillator.

Systems running I2C from OP-TEE before Linux executes - for example to
access a Secure Element [2] providing the cryptographic support - expect
this clock to be configured by the bootloader [3].

[1] IMX6SLCE Rev. 5, 02/2019, ERR007805.
[2] OP-TEE: support for NXP SE05X Plug and Trust (patch on the list).
[3] OP-TEE: check the imx_i2c.c driver (imx6 patch on the list).

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
4 years agoverdin-imx8mm: enable fdt overlays and env importing
Igor Opaniuk [Fri, 30 Oct 2020 14:55:02 +0000 (16:55 +0200)]
verdin-imx8mm: enable fdt overlays and env importing

Enable CONFIG_CMD_IMPORTENV and CONFIG_OF_LIBFDT_OVERLAY needed
for booting regular Toradex BSP images.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
4 years agodoc: board: Convert i.MX6ULL EVK README to reST
Peng Fan [Wed, 14 Oct 2020 09:12:10 +0000 (17:12 +0800)]
doc: board: Convert i.MX6ULL EVK README to reST

Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agodoc: board: Convert i.MX6UL 14x14 EVK README to reST
Peng Fan [Wed, 14 Oct 2020 09:12:09 +0000 (17:12 +0800)]
doc: board: Convert i.MX6UL 14x14 EVK README to reST

Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agodoc: board: Convert i.MX6 Sabresd README to reST
Peng Fan [Wed, 14 Oct 2020 09:12:08 +0000 (17:12 +0800)]
doc: board: Convert i.MX6 Sabresd README to reST

Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agodoc: board: Convert i.MX6 Sabreauto README to reST
Peng Fan [Wed, 14 Oct 2020 09:12:07 +0000 (17:12 +0800)]
doc: board: Convert i.MX6 Sabreauto README to reST

Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agodoc: board: Convert i.MXRT1050 EVK README to reST
Peng Fan [Wed, 14 Oct 2020 09:12:06 +0000 (17:12 +0800)]
doc: board: Convert i.MXRT1050 EVK README to reST

Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agodoc: board: Convert i.MXRT1020 EVK README to reST
Peng Fan [Wed, 14 Oct 2020 09:12:05 +0000 (17:12 +0800)]
doc: board: Convert i.MXRT1020 EVK README to reST

Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.

Signed-off-by: Peng Fan <peng.fan@nxp.com>