Franck LENORMAND [Thu, 25 Mar 2021 09:30:24 +0000 (17:30 +0800)]
imx7ulp: Enable support for cmd blob
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Franck LENORMAND [Thu, 25 Mar 2021 09:30:23 +0000 (17:30 +0800)]
caam: enable support for iMX7ULP
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Franck LENORMAND [Thu, 25 Mar 2021 09:30:22 +0000 (17:30 +0800)]
crypto: caam: change JR running loop
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:21 +0000 (17:30 +0800)]
cmd: blob: Instantiate RNG before running CMD_BLOB
U-Boot can instantiate CAAM RNG if needed by crypto operations.
Call sec_init() prior running a blob operation to ensure
RNG is correctly instantiated.
Make sure CAAM clock is enabled and check if a job ring is
available for that operation.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:20 +0000 (17:30 +0800)]
cmd: blob: Add IMX_HAB and CAAM supported SoCs as dependency
In order to build CMD_BLOB on i.MX CAAM supported devices it's
necessary to select IMX_HAB. Add IMX_HAB and CAAM supported
SoCs as dependency.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:19 +0000 (17:30 +0800)]
mx6dq: hab: Fix chip version in hab.h code
Since commit
8891410c729b ("MLK-19848 mx6dq: Fix chip version issue for
rev1.3") it's not possible to call the HAB API functions on i.MX6DQ
SoC Rev 1.3:
Authenticate image from DDR location 0x12000000...
undefined instruction
pc : [<
412c00dc>] lr : [<
8ff560bc>]
reloc pc : [<
c8b6d0dc>] lr : [<
178030bc>]
sp :
8ef444a8 ip :
126e8068 fp :
8ff59aa8
r10:
8ffd51e4 r9 :
8ef50eb0 r8 :
006e8000
r7 :
00000000 r6 :
126ea01f r5 :
0000002b r4 :
126e8000
r3 :
412c00dd r2 :
00000001 r1 :
00000001 r0 :
00000063
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
The hab.h code is defining the HAB API base address according to the
old SoC revision number, thus failing when calling the HAB API
authenticate_image() function.
Fix this issue by using mx6dq rev 1.3 instead of mx6dq rev 1.5.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Thu, 25 Mar 2021 09:30:18 +0000 (17:30 +0800)]
imx: cmd_dek: Enable DEK only for chips supporting CAAM
Since cmd_dek is using CAAM JR, so enable the CMD_DEK only when
HAS_CAAM is set
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Thu, 25 Mar 2021 09:30:17 +0000 (17:30 +0800)]
iMX8M: Add support to enable CONFIG_IMX_HAB
Add some SOC level codes and build configurations to use HAB lib for
CONFIG_IMX_HAB (secure boot), like adding the SEC_CONFIG fuse, enable
fuse driver, CAAM clock function, and add CAAM secure RAM to MMU table.
The FSL_CAAM is temporally not enabled for iMX8M when CONFIG_IMX_HAB is set,
because we don't need the CAAM driver for SPL.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:16 +0000 (17:30 +0800)]
crypto: fsl: blob: Flush dcache range for destination address
The blob command is not working on i.MX7D, i.MX8MQ and i.MX8MM
devices.
Due to different cache management it's necessary to flush dcache
range for destination address so data can be available in memory.
Add necessary operations in blob_encap() and blob_decap() functions.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Thu, 25 Mar 2021 09:30:15 +0000 (17:30 +0800)]
imx: HAB: Add support for iMX8MM
The imx8mm has changed the address of rvt_hab, use new address for imx8mm.
The authentication procedure is same as imx8mq. In u-boot, the authentication
uses SIP call to trap ATF to run HAB authenticate.
Users need to add CONFIG_SECURE_BOOT=y to defconfig to enable the feature.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:14 +0000 (17:30 +0800)]
imx: hab: Fix build warnings in 32-bit targets
When building 32-bit targets with CONFIG_SECURE_BOOT and DEBUG enabled
the following warnings are displayed:
arch/arm/mach-imx/hab.c:840:41: warning: format '%lx' expects argument \
of type 'long unsigned int', but argument 3 has type 'uint32_t \
{aka unsigned int}' [-Wformat=]
printf("HAB check target 0x%08x-0x%08lx fail\n",
~~~~^
%08x
ddr_start, ddr_start + bytes);
arch/arm/mach-imx/hab.c:845:45: warning: format '%x' expects argument \
of type 'unsigned int', but argument 3 has type 'ulong \
{aka long unsigned int}' [-Wformat=]
printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr);
~^
%lx
Fix warnings by providing the correct data type.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:13 +0000 (17:30 +0800)]
mx7ulp: hab: Add hab_status command for HABv4 M4 boot
When booting in low power or dual boot modes the M4 binary is
authenticated by the M4 ROM code.
Add an option in hab_status command so users can retrieve M4 HAB
failure and warning events.
=> hab_status m4
Secure boot disabled
HAB Configuration: 0xf0, HAB State: 0x66
No HAB Events Found!
Add command documentation in mx6_mx7_secure_boot.txt guide.
As HAB M4 API cannot be called from A7 core the code is parsing
the M4 HAB persistent memory region. The HAB persistent memory
stores HAB events, public keys and others HAB related information.
The HAB persistent memory region addresses and sizes can be found
in AN12263 "HABv4 RVT Guidelines and Recommendations".
Reviewed-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:12 +0000 (17:30 +0800)]
imx: hab: Check if IVT header is HABv4
The HABv4 implementation in ROM checks if HAB major version
in IVT header is 4.x.
The current implementation in hab.c code is only validating
HAB v4.0 and HAB v4.1 and may be incompatible with newer
HABv4 versions.
Modify verify_ivt_header() function to align with HABv4
implementation in ROM code.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Utkarsh Gupta [Thu, 25 Mar 2021 09:30:11 +0000 (17:30 +0800)]
imx: hab: Display All HAB events via hab_status command
Add ability for hab_status command to show All HAB events and not just
HAB failure events
Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:10 +0000 (17:30 +0800)]
imx: hab: Enable hab.c to authenticate additional images in open configuration
Currently it's not possible to authenticate additional boot images in HAB
open configuration.
The hab.c code is checking if the SEC_CONFIG[1] fuse is programmed prior
to calling the hab_authenticate_image() API function. Users cannot check
if their additional boot images has been correctly signed prior to closing
their device.
Enable hab.c to authenticate additional boot images in open mode so HAB
events can be retrieved through get_hab_status() function.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Thu, 25 Mar 2021 09:30:09 +0000 (17:30 +0800)]
hab: Change calling to ROM API failsafe
Modify to use hab_rvt_failsafe function for failsafe ROM API, not
directly call its ROM address. This function will wrap the sip call for iMX8M
platforms.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Utkarsh Gupta [Thu, 25 Mar 2021 09:30:08 +0000 (17:30 +0800)]
imx: HAB: Validate IVT before authenticating image
Calling csf_is_valid() with an un-signed image may lead to data abort
as the CSF pointer could be pointing to a garbage address when accessed
in HAB_HDR_LEN(*(const struct hab_hdr *)(ulong)ivt_initial->csf).
Authenticate image from DDR location 0x80800000...
Check CSF for Write Data command before authenticating image
data abort
pc : [<
fff5494c>] lr : [<
fff54910>]
reloc pc : [<
8780294c>] lr : [<
87802910>]
sp :
fdf45dc8 ip :
00000214 fp :
00000000
r10:
fffb6170 r9 :
fdf4fec0 r8 :
00722020
r7 :
80f20000 r6 :
80800000 r5 :
80800000 r4 :
00720000
r3 :
17a5aca3 r2 :
00000000 r1 :
80f2201f r0 :
00000019
Flags: NzcV IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
To avoid such errors during authentication process, validate IVT structure
by calling validate_ivt function which checks the following values in an IVT:
IVT_HEADER = 0x4X2000D1
ENTRY != 0x0
RES1 = 0x0
DCD = 0x0 /* Recommended */
SELF != 0x0 /* Absoulute address of IVT */
CSF != 0x0
RES2 = 0x0
This commit also checks if Image's start address is 4 byte aligned.
commit "
0088d127 MLK-14945 HAB: Check if IVT valid before authenticating image"
removed as this patch addresses the issue.
Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 25 Mar 2021 09:30:07 +0000 (17:30 +0800)]
imx: HAB: Update hab codes to support ARM64 and i.MX8M
There are some changes to support ARM64 i.MX8M platform in this patches:
1. The hab_rvt base and function vectors are different as i.MX6/7
2. Need to bypass an workaround for i.MX6 to fix problem in MMU.
3. The x18 register needed save & restore before calling any HAB API. According
to ARM procedure call spec, the x18 is caller saved when it is used as
temporary register. So calling HAB API may scratch this register, and
cause crash once accessing the gd pointer.
On ARMv7, the r9 is callee saved when it is used as variable register. So
no need to save & restore it.
4. Add SEC_CONFIG fuse for iMX8M
When current EL is not EL3, the direct calling to HAB will fail because
CAAM/SNVS can't initialize at non-secure mode. In this case, we use
SIP call to run the HAB in ATF.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Thu, 25 Mar 2021 09:30:06 +0000 (17:30 +0800)]
imx: hab: Add function to authenticate kernel image
When loading kernel image, the image size is parsed from header, so it
does not include the CSF and IVT.
Add back the authenticate_image function to wrap the imx_hab_authenticate_image
with calculating IVT offset and full image size.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:05 +0000 (17:30 +0800)]
imx: Avoid hardcoded Job Ring Max size
Prior instantiating RNG we have to ensure if the CAAM job rings are
available. Avoid hardcoded job ring max size and use the definition at
fsl_sec.h
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:04 +0000 (17:30 +0800)]
imx: Ensure CAAM clock is enabled prior getting out_jr_size
Prior calling sec_in32() we have to ensure CAAM clock is enabled, the
function sec_in32() is reading CAAM registers and if CAAM clock is disabled
the system will hang.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:03 +0000 (17:30 +0800)]
imx: Avoid hardcoded output ring size register offset (ORSR)
The CAAM output ring size register offset is currently defined in fsl_sec.h
as FSL_CAAM_ORSR_JRa_OFFSET, use this definition to avoid hardcoded value in
i.MX common code.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Breno Lima [Thu, 25 Mar 2021 09:30:02 +0000 (17:30 +0800)]
imx: imx7 Support for Manufacturing Protection
This code was originally developed by Raul Cardenas <raul.casas@nxp.com>
and modified to be applied in U-Boot imx_v2017.03.
More information about the initial submission can be seen
in the link below:
https://lists.denx.de/pipermail/u-boot/2016-February/245273.html
i.MX7D has an a protection feature for Manufacturing process.
This feature uses asymmetric encryption to sign and verify
authenticated software handled between parties. This command
enables the use of such feature.
The private key is unique and generated once per device.
And it is stored in secure memory and only accessible by CAAM.
Therefore, the public key generation and signature functions
are the only functions available for the user.
The manufacturing-protection authentication process can be used to
authenticate the chip to the OEM's server.
Command usage:
Print the public key for the device.
- mfgprot pubk
Generates Signature over given data.
- mfgprot sign <data_address> <data_size>
Signed-off-by: Raul Ulises Cardenas <raul.casas@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 25 Mar 2021 09:30:01 +0000 (17:30 +0800)]
imx8m: add regs used by CAAM
Add regs used by CAAM
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng [Thu, 25 Mar 2021 09:30:00 +0000 (17:30 +0800)]
imx8mn: evk: update MAINTAINERS
Add imx8mn_evk_defconfig to be maintained
Typo fix
Signed-off-by: Peng <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:57:18 +0000 (15:57 +0800)]
imx8mq_evk: Applying default LPDDR4 script for B2
Both i.MX8MQ B1 and B2 should use default LPDDR4 script, while B0
has another dedicated script.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:57:17 +0000 (15:57 +0800)]
misc: ocotp: Update OCOTP driver for iMX8MQ B2
i.MX8MQ B2 also has fixed value in OCOTP_READ_FUSE_DATA register,
so it does not support "fuse sense" command like B1.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:57:16 +0000 (15:57 +0800)]
iMX8MQ: Recognize the B2 revision
i.MX8MQ B2 is using same value in OCOTP_READ_FUSE_DATA like B1, so
we have to check the ROM verision to distinguish the revision.
As we have checked the B1 rev for sticky bits work around in
secure boot. So it won't apply on B2.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:57:15 +0000 (15:57 +0800)]
arch: mach-imx: imx8m: fix unique_id read error for imx8mp
The value of Unique ID in uboot and kernel is different for iMX8MP:
serial#=
02e1444a0002aaff
root@imx8mpevk:/sys/devices/soc0# cat soc_uid
D699300002E1444A
The reason is that Fuse Addresses of Unique ID of iMX8MP are 0x420 and
0x430.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:57:14 +0000 (15:57 +0800)]
imx8m: ddr: Disable CA VREF Training for LPDDR4
Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
but not set in 1D. According to PHY training application node,
to enable the feature both 1D and 2D need set this field to 1,
otherwise the training result will be incorrect.
The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
MR12 value from message block (FSP structure). So update the LPDDR4
scripts of all mscale to clear CATrainOpt[0].
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:57:13 +0000 (15:57 +0800)]
imx8m: soc: update fuse path
Update fuse path to disable modules correctly.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:57:12 +0000 (15:57 +0800)]
imx8m: Update thermal and PMU kernel nodes for dual/single cores
For dual core and single core iMX8M parts, the thermal node and PMU node
in kernel DTB also needs update to remove the refers to deleted core nodes.
Otherwise both driver will fail to work.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:57:11 +0000 (15:57 +0800)]
imx8mn: Add support for 11x11 UltraLite part number
There are 3 part numbers for 11x11 i.MX8MNano with different core number
configuration: UltraLite Quad/Dual/Solo
Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So
checking the MIPI DSI disable fuse to recognize these parts.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:57:09 +0000 (15:57 +0800)]
imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK
Add dedicated defconfigs for iMX8MN low drive mode which set the VDD_SOC
and VDD_DRAM to 0.8v, DDR at 1600MTS (800Mhz clock) and GPU at 200Mhz.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:57:08 +0000 (15:57 +0800)]
imx8mn: Add LPDDR4 EVK board support
Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and
PCA9450B PMIC.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:57:07 +0000 (15:57 +0800)]
imx8mn_evk: drop duplicated code
uart clk has been enabled, no need enable again.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:57:06 +0000 (15:57 +0800)]
power: pca9450: add a new parameter for power_pca9450_init
Currently PCA9450 might have address 0x25 or 0x35, so let user
choose the address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Jacky Bai [Fri, 19 Mar 2021 07:57:05 +0000 (15:57 +0800)]
imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk
On i.MX8MN, we can only support DLL-ON mode only, so update the timing
to support 2400mts & 1066mts setpoint.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:57:04 +0000 (15:57 +0800)]
imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage
There is a frequency/timing limitation for SOC and ARM, if SOC is OD
voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have
timing risk from SOC to ARM.
Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will
increase bus clocks to OD frequency before it increases ARM voltage.
So to conform to the limitation, we'd better increases VDD_ARM to OD
voltage in SPL.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:57:03 +0000 (15:57 +0800)]
imx8mp_evk: spl: clean up including headers
Clean up the including headers
Signed-off-by: Peng Fan <peng.fan@nxp.com>
haidong.zheng [Fri, 19 Mar 2021 07:57:02 +0000 (15:57 +0800)]
imx8mp: refine power on imx8mp board
VDD SOC normal run changed to 0.85V
LPDDR4 freq0 change from 4000MTS to 2400MTS
Signed-off-by: haidong.zheng <haidong.zheng@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:57:01 +0000 (15:57 +0800)]
imx8mp_evk: Update LPDDR4 refresh time
Use more safer refresh time value for 6GB LPDDR4 on this EVK board.
Update the parameters for every frequency point.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:57:00 +0000 (15:57 +0800)]
imx8mp_evk: Update LPDDR4 timing for new FW 202006
After switching to new LPDDR4 firmware 202006 version, have to
update the LPDDR4 timing accordingly from RPA tool.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Sherry Sun <sherry.sun@nxp.com>
Tested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sherry Sun [Fri, 19 Mar 2021 07:56:59 +0000 (15:56 +0800)]
imx8mp: ddr: Add inline ECC feature support
Add inline ECC support for lpddr4 on imx8mp-evk. And add a config which
can enable/disable inline ECC feature for lpddr4 on imx8mp-evk board.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:56:58 +0000 (15:56 +0800)]
imx8mp_evk: add/cleanup variable for distro
Add fdt_addr_r fdtfile which used by distro boot
Clean up environment
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:56:57 +0000 (15:56 +0800)]
imx8mm_evk: add/cleanup variable for distro
Add fdt_addr_r fdtfile which used by distro boot
Clean up environment
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:56:56 +0000 (15:56 +0800)]
imx8mm/p: remove boot.cmd
These files should not be in U-Boot repo
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:56:55 +0000 (15:56 +0800)]
imx8mm_evk: Switch to new imx8mm evk board
Update PMIC to use PCA9540, the legacy board not supported by NXP
Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li [Fri, 19 Mar 2021 07:56:54 +0000 (15:56 +0800)]
imx8mm_evk: Update to latest LPDDR4 script
Update LPDDR4 script to sync with v2020.04 u-boot
Signed-off-by: Ye Li <ye.li@nxp.com>
Peng Fan [Fri, 19 Mar 2021 07:56:53 +0000 (15:56 +0800)]
tools: imx image: fix write warning
Fix the warning by set the variable zero to uint64_t
"warning: ‘write’ reading 5 bytes from a region of size 4"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Wed, 7 Apr 2021 19:54:07 +0000 (15:54 -0400)]
Merge branch '2021-04-07-CI-improvements'
- Assorted Azure/GitLab improvements
- Move the Dockerfile used for making containers in CI in to this
repository.
Tom Rini [Mon, 15 Mar 2021 17:19:01 +0000 (13:19 -0400)]
tools: Integrate the Dockerfile used for CI
Integrate the Dockerfile from
https://source.denx.de/u-boot/gitlab-ci-runner.git as of
commit
bc6130d572f1 ("Dockerfile: Remove high UID/GID") and introduce a
short rST on how to build the container.
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Heinrich Schuchardt [Fri, 2 Apr 2021 09:42:01 +0000 (11:42 +0200)]
Azure/GitLab: bump OpenSBI version to 0.9
Version 0.9 of OpenSBI provides the system reset extension which allows us
to reset and power off boards without board specific code.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Wed, 7 Apr 2021 15:14:13 +0000 (11:14 -0400)]
Merge branch '2021-04-07-fs-updates'
- JFFS2 updates
Tom Rini [Fri, 26 Feb 2021 12:52:28 +0000 (07:52 -0500)]
pytest: Lower pygit2 requirement
The latest versions of pygit2 are not available in practically any
distribution at this time. Furthermore, we don't need the latest in
order to run all of our testsuites. Reduce this version requirement to
something older that meets our needs while still supporting running our
tests on older hosts (and so, test labs).
Reported-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 26 Feb 2021 12:52:27 +0000 (07:52 -0500)]
GitLab: Remove "tags" stanzas
Given the structure of our current GitLab tests, we don't make real use
of the tags. Furthermore, these tags prevent the automatic usage of the
default GitLab runners. Remove these tags.
Reported-by: Roger Meier <r.meier@siemens.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 15 Feb 2021 15:52:19 +0000 (10:52 -0500)]
Azure: Rework SH / Renesas job
Now that there is a single SuperH platform, rework the Azure job
slightly. Azure build time limits mean that we need to split the world
build up still. Make a single build job for the single Renesas SuperH
platform as well as all of the ARM platforms from Renesas.
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Wagner Popov dos Santos [Tue, 23 Feb 2021 03:49:00 +0000 (00:49 -0300)]
JFFS2: fix jffs2 summary datacrc status uninitialized
The function jffs2_1pass_read_inode() was discarding the summary
inodes and dirent because the value in datacrc flag wasn't
initialized in function jffs2_sum_process_sum_data().
This fix initializes the status of all summary records to indicate
that the CRC needs to be verified when they are loaded.
Before this fix, the behaviors produced by the undefined value of
datacrc was:
- Summary's registries were discarded when 'b->datacrc' is equal
as 'CRC_BAD'.
- Summary's registries were not checked when b->datacrc differs of
'CRC_BAD' and 'CRC_UNKNOWN'
So, almost all of the time the crc just isn't checked, and in some
cases the registries are discarded.
Signed-off-by: Wagner Popov dos Santos <wpopov@gmail.com>
Wagner Popov dos Santos [Tue, 23 Feb 2021 02:30:58 +0000 (23:30 -0300)]
JFFS2: fix the reading address over nand's limit
Fixes address violation in functions read_nand_cached() and
read_onenand_cached(). This happens because these functions
try to read a fixed amount
of data even when the offset+length
is above the nand's limit.
Signed-off-by: Wagner Popov dos Santos <wpopov@gmail.com>
Tom Rini [Wed, 7 Apr 2021 02:42:55 +0000 (22:42 -0400)]
Merge tag 'mmc-2021-4-6' of https://source.denx.de/u-boot/custodians/u-boot-mmc
Update hwpartition usage
Check bootbus's arguments
workaround for erratum A-011334 for fsl_esdhc driver
add pulse width detection workaround for fsl_esdhc driver
Use alias num before checking mmc index when creating device
Tom Rini [Tue, 6 Apr 2021 18:11:21 +0000 (14:11 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- XHCI fixes
Stefan Roese [Tue, 6 Apr 2021 10:10:18 +0000 (12:10 +0200)]
usb: xhci: Make debug output better readable and checkpatch clean
This change makes debugging a bit easier as the output is better
readable with the added space. The explicit le16_to_cpu() is not
needed in the output. Also this patch moves the strings into one line
to make the patch checkpatch clean.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Aaron Williams [Tue, 6 Apr 2021 10:10:17 +0000 (12:10 +0200)]
usb: xhci: Add missing xhci_readl()
Accessing the xHCI controller registers should be done via the
xhci_readl/writel functions. This patch adds this to a few missing
places.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Aaron Williams [Tue, 6 Apr 2021 10:10:16 +0000 (12:10 +0200)]
usb: hub: Fix usb_get_port_status() for big-endian platforms
Add missing endianness conversions to usb_get_port_status(). This
(amongst others) is necessary to enable the use of USB 3 hubs on
big-endian platforms like MIPS Octeon.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Tom Rini [Tue, 6 Apr 2021 12:37:28 +0000 (08:37 -0400)]
Merge tag 'u-boot-amlogic-
20210406' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- Add MMIO MDIO mux driver
- Add Amlogic G12A MDIO mux driver
- Add DM_MDIO support for designware ethernet driver
- Add Amlogic Meson8b and later designware ethernet glue driver
- Switch all amlogic boards to Amlogic designware ethernet glue driver
- Switch all amlogic boards to DM_MDIO when necessary
- Remove all static ethernet setup code
Tom Rini [Tue, 6 Apr 2021 12:37:06 +0000 (08:37 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Enhance WDT handling (starting / stopping) and introduce
CONFIG_WATCHDOG_AUTOSTART to allow disabling of autostart of
the WDT (Pali)
Tom Rini [Tue, 6 Apr 2021 12:36:49 +0000 (08:36 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flash
- Fix detection of 8-bit bus flash devices via address shift
Tom Rini [Tue, 6 Apr 2021 12:36:11 +0000 (08:36 -0400)]
Merge tag 'dm-pull-6apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm
ENOSYS clean-up
Minor dtoc improvements
Convert CONFIG_MISC_INIT_F to Kconfig
Allow unit tests to run on any board
pylibfdt build-rule fix
Aswath Govindraju [Thu, 25 Mar 2021 07:18:48 +0000 (12:48 +0530)]
mmc: mmc-uclass: Use dev_seq() to read aliases node's index
Use dev_seq() to read aliases node's index and pass it as device number
for creating bulk device.
Suggested-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Aswath Govindraju [Thu, 25 Mar 2021 07:18:47 +0000 (12:48 +0530)]
mmc: Check for device with a seq number equal to num before checking against index
First check if there is an alias for the device tree node defined with the
given num before checking against device index.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Michael Walle [Wed, 17 Mar 2021 14:01:38 +0000 (15:01 +0100)]
board: sl28: enable HS400 mode again
Now that it is working reliable on the LS1028A SoC, reenable support for
it.
Signed-off-by: Michael Walle <michael@walle.cc>
Michael Walle [Wed, 17 Mar 2021 14:01:37 +0000 (15:01 +0100)]
mmc: fsl_esdhc: add pulse width detection workaround
HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a
workaroung for the pulse width detection. Apply this workaround in
u-boot, too.
This will make HS400 mode work reliably on the LS1028A SoC.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Michael Walle [Wed, 17 Mar 2021 14:01:36 +0000 (15:01 +0100)]
mmc: fsl_esdhc: add workaround for erratum A-011334
LS1028A SoCs are restricted in what divider values are allowed for HS400
mode. This is basically a port from the corresponding linux driver.
Signed-off-by: Michael Walle <michael@walle.cc>
Jaehoon Chung [Fri, 26 Feb 2021 09:38:20 +0000 (18:38 +0900)]
cmd: mmc: check whether bootbus's arguments is valid or not
According to Specification, each bit have valid value.
But it doesn't check whether arguments is valid or not.
It has potential bug with arguments passed by wrong value.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung [Fri, 26 Feb 2021 07:07:18 +0000 (16:07 +0900)]
cmd: mmc: modify more readable about hwpartition usage
Modified more readable about hwpartition usage.
Because it's difficult to understand how to use its command.
The arguments didn't optional.
mmc hwpartition needs to pass <USER> <GP> <MODE> as arguments.
Description about each arguments what is required is the below:
USER - <user> <enh> <start> <cnt> <wrrel> <{on|off}>
GP - <{gp1|gp2|gp3|gp4}> <cnt> <enh> <wrrel> <{on|off}>
MODE - <{check|set|complete}>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Neil Armstrong [Thu, 25 Feb 2021 08:44:38 +0000 (09:44 +0100)]
arm: meson: remove static ethernet link setup
The static ethernet link type config code is no more needed because now handled by
the meson8b glue driver, delete it.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Thu, 25 Feb 2021 08:44:37 +0000 (09:44 +0100)]
arm: meson: remove static ethernet memory power domain enable
The ethernet memory power domain is handled by the meson-ee-pwrc driver,
delete the static code.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Thu, 25 Feb 2021 08:44:36 +0000 (09:44 +0100)]
net: designware: remove amlogic compatibles
These compatibles are now handled by the dwmac_meson8b glue driver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Thu, 25 Feb 2021 08:44:35 +0000 (09:44 +0100)]
configs: meson: use Designware glue driver for Amlogic Meson8b & later SoCs
Use the proper Synopsys DWMAC Meson8b glue to handle the ethernet link type.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Thu, 25 Feb 2021 08:44:34 +0000 (09:44 +0100)]
arm: meson: remove static MDIO mux handling
The static MDIO mux handling in mach-meson is no more needed, delete it.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Thu, 25 Feb 2021 08:44:33 +0000 (09:44 +0100)]
configs: update Amlogic Meson G12A, G12B & SM1 configs for MDIO MUX
Use DM_MDIO and the new G12A MDIO MUX driver for G12A, G12B & SM1 boards.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Thu, 25 Feb 2021 08:44:32 +0000 (09:44 +0100)]
configs: update Amlogic Meson GXL & GXM config for MDIO MUX
Use DM_MDIO and the new MMIOREG MDIO MUX driver for GXL & GXM board.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Wed, 24 Feb 2021 19:33:56 +0000 (20:33 +0100)]
net: designware: add Amlogic Meson8b & later glue driver
This adds a proper glue driver for the Designware DWMAC ethernet MAC IP
found in the Amlogic Meson8, GXBB, GXL, GXM, G12A, G12B & SM1 SoCs.
This is aimed to replace the static ethernet link setup found on the board
init code for the Amlogic SoC based boards.
Tested on a libretech-cc (S905x Internal RMII 10/100 PHY) and Khadas VIM3 (A113d
with external 10/100/1000 RGMII PHY) to cover the most extreme setups.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Wed, 24 Feb 2021 16:31:53 +0000 (17:31 +0100)]
net: add Amlogic Meson G12A MDIO MUX driver
The Amlogic G12A & compatible SoCs embeds a mux to either communicate with
the external PHY or the internal 10/100 PHY.
This adds support for this mux as a MDIO MUX device.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Neil Armstrong [Wed, 24 Feb 2021 14:02:39 +0000 (15:02 +0100)]
net: designware: add DM_MDIO support
Add support for DM_MDIO to connect to PHY and expose a MDIO device for the
internal MDIO bus in order to dynamically connect to MDIO PHYs with DT
with eventual MDIO muxes in between.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Neil Armstrong [Wed, 24 Feb 2021 14:02:23 +0000 (15:02 +0100)]
net: add MMIO Register MDIO MUX driver
Add support for MMIO register MDIO muxes based on the Linux mdio-mux-mmioreg driver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Pali Rohár [Tue, 9 Mar 2021 13:26:57 +0000 (14:26 +0100)]
arm: mvebu: Espressobin: Enable watchdog support but do not start it
Espressobin had disabled watchdog support (CONFIG_WDT) because older stable
Linux kernel versions (which are used by current stable OpenWRT and Debian
versions) do not have support for Armada 3700 watchdog driver. Therefore
they are not able to periodically kick watchdog so Espressobin enter into
boot loop.
This change enable CONFIG_WDT, CONFIG_WDT_ARMADA_37XX and CONFIG_CMD_WDT
options which add support for U-Boot 'wdt' command. And unset new
CONFIG_WATCHDOG_AUTOSTART option which cause that watchdog is not
automatically started by U-Boot during init phase, like when CONFIG_WDT
option is not set at all.
So with this change, U-Boot on Espressobin would have working 'wdt' command
which can be used from boot scripts (e.g. for enabling watchdog prior new
Linux booting kernel). But default behavior of watchdog status stays
unchanged, U-Boot does not start watchdog on Espressobin during its init
phase.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Tue, 9 Mar 2021 13:26:56 +0000 (14:26 +0100)]
watchdog: Allow to use CONFIG_WDT without starting watchdog
In some cases it is useful to compile support for U-Boot command 'wdt'
without starting HW watchdog in early U-Boot phase. For example when the
user want to start the watchdog only on demand by some boot script.
This change adds a new compile option WATCHDOG_AUTOSTART to control whether
U-Boot should automatically start the watchdog during init phase or not.
This option is enabled by default as it was the default behavior prior
introducing this new change. When compiling U-Boot users can decide to turn
this option off.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Tue, 9 Mar 2021 13:26:55 +0000 (14:26 +0100)]
watchdog: Show error message when initr_watchdog() cannot start watchdog
Function wdt_start() may fail. So in initr_watchdog() function check return
value of wdt_start() call and print error message when watchdog starting
failed.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Tue, 9 Mar 2021 13:26:54 +0000 (14:26 +0100)]
watchdog: Set/unset GD_FLG_WDT_READY flag in wdt_start()/wdt_stop()
Watchdog is ready after successful call of ops->start() callback in
wdt_start() function. And is stopped after successful call of ops->stop()
callback in wdt_stop function.
So move setting of GD_FLG_WDT_READY flag from initr_watchdog() function to
wdt_start() and ensure that GD_FLG_WDT_READY flag is unset in wdt_stop()
function.
This change ensures that GD_FLG_WDT_READY flag is set only when watchdog is
running. And ensures that flag is also also when watchdog was started not
only by initr_watchdog() call (e.g. by U-Boot 'wdt' command).
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Jagannadha Sutradharudu Teki [Fri, 26 Feb 2021 07:51:49 +0000 (08:51 +0100)]
cfi_flash: Fix detection of 8-bit bus flash devices via address shift
We had a problem detecting 8/16bit flash devices connected only via
8bits to the SoC for quite a while. Commit
239cb9d9
[mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support] finally
fixed this 8-bit bus support. But also broke some other boards using
this cfi driver. So this patch had to be reverted.
I spotted a different, simpler approach for this 8-bit bus support
on the barebox mailing list posted by
Oleksij Rempel <bug-track@fisher-privat.net>:
http://www.spinics.net/lists/u-boot-v2/msg14687.html
Here the commit text:
"
Many cfi chips support 16 and 8 bit modes. Most important
difference is use of so called "Q15/A-1" pin. In 16bit mode this
pin is used for data IO. In 8bit mode, it is an address input
which add one more least significant bit (LSB). In this case
we should shift all adresses by one:
For example 0xaa << 1 = 0x154
"
This patch now is a port of this barebox patch to U-Boot.
Along with the change w.r.t from barebox,
Some flash chips can support multiple bus widths, override the
interface width and limit it to the port width.
Tested on 16-bit Spansion flash on sequoia.
Tested 8-bit flashes like 256M29EW, 512M29EW.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: York Sun <york.sun@nxp.com>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Simon Glass [Wed, 24 Mar 2021 21:44:33 +0000 (10:44 +1300)]
test: Allow tests to run on any board
Due to a recent change, tests are limited to running on sandbox only.
Correct this so that any architecture can run them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Sean Anderson <seanga2@gmail.com>
Fixes: c79705ea938 ("test: Move dm_test_init() into test-main.c")
Tested-by: Sean Anderson <seanga2@gmail.com>
Heinrich Schuchardt [Sun, 28 Mar 2021 09:05:00 +0000 (11:05 +0200)]
sandbox: document parameters of os_realloc()
Avoid 'make htmldocs' build warnings:
./include/os.h:139: warning:
Function parameter or member 'ptr' not described in 'os_realloc'
./include/os.h:139: warning:
Function parameter or member 'length' not described in 'os_realloc'
Fixes: 14e46dfb176b ("sandbox: Add os_realloc()")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 26 Mar 2021 03:17:30 +0000 (16:17 +1300)]
Convert CONFIG_MISC_INIT_F to Kconfig
This converts the following to Kconfig:
CONFIG_MISC_INIT_F
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Simon Glass [Fri, 26 Mar 2021 03:17:29 +0000 (16:17 +1300)]
moveconfig: Handle binary files cleanly
Some files are not actually source code and thus can produce unicode
errors. Report this and continue.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 26 Mar 2021 03:17:28 +0000 (16:17 +1300)]
log: Fix up debug_cond() when LOG is enabled
At present debug() statements can cause debuf output to appear when LOG is
enabled but DEBUG is not. This is not intended and it seems that the
condition is wrong.
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 26 Mar 2021 03:17:27 +0000 (16:17 +1300)]
dtoc: Improve handling of reg properties
This existing code assumes that a reg property is larger than one cell,
but this is not always the case. Fix this assumption.
Also if a node's parent is missing the #address-cells and #size-cells
properties we use 2 as a default for each. But this should not happen in
practice. More likely the properties were removed for SPL due to there
being no 'u-boot,dm-pre-reloc' property, or similar. Add a warning for
this as the failure can be very confusing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 26 Mar 2021 03:17:26 +0000 (16:17 +1300)]
dtoc: Adjust detection of 64-bit properties
At present an empty size is considered to be a 64-bit value. This does not
seem useful and wastes space. Limit the 64-bit detection to where one or
both of the addr/size is two cells or more.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 26 Mar 2021 03:17:25 +0000 (16:17 +1300)]
dtoc: Show driver warnings once at the end
At present warnings are shown as soon as they are discovered in the
source scannner. But the function that detects them may be called multiple
times.
Collect all the warnings and show them at the end.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 26 Mar 2021 01:39:39 +0000 (14:39 +1300)]
buildman: Add an encoding to the out-env file
The environment may contain some unicode characters. At least that is what
seemed to happen on one commit:
Building current source for 1 boards (0 threads, 64 jobs per thread)
0 0 0 /1 -1 (starting)
Traceback (most recent call last):
File ".../tools/buildman/buildman", line 64, in <module>
ret_code = control.DoBuildman(options, args)
File "tools/buildman/control.py", line 372, in DoBuildman
options.keep_outputs, options.verbose)
File ".../tools/buildman/builder.py", line 1704, in BuildBoards
results = self._single_builder.RunJob(job)
File ".../tools/buildman/builderthread.py", line 526, in RunJob
self._WriteResult(result, job.keep_outputs, job.work_in_output)
File ".../tools//buildman/builderthread.py", line 349, in _WriteResult
print('%s="%s"' % (var, env[var]), file=fd)
UnicodeEncodeError: 'ascii' codec can't encode characters in position
311-312: ordinal not in range(128)
The problem defies repetition with any change at all to buildman. But
let's set an encoding in any case.
Signed-off-by: Simon Glass <sjg@chromium.org>