Fangrui Song [Wed, 30 Dec 2020 18:32:34 +0000 (10:32 -0800)]
[PowerPC][test] Add explicit dso_local to definitions in ELF static relocation model tests
TargetMachine::shouldAssumeDSOLocal currently implies dso_local for such definitions.
Adding explicit dso_local makes these tests align with the clang -fpic behavior
and allow the removal of the TargetMachine::shouldAssumeDSOLocal special case.
Rewrite preemption.ll to dsolocal-static.ll and dsolocal-pic.ll, and add
"PIC Level" metadata.
Max Moroz [Wed, 30 Dec 2020 18:10:23 +0000 (10:10 -0800)]
[compiler-rt] FuzzedDataProvider: Add PickValueInArray for std::array
This makes `PickValueInArray` work for `std::array<T, s>` (C++11). I've also tested the C++17 `std::array` (with compiler-deduced template parameters)
```
Author:
MarcoFalke <falke.marco@gmail.com>
```
Reviewed By: Dor1s
Differential Revision: https://reviews.llvm.org/D93412
Andrew Litteken [Wed, 16 Sep 2020 03:02:18 +0000 (22:02 -0500)]
[IROutliner] Adding option to enable outlining from linkonceodr functions
There are functions that the linker is able to automatically
deduplicate, we do not outline from these functions by default. This
allows for outlining from those functions.
Tests:
llvm/test/Transforms/IROutliner/outlining-odr.ll
Reviewers: jroelofs, paquette
Differential Revision: https://reviews.llvm.org/D87309
Fangrui Song [Wed, 30 Dec 2020 17:30:58 +0000 (09:30 -0800)]
[CMake][tsan] Remove --sysroot=.
rL254966 added `--sysroot=.` to prevent accidental including system headers.
It caused hassle to FreeBSD (D17383)/NetBSD. The next problem is that
we want to include `features.h` (usually `/usr/include/features.h`) to detect `__GLIBC__`.
At this point it seems that `--sysroot=.` adds lots of inconvenience so we disable it for now.
If there is a better way preventing accidental system header inclusion we can consider it again.
Reviewed By: #sanitizers, vitalybuka
Differential Revision: https://reviews.llvm.org/D93921
Fangrui Song [Wed, 30 Dec 2020 17:16:26 +0000 (09:16 -0800)]
[ELF] Drop '>>> defined in ' for locations of linker synthesized symbols
Reviewed By: grimar
Differential Revision: https://reviews.llvm.org/D93925
Nicolas Vasilache [Wed, 30 Dec 2020 16:42:21 +0000 (16:42 +0000)]
[mlir] Fix indexing of first offset operand in ops that implement OffsetSizeAndStrideOpInterface
OffsetSizeAndStrideOpInterface ops may have a varying number of operands before the first
offset operand. This revision adds a method that such ops much implement to properly specify
the position of the first offset operand.
Differential Revision: https://reviews.llvm.org/D93947
Nicolas Vasilache [Wed, 30 Dec 2020 16:33:32 +0000 (16:33 +0000)]
[mlir] NFC - Fix SubViewOp printing
Avoid casting the source operand type allows better debugging when conversion patterns
fail to produce a proper MemRefType.
Sanjay Patel [Wed, 30 Dec 2020 16:27:23 +0000 (11:27 -0500)]
[SLP] add fadd reduction test to show broken FMF propagation; NFC
Bogdan Graur [Wed, 30 Dec 2020 14:56:29 +0000 (06:56 -0800)]
Fixes warning 'enumeration value not handled in switch'.
This was introduced in commit:
981a0bd85811fe49379fdbef35528e2c2f3511a3.
Differential Revision: https://reviews.llvm.org/D93944
Sanjay Patel [Wed, 30 Dec 2020 14:11:10 +0000 (09:11 -0500)]
[IR] remove 'NoNan' param when creating FP reductions
This is no-functional-change-intended (AFAIK, we can't
isolate this difference in a regression test).
That's because the callers should be setting the IRBuilder's
FMF field when creating the reduction and/or setting those
flags after creating. It doesn't make sense to override this
one flag alone.
This is part of a multi-step process to clean up the FMF
setting/propagation. See PR35538 for an example.
Juneyoung Lee [Wed, 30 Dec 2020 14:49:09 +0000 (23:49 +0900)]
Remove functions from *-inseltpoison.ll tests if unnecessary
X-inseltpoison.ll is a copy of X.ll with insertelement/shufflevector's
placeholder replaced with poison.
This commit removes a few redundant functions which do not contain any
shufflevector/insertelement.
Wang, Pengfei [Wed, 30 Dec 2020 14:22:13 +0000 (22:22 +0800)]
[X86][AMX] Fix compilation warning introduced by
981a0bd8.
Juneyoung Lee [Wed, 30 Dec 2020 14:05:07 +0000 (23:05 +0900)]
clang-format, address warnings
Juneyoung Lee [Tue, 29 Dec 2020 22:28:17 +0000 (07:28 +0900)]
Use unary CreateShuffleVector if possible
As mentioned in D93793, there are quite a few places where unary `IRBuilder::CreateShuffleVector(X, Mask)` can be used
instead of `IRBuilder::CreateShuffleVector(X, Undef, Mask)`.
Let's update them.
Actually, it would have been more natural if the patches were made in this order:
(1) let them use unary CreateShuffleVector first
(2) update IRBuilder::CreateShuffleVector to use poison as a placeholder value (D93793)
The order is swapped, but in terms of correctness it is still fine.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D93923
Alexander Belyaev [Wed, 30 Dec 2020 13:35:25 +0000 (14:35 +0100)]
[mlir] Fix a typo MemRefType -> UnrankedMemRefType
Marek Kurdej [Wed, 30 Dec 2020 13:24:02 +0000 (14:24 +0100)]
[libc++] [docs] Mark contract-related papers as removed from C++20.
Juneyoung Lee [Wed, 30 Dec 2020 13:13:10 +0000 (22:13 +0900)]
[SimplifyCFG] Add tests for select form and/or for creating select from icmps
Juneyoung Lee [Wed, 30 Dec 2020 07:11:54 +0000 (16:11 +0900)]
[ConstraintElimination] Add support for select form of and/or
This patch adds support for select form of and/or.
Currently there is an ongoing effort for moving towards using `select a, b, false` instead of `and i1 a, b` and
`select a, true, b` instead of `or i1 a, b` as well.
D93065 has links to relevant changes.
Alive2 proof: (undef input was disabled due to timeout :( )
- and: https://alive2.llvm.org/ce/z/AgvFbQ
- or: https://alive2.llvm.org/ce/z/KjLJyb
Differential Revision: https://reviews.llvm.org/D93935
zhanghb97 [Mon, 14 Dec 2020 10:43:05 +0000 (18:43 +0800)]
[mlir][Python] Initial Affine Map Python Bindings.
- Add `PyAffineMap` to wrap around `MlirAffineMap`.
- Add `mlirPythonAffineMapToCapsule` and `mlirPythonCapsuleToAffineMap` to interoperate with python capsule.
- Add and test some simple bindings of `PyAffineMap`.
Differential Revision: https://reviews.llvm.org/D93200
Luo, Yuanke [Wed, 30 Dec 2020 07:22:19 +0000 (15:22 +0800)]
[X86] Refactor AMX test case, remove unnecessary code.
Differential Revision: https://reviews.llvm.org/D93792
Fangrui Song [Wed, 30 Dec 2020 07:37:55 +0000 (23:37 -0800)]
Move -fno-semantic-interposition dso_local logic from TargetMachine to Clang CodeGenModule
This simplifies TargetMachine::shouldAssumeDSOLocal and and gives frontend the
decision to use dso_local. For LLVM synthesized functions/globals, they may lose
inferred dso_local but such optimizations are probably not very useful.
Note: the hasComdat() condition in canBenefitFromLocalAlias (D77429) may be dead now.
(llvm/CodeGen/X86/semantic-interposition-comdat.ll)
(Investigate whether we need test coverage when Fuchsia C++ ABI is clearer)
Andrew Litteken [Mon, 24 Aug 2020 09:25:54 +0000 (04:25 -0500)]
[IROutliner] Adding support for swift errors in the IROutliner
Since some values can be swift errors, we need to make sure that we
correctly propagate the parameter attributes.
Tests found at:
llvm/test/Transforms/IROutliner/outlining-swift-error.ll
Reviewers: jroelofs, paquette
Recommit of:
71867ed5e6606a93f0c1413f205afe3bb16317fe
Differential Revision: https://reviews.llvm.org/D87742
Andrew Litteken [Wed, 30 Dec 2020 07:15:48 +0000 (01:15 -0600)]
Revert "[IROutliner] Adding support for swift errors"
This reverts commit
71867ed5e6606a93f0c1413f205afe3bb16317fe.
Reverting for lack of commit messages.
Andrew Litteken [Mon, 24 Aug 2020 09:25:54 +0000 (04:25 -0500)]
[IROutliner] Adding support for swift errors
Juneyoung Lee [Wed, 30 Dec 2020 07:05:19 +0000 (16:05 +0900)]
[ConstraintElimination] Add tests for select form and/or (NFC)
Siva Chandra Reddy [Mon, 21 Dec 2020 17:16:41 +0000 (09:16 -0800)]
[libc] Add implementations of rounding functions which depend rounding mode.
Namely, implementations for rint, rintf, rintl, lrint, lrintf, lrintl,
llrint, llrintf and llrintl have been added.
Reviewed By: lntue
Differential Revision: https://reviews.llvm.org/D93889
Luo, Yuanke [Fri, 20 Nov 2020 07:19:34 +0000 (15:19 +0800)]
[X86] Add x86_amx type for intel AMX.
The x86_amx is used for AMX intrisics. <256 x i32> is bitcast to x86_amx when
it is used by AMX intrinsics, and x86_amx is bitcast to <256 x i32> when it
is used by load/store instruction. So amx intrinsics only operate on type x86_amx.
It can help to separate amx intrinsics from llvm IR instructions (+-*/).
Thank Craig for the idea. This patch depend on https://reviews.llvm.org/D87981.
Differential Revision: https://reviews.llvm.org/D91927
Fangrui Song [Wed, 30 Dec 2020 05:26:30 +0000 (21:26 -0800)]
[X86][test] Improve global address offset folding tests
Craig Topper [Wed, 30 Dec 2020 05:04:19 +0000 (21:04 -0800)]
[Verifier] Remove declaration of method that was removed 8.5 years ago. NFC
Haowei Wu [Wed, 9 Dec 2020 01:23:53 +0000 (17:23 -0800)]
[llvm-elfabi] Add flag to preserve timestamp when output is the same
This change adds '--write-if-changed' flag to llvm-elfabi tool. When
enabled, llvm-elfabi will not overwrite the existing file if the
content of the file will not be changed, which preserves the
timestamp.
Differential Revision: https://reviews.llvm.org/D92902
Stella Laurenzo [Wed, 30 Dec 2020 02:06:24 +0000 (18:06 -0800)]
[mlir][python] Install generated dialect sources.
Differential Revision: https://reviews.llvm.org/D93928
Kazu Hirata [Wed, 30 Dec 2020 03:23:24 +0000 (19:23 -0800)]
[Analysis, IR] Use *Map::lookup (NFC)
Kazu Hirata [Wed, 30 Dec 2020 03:23:22 +0000 (19:23 -0800)]
[Transforms/Utils] Construct SmallVector with iterator ranges (NFC)
Kazu Hirata [Wed, 30 Dec 2020 03:23:21 +0000 (19:23 -0800)]
[Analysis] Use llvm::append_range (NFC)
ShihPo Hung [Fri, 25 Dec 2020 02:56:24 +0000 (18:56 -0800)]
[RISCV] Add intrinsics for vcompress instruction
This patch defines vcompress intrinsics and lower to V instructions.
We work with @rogfer01 from BSC to come out this patch.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>
Differential revision: https://reviews.llvm.org/D93809
Kai Luo [Wed, 30 Dec 2020 02:23:05 +0000 (02:23 +0000)]
[PowerPC] Add mir test to show effect of `optimizeCompareInstr` when `equalityOnly` is true. NFC.
Kai Luo [Tue, 29 Dec 2020 12:11:55 +0000 (12:11 +0000)]
[PowerPC] Remaining KnownBits should be constant when performing non-sign comparison
In `PPCTargetLowering::DAGCombineTruncBoolExt`, when checking if it's correct to perform the transformation for non-sign comparison, as the comment says
```
// This is neither a signed nor an unsigned comparison, just make sure
// that the high bits are equal.
```
Origin check
```
if (Op1Known.Zero != Op2Known.Zero || Op1Known.One != Op2Known.One)
return SDValue();
```
is not strong enough. For example,
```
Op1Known = 111x000x;
Op2Known = 111x000x;
```
Bit 4, besides bit 0, is still unknown and affects the final result.
This patch fixes https://bugs.llvm.org/show_bug.cgi?id=48388.
Reviewed By: nemanjai, #powerpc
Differential Revision: https://reviews.llvm.org/D93092
Lang Hames [Tue, 29 Dec 2020 09:27:41 +0000 (20:27 +1100)]
[ORC] Move Orc RPC code into Shared, rename some RPC types.
Moves all headers from Orc/RPC to Orc/Shared, and from the llvm::orc::rpc
namespace into llvm::orc::shared. Also renames RPCTypeName to
SerializationTypeName and Function to RPCFunction.
In addition to being a more reasonable home for this code, this will make it
easier for the upcoming Orc runtime to re-use the Serialization system for
creating and parsing wrapper-function binary blobs.
Stella Laurenzo [Wed, 30 Dec 2020 01:43:04 +0000 (17:43 -0800)]
[mlir][python] Aggressively avoid name collisions in generated python ODS code.
* When porting npcomp to use these bindings, I ran into enough patterns of collisions that I decided to be somewhat draconian about not polluting the namespace.
* With these changes all of the npcomp dialects generate and pass what tests we have.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D93920
Vitaly Buka [Wed, 30 Dec 2020 01:27:53 +0000 (17:27 -0800)]
[NFC][lsan] Extract PrintResults function
Vitaly Buka [Wed, 30 Dec 2020 01:18:39 +0000 (17:18 -0800)]
[lsan] Parse suppressions just before leak reporting
Without leaks suppressions are not needed.
Haowei Wu [Wed, 30 Dec 2020 01:26:22 +0000 (17:26 -0800)]
Revert "[llvm-elfabi] Add flag to preserve timestamp when output is the same"
This reverts commit
fddb41744958d21635a60622cfb4067122810bcc. which
causes test failures on Mac builders.
Zakk Chen [Mon, 28 Dec 2020 16:44:38 +0000 (08:44 -0800)]
[RISCV] Define vsext/vzext intrinsics.
Define vsext/vzext intrinsics.and lower to V instructions.
Define new fraction register class fields in LMULInfo and a
NoReg to present invalid LMUL register classes.
Authored-by: ShihPo Hung <shihpo.hung@sifive.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D93893
LLVM GN Syncbot [Wed, 30 Dec 2020 00:40:53 +0000 (00:40 +0000)]
[gn build] Port
480936e741d
Yuanfang Chen [Wed, 30 Dec 2020 00:30:16 +0000 (16:30 -0800)]
Reland "[NewPM][CodeGen] Introduce CodeGenPassBuilder to help build codegen pipeline" (again)
This reverts commit
16c8f6e91344ec9840d6aa9ec6b8d0c87a104ca3 with fix.
-Wswitch catched an unhandled enum value due to recent commits in
TargetPassConfig.cpp.
LLVM GN Syncbot [Wed, 30 Dec 2020 00:29:58 +0000 (00:29 +0000)]
[gn build] Port
16c8f6e9134
Yuanfang Chen [Wed, 30 Dec 2020 00:29:07 +0000 (16:29 -0800)]
Revert "Reland "[NewPM][CodeGen] Introduce CodeGenPassBuilder to help build codegen pipeline""
This reverts commit
21314940c4856e0cb81b664fd2d2117d1b7dc3e3.
Build failure in some bots.
Mehdi Amini [Wed, 30 Dec 2020 00:19:31 +0000 (00:19 +0000)]
Fix DRR pattern when attributes and operands are interleaved and a dag subtree appears in the rewrite
This fixes an incorrect fatal error in TableGen. This code probably comes
from before attributes were allowed to interleave with operands in ODS.
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D93915
Chris Morin [Tue, 29 Dec 2020 22:04:55 +0000 (22:04 +0000)]
[MLIR] Make ComplexType buildable if its element type is buildable
If a ComplexType's element type is buildable, then that ComplexType should be
buildable. This is accomplished by the introduction of a new ODS class called
`SameBuildabilityAs`. This can be used by other types that are conditionally
buildable.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D93892
LLVM GN Syncbot [Tue, 29 Dec 2020 23:18:48 +0000 (23:18 +0000)]
[gn build] Port
21314940c48
Yuanfang Chen [Tue, 29 Dec 2020 01:48:17 +0000 (17:48 -0800)]
Reland "[NewPM][CodeGen] Introduce CodeGenPassBuilder to help build codegen pipeline"
This reverts commit
94427af60c66ffea655a3084825c6c3a9deec1ad (relands
4646de5d75cfce3da4ddeffb6eb8e66e38238800 with fix).
Use "return std::move(AsmStreamer);" instead of "return AsmStreamer;" in
LVMTargetMachine::createMCStreamer. Unlike Clang, GCC seems having trouble
inserting a implicit lvalue->rvalue conversion.
Haowei Wu [Wed, 9 Dec 2020 01:23:53 +0000 (17:23 -0800)]
[llvm-elfabi] Add flag to preserve timestamp when output is the same
This change adds '--write-if-changed' flag to llvm-elfabi tool. When
enabled, llvm-elfabi will not overwrite the existing file if the
content of the file will not be changed, which preserves the
timestamp.
Differential Revision: https://reviews.llvm.org/D92902
Peter Collingbourne [Thu, 17 Dec 2020 23:34:49 +0000 (15:34 -0800)]
CrashReason: Add MTE tag check faults to the list of crash reasons.
As of Linux 5.10, the kernel may report either of the two following
crash reasons:
- SEGV_MTEAERR: async MTE tag check fault
- SEGV_MTESERR: sync MTE tag check fault
Teach LLDB about them.
Differential Revision: https://reviews.llvm.org/D93495
Jacques Pienaar [Tue, 29 Dec 2020 22:20:19 +0000 (14:20 -0800)]
[mlir] Add error message when failing to add pass
Ran into failure without any error message previously here.
Differential Revision: https://reviews.llvm.org/D93910
Siddharth Krishna [Tue, 29 Dec 2020 22:14:08 +0000 (14:14 -0800)]
[mlir][Python] Add an Operation.name property
Reviewed By: stellaraccident, mehdi_amini
Differential Revision: https://reviews.llvm.org/D93474
Stella Laurenzo [Tue, 29 Dec 2020 22:10:31 +0000 (14:10 -0800)]
[mlir][python] Add Operation.verify().
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D93913
Vitaly Buka [Tue, 29 Dec 2020 02:58:11 +0000 (18:58 -0800)]
[NFC][lsan] Add nested leak in test
Vitaly Buka [Tue, 29 Dec 2020 01:45:54 +0000 (17:45 -0800)]
[NFC][sanitizer] Add SortAndDedup function
Vitaly Buka [Tue, 29 Dec 2020 01:16:49 +0000 (17:16 -0800)]
[NFC][sanitizer] Simplify InternalLowerBound
Vitaly Buka [Tue, 29 Dec 2020 00:25:45 +0000 (16:25 -0800)]
[tsan] Remove stdlib.h from dd_interceptors.cpp
This fixes "realpath already defined" error.
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D93877
Jacques Pienaar [Tue, 29 Dec 2020 21:59:53 +0000 (13:59 -0800)]
[mlir] Skip empty op-pipelines in inliner textual opt parsing
Avoids failing on cases like
inline{default-pipeline=canonicalize max-iterations=4 op-pipelines=},
as produced by crash reproducer.
Andrew Litteken [Mon, 24 Aug 2020 09:21:38 +0000 (04:21 -0500)]
[IROutliner] Adding OptRemarks to the IROutliner Pass
This prints OptRemarks at each location where a decision is made to not
outline, or to outline a specific section for the IROutliner pass.
Test:
llvm/test/Transforms/IROutliner/opt-remarks.ll
Reviewers: jroelofs, paquette
Differential Revision: https://reviews.llvm.org/D87300
Roman Lebedev [Tue, 29 Dec 2020 21:41:57 +0000 (00:41 +0300)]
[SimplifyCFG] Teach SimplifyTerminatorOnSelect() to preserve DomTree
Roman Lebedev [Tue, 29 Dec 2020 21:21:32 +0000 (00:21 +0300)]
[SimplifyCFG] Teach SimplifyCondBranchToCondBranch() to preserve DomTree
Roman Lebedev [Tue, 29 Dec 2020 20:45:54 +0000 (23:45 +0300)]
[SimplifyCFG] Teach mergeConditionalStoreToAddress() to preserve DomTree
Roman Lebedev [Tue, 29 Dec 2020 19:58:28 +0000 (22:58 +0300)]
[SimplifyCFG] Teach FoldCondBranchOnPHI() to preserve DomTree
Roman Lebedev [Tue, 29 Dec 2020 19:32:45 +0000 (22:32 +0300)]
[SimplifyCFG] Teach SinkCommonCodeFromPredecessors() to preserve DomTree
Roman Lebedev [Tue, 29 Dec 2020 18:31:58 +0000 (21:31 +0300)]
[SimplifyCFG] Teach HoistThenElseCodeToIf() to preserve DomTree
Roman Lebedev [Tue, 29 Dec 2020 17:31:37 +0000 (20:31 +0300)]
[SimplifyCFG] Teach SimplifyEqualityComparisonWithOnlyPredecessor() to preserve DomTree, part 2
Roman Lebedev [Tue, 29 Dec 2020 16:20:27 +0000 (19:20 +0300)]
[SimplifyCFG] Teach SimplifyEqualityComparisonWithOnlyPredecessor() to preserve DomTree, part 1
James Y Knight [Tue, 29 Dec 2020 21:17:14 +0000 (16:17 -0500)]
Copy demangle changes from libcxxabi to llvm with cp_to_llvm.sh.
This includes changes from these commits:
5641b1dfddff847f7f3edc484537f9314c283225
8d313927539de66808e5bf3566fbd844aa78a916
Sanjay Patel [Tue, 29 Dec 2020 20:53:17 +0000 (15:53 -0500)]
[Utils] reduce code in createTargetReduction(); NFC
The switch duplicated the translation in getRecurrenceBinOp().
This code is still weird because it translates to the TTI
ReductionFlags for min/max, but then createSimpleTargetReduction()
converts that back to RecurrenceDescriptor::MinMaxRecurrenceKind.
Stella Laurenzo [Tue, 29 Dec 2020 20:07:57 +0000 (12:07 -0800)]
[mlir][python] Add FlatSymbolRef attribute.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D93909
Sanjay Patel [Tue, 29 Dec 2020 19:21:16 +0000 (14:21 -0500)]
[SLP] replace local reduction enum with RecurrenceKind; NFCI
I'm not sure if the SLP enum was created before the IVDescriptor
RecurrenceDescriptor / RecurrenceKind existed, but the code in
SLP is now redundant with that class, so it just makes things
more complicated to have both. We eventually call LoopUtils
createSimpleTargetReduction() to create reduction ops, so we
might as well standardize on those enum names.
There's still a question of whether we need to use TTI::ReductionFlags
vs. MinMaxRecurrenceKind, but that can be another clean-up step.
Another option would just be to flatten the enums in RecurrenceDescriptor
into a single enum. There isn't much benefit (smaller switches?) to
having a min/max subset.
Fraser Cormack [Mon, 28 Dec 2020 08:41:49 +0000 (08:41 +0000)]
[RISCV] Fill out basic integer RVV ISel patterns
This complements the existing RVV ISel patterns for arithmetic, bitwise
and shifts with the remaining operations in those categories: sub, and,
xor, sra.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D93852
Juneyoung Lee [Thu, 24 Dec 2020 00:33:58 +0000 (09:33 +0900)]
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder
This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D93793
Andrew Litteken [Mon, 14 Sep 2020 21:58:15 +0000 (16:58 -0500)]
[IROutliner] Adding a cost model, and debug option to turn the model off.
This adds a cost model that takes into account the total number of
machine instructions to be removed from each region, the number of
instructions added by adding a new function with a set of instructions,
and the instructions added by handling arguments.
Tests not adding flags:
llvm/test/Transforms/IROutliner/outlining-cost-model.ll
Reviewers: jroelofs, paquette
Differential Revision: https://reviews.llvm.org/D87299
Craig Topper [Tue, 29 Dec 2020 18:18:27 +0000 (10:18 -0800)]
[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source
If the destination is tied, then user has some control of the
register used for input. They would have the ability to control
the value of any tail elements. By using tail agnostic we take
this option away from them.
Its not clear that the intrinsics are defined such that this isn't
supposed to work. And undisturbed is a valid implementation for agnostic
so code wouldn't even fail to work on all systems if we always used
agnostic.
The vcompress intrinsic is defined to require tail undisturbed so
at minimum we need this for that instruction or need to redefine
the intrinsic.
I've made an exception here for vmv.s.x/fmv.s.f and reduction
instructions which only write to element 0 regardless of the tail
policy. This allows us to keep the agnostic policy on those which
should allow better redundant vsetvli removal.
An enhancement would be to check for undef input and keep the
agnostic policy, but we don't have good test coverage for that yet.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D93878
Arthur Eubanks [Mon, 28 Dec 2020 21:48:34 +0000 (13:48 -0800)]
[NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes
And add it to the AMDGPU opt pipeline.
This is a function pass instead of a module pass (like the legacy pass)
because it's getting added to a CGSCCPassManager, and you can't put a
module pass in a CGSCCPassManager.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D93885
Florian Hahn [Tue, 29 Dec 2020 15:27:18 +0000 (15:27 +0000)]
[MSSAUpdater] Skip renaming when inserting def in unreachable block.
This fixes a updater crash when moving memory defs between unreachable
blocks.
Fixes PR48616.
Craig Topper [Tue, 29 Dec 2020 17:59:57 +0000 (09:59 -0800)]
[RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m instructions
The spec for these instructions include this note. "The destination register
cannot overlap either the source register or the mask register ('v0') if the
instruction is masked." So we need earlyclobber to enforce this constraint.
I've regenerated the tests with update_llc_test_checks.py to show the
effects of the earlyclobber.
Reviewed By: khchen, frasercrmck
Differential Revision: https://reviews.llvm.org/D93867
Michael Stapelberg [Tue, 29 Dec 2020 17:26:57 +0000 (12:26 -0500)]
sanitizer: fix typo/spelling: Dissassemble → Disassemble
Differential Revision: https://reviews.llvm.org/D93902
Thomas Raoux [Tue, 29 Dec 2020 07:55:15 +0000 (23:55 -0800)]
[mlir][linalg] Add vectorization for linalg on tensor ops
Support vectorization of linalg ops using tensor inputs/outputs.
Differential Revision: https://reviews.llvm.org/D93890
Nicolai Hähnle [Wed, 9 Dec 2020 08:54:54 +0000 (09:54 +0100)]
RegionInfo: use a range-based for loop [NFCI]
Change-Id: I9985d72191a2b0680195032acf8a14ad2ba954ed
Differential Revision: https://reviews.llvm.org/D92932
Roman Lebedev [Tue, 29 Dec 2020 13:27:55 +0000 (16:27 +0300)]
[InstCombine] 'hoist xor-by-constant from xor-by-value': completely give up on constant exprs
As Mikael Holmén is noting in the post-commit review for the first fix
https://reviews.llvm.org/rGd4ccef38d0bb#967466
not hoisting constantexprs is not enough,
because if the xor originally was a constantexpr (i.e. X is a constantexpr).
`SimplifyAssociativeOrCommutative()` in `visitXor()` will immediately
undo this transform, thus again causing an infinite combine loop.
This transform has resulted in a surprising number of constantexpr failures.
Nemanja Ivanovic [Tue, 29 Dec 2020 12:32:45 +0000 (06:32 -0600)]
[PowerPC] Provide patterns for permuted scalar to vector for pre-P8
We will emit these permuted nodes on all VSX little endian subtargets
but don't have the patterns available to match them on subtargets
that don't have direct moves.
Fixes: https://bugs.llvm.org/show_bug.cgi?id=47916
Fraser Cormack [Tue, 29 Dec 2020 11:29:18 +0000 (11:29 +0000)]
[RISCV] Rewrite and simplify helper function. NFC.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D93851
Nemanja Ivanovic [Tue, 29 Dec 2020 04:51:51 +0000 (22:51 -0600)]
[PowerPC] Disable CTR loops containing operations on half-precision
On subtargets prior to Power9, conversions to/from half precision
are lowered to libcalls. This makes loops containing such operations
invalid candidates for HW loops.
Fixes: https://bugs.llvm.org/show_bug.cgi?id=48519
Mark Murray [Thu, 24 Dec 2020 10:15:12 +0000 (10:15 +0000)]
[ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM
This patch upstreams support for the Armv8-a Cortex-A78C
processor for AArch64 and ARM.
In detail:
Adding cortex-a78c as cpu option for aarch64 and arm targets in clang
Adding Cortex-A78C CPU name and ProcessorModel in llvm
Details of the CPU can be found here:
https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78c
Pavel Labath [Mon, 21 Dec 2020 21:20:58 +0000 (22:20 +0100)]
[lldb] Deduplicate some tests in TestLldbGdbServer
Use the new gdb-remote test case factory to generate debugserver and
llgs variants, handling the simple cases first.
Juneyoung Lee [Tue, 29 Dec 2020 08:02:25 +0000 (17:02 +0900)]
Precommit tests that have poison as shufflevector's placeholder
This commit copies existing tests at llvm/Transforms containing
'shufflevector X, undef' and replaces them with 'shufflevector X, poison'.
The new copied tests have *-inseltpoison.ll suffix at its file name
(as
db7a2f347f132b3920415013d62d1adfb18d8d58 did)
See https://reviews.llvm.org/D93793
Test files listed using
grep -R -E "^[^;]*shufflevector <.*> .*, <.*> undef" | cut -d":" -f1 | uniq
Test files copied & updated using
file_org=llvm/test/Transforms/$1
if [[ "$file_org" = *-inseltpoison.ll ]]; then
file=$file_org
else
file=${file_org%.ll}-inseltpoison.ll
if [ ! -f $file ]; then
cp $file_org $file
fi
fi
sed -i -E 's/^([^;]*)shufflevector <(.*)> (.*), <(.*)> undef/\1shufflevector <\2> \3, <\4> poison/g' $file
head -1 $file | grep "Assertions have been autogenerated by utils/update_test_checks.py" -q
if [ "$?" == 1 ]; then
echo "$file : should be manually updated"
# The test is manually updated
exit 1
fi
python3 ./llvm/utils/update_test_checks.py --opt-binary=./build-releaseassert/bin/opt $file
Georgii Rymar [Mon, 28 Dec 2020 10:20:00 +0000 (13:20 +0300)]
[LLD][ELF] - Use LLVM_ELF_IMPORT_TYPES_ELFT instead of multiple types definitions. NFCI.
We can reduce the number of "using" declarations.
`LLVM_ELF_IMPORT_TYPES_ELFT` was extended in D93801.
Differential revision: https://reviews.llvm.org/D93856
Pavel Labath [Mon, 28 Dec 2020 19:57:45 +0000 (20:57 +0100)]
[lldb] Fix logging in lldb-server tests
Fangrui Song [Tue, 29 Dec 2020 04:30:31 +0000 (20:30 -0800)]
[ubsan][test] FLush stdout before checking interleaved stdout/stderr
Detected by musl.
Arthur Eubanks [Tue, 29 Dec 2020 04:17:31 +0000 (20:17 -0800)]
[test] Fix conditional-temporaries.cpp
Broken by https://reviews.llvm.org/D93880.
(but now the test is much better :) )
Arthur Eubanks [Mon, 28 Dec 2020 21:07:46 +0000 (13:07 -0800)]
[NewPM] Port infer-address-spaces
And add it to the AMDGPU opt pipeline.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D93880
Fangrui Song [Tue, 29 Dec 2020 03:56:08 +0000 (19:56 -0800)]
[asan][test] Annotate glibc specific tests with REQUIRES: glibc-2.27
Kazu Hirata [Tue, 29 Dec 2020 03:55:20 +0000 (19:55 -0800)]
[CFGPrinter] Use succ_empty (NFC)
Kazu Hirata [Tue, 29 Dec 2020 03:55:18 +0000 (19:55 -0800)]
[Scalar] Construct SmallVector with iterator ranges (NFC)
Kazu Hirata [Tue, 29 Dec 2020 03:55:16 +0000 (19:55 -0800)]
[CodeGen] Use llvm::append_range (NFC)