Hyunjun Ko [Wed, 15 Sep 2021 06:56:09 +0000 (06:56 +0000)]
freedreno/a5xx,a6xx: rename MSAA_ENABLE to LINE_MODE in GRAS_SU_CNTL
This bit seems like the control for line mode of rastrization.
That can be simply figured out by comparing
dEQP-VK.rasterization.primitives.no_stipple.bresenham_lines,
dEQP-VK.rasterization.primitives.no_stipple.rectangular_lines and
dEQP-VK.rasterization.primitives.no_stipple.lines.
For opengl, the value of bresenham lines mode, which is 0, is set
by default and the value of rectangular mode, which is 0x1, is set
when multi-sampled.
For vulkan, the bresenham lines are enabled when lineRasterizationMode is
VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT, which sets the bit to 0, while
the value is 1 when it's VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT,
that seems to be default.
If both multi-sampled and bresenham-lines are used when primitive type is
line, the bit is to be set as 0 and makes msaa disabled.
Note that this is only tested on a6xx, but I guess it's likely the same
for a5xx.
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6020>
Tapani Pälli [Wed, 13 Oct 2021 07:37:32 +0000 (10:37 +0300)]
anv: use vk_object_zalloc for wsi fences created
Otherwise we hit assert in vk_object_base_assert_valid when attemping to
create handle from anv_fence with unknown base type.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13330>
Emma Anholt [Tue, 12 Oct 2021 20:40:42 +0000 (13:40 -0700)]
radeonsi: Fix leak of screen->perfcounters.
A refactor dropped one of the frees.
Fixes:
380ac288911d ("ac: import performance counters from RadeonSI")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13322>
Yipeng Chen (Jasber) [Tue, 12 Oct 2021 08:37:24 +0000 (16:37 +0800)]
radeonsi: do not use staging texture for APU
This is to fix serious performance drop of texture_upload/
texture_resue relative items in chromeos glbench test.
Staging texture is not efficient for CPU uploading.
Signed-off-by: Jasber Chen <yipeng.chen@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13306>
Marek Olšák [Tue, 5 Oct 2021 21:16:10 +0000 (17:16 -0400)]
radeonsi: simplify write_psize code in si_get_vs_out_cntl
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12789>
Marek Olšák [Tue, 5 Oct 2021 21:14:06 +0000 (17:14 -0400)]
radeonsi: simplify how VS_OUT_CCDIST is set
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12789>
Arvind Yadav [Thu, 30 Sep 2021 12:04:02 +0000 (17:34 +0530)]
radeonsi: remove the use of PKT3_CONTEXT_REG_RMW
This patch is to to remove PKT3_CONTEXT_REG_RMW from radeonsi.
and avoid multiple command buffer(PM4 packet)creation for R_02881C_PA_CL_VS_OUT_CNTL.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Arvind Yadav <arvind.yadav@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12789>
Timur Kristóf [Tue, 12 Oct 2021 14:36:47 +0000 (16:36 +0200)]
drirc: Apply radv_invariant_geom workaround to World War Z games.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5433
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13312>
Timur Kristóf [Tue, 12 Oct 2021 14:29:01 +0000 (16:29 +0200)]
drirc: Apply radv_invariant_geom workaround to Resident Evil Village.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5071
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13312>
Timur Kristóf [Tue, 12 Oct 2021 14:21:11 +0000 (16:21 +0200)]
drirc: Fix indentation.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13312>
Marek Olšák [Wed, 6 Oct 2021 06:23:43 +0000 (02:23 -0400)]
ac/surface: enable better display DCC for chips newer than Yellow Carp
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13214>
Marek Olšák [Wed, 6 Oct 2021 06:35:08 +0000 (02:35 -0400)]
ac/surface: disallow display DCC for big resolutions
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13214>
Marek Olšák [Wed, 6 Oct 2021 06:26:20 +0000 (02:26 -0400)]
ac/surface: always use suboptimal display DCC with DRM <= 3.43.0
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13214>
Tapani Pälli [Tue, 12 Oct 2021 08:13:49 +0000 (11:13 +0300)]
anv/android: fix parameters given for vk_common_QueueSubmit
Common queue submit expects pWaitDstStageMask to be set per each
semaphore (as per Vulkan spec) and crashes if these are not given
properly.
This fixes crashes seen when running vulkan apps on Android.
v2: change the VkPipelineStageFlags given (Lionel)
Fixes:
b996fa8efaa4 ("anv: implement VK_KHR_synchronization2")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13305>
Kyle Brenneman [Tue, 12 Oct 2021 14:32:52 +0000 (08:32 -0600)]
Remove the shebang from eglFunctionList.py.
eglFunctionList.py isn't executed directly, so it doesn't need a shebang
line.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13130>
Kyle Brenneman [Thu, 30 Sep 2021 19:46:39 +0000 (13:46 -0600)]
Add copyright comments to the GLVND-related files.
A few of the GLVND-related files were missing a copyright comment at the
top. Copy the same MIT license text from gen_egl_dispatch.py et. al.
https://gitlab.freedesktop.org/mesa/mesa/-/issues/5267
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13130>
Rhys Perry [Wed, 30 Jun 2021 16:03:37 +0000 (17:03 +0100)]
radv: enable VK_EXT_vertex_input_dynamic_state
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4768
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Wed, 12 May 2021 14:46:53 +0000 (15:46 +0100)]
radv: implement VK_EXT_vertex_input_dynamic_state
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Mon, 17 May 2021 16:56:28 +0000 (17:56 +0100)]
aco: implement VS input loads with prologs
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Mon, 17 May 2021 16:53:30 +0000 (17:53 +0100)]
aco: implement aco_compile_vs_prolog
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Mon, 17 May 2021 18:17:15 +0000 (19:17 +0100)]
radv: add pre-compiled vertex shader prologs for common states
This lets us pre-compile a prolog and avoid a hash table lookup during
command buffer recording, most of the time.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Fri, 16 Apr 2021 10:55:59 +0000 (11:55 +0100)]
radv: implement dynamic vertex input state using vertex shader prologs
This doesn't actually use the functionality or implement prolog
compilation yet.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Fri, 21 May 2021 14:26:38 +0000 (15:26 +0100)]
radv: move VS specific input SGPRs first
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Fri, 14 May 2021 11:44:17 +0000 (12:44 +0100)]
radv: add segregated fit shader memory allocator
Way faster than the previous one, especially with a large number of
shaders.
This doesn't have much of an effect right now, but the previous allocator
was expensive compared to the cost of compiling vertex shader prologs.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Thu, 27 May 2021 16:29:42 +0000 (17:29 +0100)]
radv: add radv_shader_variant_get_va and radv_find_shader_variant helpers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Fri, 2 Jul 2021 15:02:37 +0000 (16:02 +0100)]
radv: add radv_translate_vertex_format()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Fri, 2 Jul 2021 15:07:51 +0000 (16:07 +0100)]
radv: add and use radv_vs_input_alpha_adjust
Unlike ac_fetch_format, this enum can be packed into two bits.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Rhys Perry [Wed, 18 Aug 2021 12:29:59 +0000 (13:29 +0100)]
aco: fix vadd32() when b is neither a constant nor temporary
This will be useful for compiling vertex shader prologs, where we
basically use ACO as an assembler.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
Qiang Yu [Wed, 29 Sep 2021 07:22:33 +0000 (15:22 +0800)]
nir/linker: rename replace_constant_input to replace_varying_input_by_constant_load
To align with replace_varying_input_by_uniform_load and better
describe what it does.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12613>
Qiang Yu [Mon, 30 Aug 2021 07:51:50 +0000 (15:51 +0800)]
nir/linker: support uniform when optimizing varying
Varying assigned from uniform won't change after interpolation,
so move uniform load to fragment shader to eliminate the varying.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12613>
Qiang Yu [Wed, 8 Sep 2021 06:44:11 +0000 (14:44 +0800)]
mesa/st: delay nir spirv link
Following commit for st_nir_link_shaders->nir_link_opt_varyings
may copy uniform variable from one shader to another, so delay
the nir_spirv link which contains mesa uniform information
update (gl_nir_link_uniforms) after it and align with glsl link.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12613>
Felix DeGrood [Wed, 25 Aug 2021 21:12:36 +0000 (21:12 +0000)]
anv: dirty only state impacted by blorp_exec
Instead of dirtying all state after blorp operations,
avoid dirtying state that blorp never touches.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5077
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12567>
Filip Gawin [Tue, 12 Oct 2021 11:53:52 +0000 (13:53 +0200)]
r300: fixes for UB caused by left shifts
r300_vs.c:252:37: runtime error: left shift of negative value -1
r300_state.c:1824:66: runtime error: left shift of 63112 by 16 places
cannot be represented in type 'int'
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13308>
Marek Olšák [Tue, 12 Oct 2021 13:36:13 +0000 (09:36 -0400)]
radeonsi: fix an out-of-bounds access in si_create_vertex_state
Fixes:
fb8f532ea1b - radeonsi: implement draw_vertex_state for lower display list overhead
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5484
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13309>
Marek Olšák [Sun, 27 Jun 2021 21:57:56 +0000 (17:57 -0400)]
radeonsi: align pipe_resource & sampler_view allocations to a cache line
It eliminates "False Sharing" for atomic operations. (see wikipedia)
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11618>
Marek Olšák [Sun, 27 Jun 2021 21:55:29 +0000 (17:55 -0400)]
util,gallium: put count in pipe_resource & sampler_view on its own cache line
This adds 60 bytes to both structures. It eliminates "False Sharing"
for atomic operations (see wikipedia).
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11618>
Daniel Schürmann [Mon, 11 Oct 2021 14:14:21 +0000 (16:14 +0200)]
driconf: set vk_x11_strict_image_count for Wolfenstein: Youngblood
Otherwise, the game refuses to start on xwayland.
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13289>
Filip Gawin [Tue, 12 Oct 2021 17:22:26 +0000 (19:22 +0200)]
nir: avoiding reading unitialized memory when using nir_dest_copy
Deeper in chain of calls, function "src_has_indirect" is used (which
reads "is_ssa" and "reg.indirect").
Fixes:
d1eae6f36be6 ("nir: Properly clean up nir_src/dest indirects")
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13317>
Danylo Piliaiev [Tue, 12 Oct 2021 15:03:37 +0000 (18:03 +0300)]
turnip: fix streamout buffer offset calculations
Fixes vkd3d test "test_vbv_stride_edge_cases"
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13315>
Emma Anholt [Thu, 7 Oct 2021 19:07:31 +0000 (12:07 -0700)]
ci: Update piglit to
7d7dd2688c214e1b3c00f37226500cbec4a58efb.
This brings in a bunch of i915g spurious fail fixes, fixes for !12613, and
new tests.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13253>
Emma Anholt [Fri, 17 Sep 2021 18:52:38 +0000 (11:52 -0700)]
ci: Update deqp to vulkan-cts-1.2.7.1.
Brings in some VK fixes for tilers.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13253>
Jason Ekstrand [Wed, 6 Oct 2021 18:11:30 +0000 (13:11 -0500)]
vulkan/wsi/display: Delete the wrapper entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 17:32:20 +0000 (12:32 -0500)]
vulkan/wsi/wayland: Delete the wrapper entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 17:29:10 +0000 (12:29 -0500)]
vulkan/wsi/x11: Delete the wrapper entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 17:42:18 +0000 (12:42 -0500)]
vulkan/wsi/common: Delete the wrapper entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 17:20:56 +0000 (12:20 -0500)]
venus: Use the common WSI wrappers
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 16:58:48 +0000 (11:58 -0500)]
lavapipe: Use the common WSI wrappers
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 16:54:13 +0000 (11:54 -0500)]
panvk: Use the common WSI wrappers
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 16:45:06 +0000 (11:45 -0500)]
v3dv: Use the common WSI wrappers
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 16:39:06 +0000 (11:39 -0500)]
turnip: Use the common WSI wrappers
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 16:34:22 +0000 (11:34 -0500)]
radv: Use the common WSI wrappers
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 16:21:55 +0000 (11:21 -0500)]
anv: Use the common WSI wrappers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 16:09:12 +0000 (11:09 -0500)]
vulkan/wsi: Add common wrappers for most entrypoints
For a long time, our Vulkan WSI code has acted as something of a layer.
The WSI code calls into various Vulkan entrypoints inside the driver to
create images, allocate memory, etc. It then implements the API-facing
interface almost entirely. The only thing the driver has to provide is
little wrappers that wrap around the WSI calls to expose them through
the API.
However, now that we have a common dispatch framework, we can implement
entrypoints directly in the WSI code. As long as the driver uses
vk_instance, vk_physical_device, and vk_device, we can provide common
wrappers for the vast majority of entrypoints. The only exceptions are
vkAcquireNextImage, vkQueuePresent, vkRegisterDeviceEventEXT, and
vkRegisterDisplayEventEXT because those may have to manually poke at
synchronization primitives. We provide wrappers for vkAcquireNextImage
and vkQueuePresent because some drivers can use the default versions.
For now, we're intentionally avoiding any link-time dependencies between
WSI and the common code. We only use VK_FROM_HANDLE and associated
inline helpers and vk_physical_device has a pointer to a wsi_device.
Eventually, we may tie the two together closer, but this lets us get 95%
of the way there without reworking the universe.
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 14:37:32 +0000 (09:37 -0500)]
vulkan/wsi: Add a dispatch table for WSI entrypoints
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Jason Ekstrand [Wed, 6 Oct 2021 14:32:17 +0000 (09:32 -0500)]
meson: Add and use an idep for Vulkan WSI
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>
Ella-0 [Sun, 10 Oct 2021 14:42:30 +0000 (14:42 +0000)]
v3dv: enable VK_KHR_surface_protected_capabilities
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13298>
Eric Engestrom [Mon, 2 Aug 2021 20:16:34 +0000 (21:16 +0100)]
egl: implement EGL_EXT_present_opaque on wayland
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: James Jones <jajones@nvidia.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12373>
Eric Engestrom [Wed, 18 Aug 2021 17:58:36 +0000 (18:58 +0100)]
egl: sync eglext.h & egl.xml from Khronos
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12373>
Emma Anholt [Tue, 12 Oct 2021 16:17:14 +0000 (09:17 -0700)]
ci/freedreno: Disable the minetest trace due to flaky shader code.
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4595
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13316>
Nanley Chery [Tue, 22 Jun 2021 17:24:31 +0000 (10:24 -0700)]
iris: Tile cache flush for depth before fast clear
Instead of doing a tile cache flush after slow clears or when the clear
value changes, do it before every fast clear of a HIZ_CCS_WT surface.
This agrees with the Bspec.
Fixes:
c85ea824bca ("iris: reduce redundant tile cache flushes")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
Nanley Chery [Tue, 22 Jun 2021 17:35:08 +0000 (10:35 -0700)]
anv: Tile cache flush for depth before fast clear
Instead of doing a tile cache flush after slow clears, resolves, and
ambiguates, do it before fast clears of HIZ_CCS_WT surfaces. This agrees
with the Bspec.
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
Nanley Chery [Tue, 5 Oct 2021 19:02:23 +0000 (12:02 -0700)]
anv: Allow HIZ_CCS_WT with subpass self-dependencies
This unblocks later commits that aim to align the driver with the tile
cache flushing requirements in the Bspec.
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
Danylo Piliaiev [Tue, 12 Oct 2021 14:14:21 +0000 (17:14 +0300)]
ir3/freedreno: handle non-uniform a1en instructions
Fixes vkd3d test "test_bindless_samplers_sm51"
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13311>
Danylo Piliaiev [Tue, 12 Oct 2021 13:37:07 +0000 (16:37 +0300)]
ir3/freedreno: handle non-uniform resinfo
We forgot to handle non-uniform resinfo case.
Fixes vkd3d test "test_bindless_bufinfo_sm51"
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13311>
Timur Kristóf [Thu, 30 Sep 2021 12:32:07 +0000 (14:32 +0200)]
aco/optimizer: Skip SDWA on v_lshlrev when unnecessary in apply_extract.
In the following cases:
- lower 16 bits are extracted and the shift amount is 16 or more
- lower 8 bits are extracted and the shift amount is 24 or more
the undesireable upper bits are already shifted out, and therefore
there is no need to add SDWA to the v_lshlrev instruction.
Fossil DB stats on Sienna Cichlid with NGGC on:
Totals from 58239 (45.27% of 128647) affected shaders:
CodeSize:
153498624 ->
153265616 (-0.15%); split: -0.15%, +0.00%
Instrs:
29636304 ->
29578064 (-0.20%); split: -0.20%, +0.00%
Latency:
136931496 ->
136876379 (-0.04%); split: -0.04%, +0.00%
InvThroughput:
21134367 ->
21078861 (-0.26%); split: -0.26%, +0.00%
Copies: 2777550 -> 2777548 (-0.00%); split: -0.00%, +0.00%
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13121>
Timur Kristóf [Thu, 30 Sep 2021 12:09:29 +0000 (14:09 +0200)]
ac/nir/nggc: Write undef to variables in non-repacked ES threads.
This helps the compiler generate a little bit more efficient code.
Fossil DB stats on Sienna Cichlid with NGGC on:
Totals from 4659 (3.62% of 128647) affected shaders:
CodeSize: 7468320 -> 7404484 (-0.85%); split: -0.88%, +0.03%
Instrs: 1423425 -> 1407454 (-1.12%); split: -1.16%, +0.03%
Latency: 5250593 -> 5226163 (-0.47%); split: -0.47%, +0.00%
InvThroughput: 739848 -> 733373 (-0.88%); split: -0.90%, +0.02%
Copies: 200139 -> 190307 (-4.91%); split: -5.13%, +0.22%
Branches: 87925 -> 85998 (-2.19%)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13121>
Timur Kristóf [Mon, 11 Oct 2021 18:41:35 +0000 (20:41 +0200)]
ac/nir/cull: Accept NaN and +/- Inf in face culling.
When the determinant that we use for calculating triangle area
is NaN, it's not possible to decide the facing of the triangle.
This can happen when a coordinate of one of the triangle's vertices
is INFINITY. It's better to just accept these triangles in the shader
and let the PA deal with them.
Let's do the same for +/- Infinity too.
Though we haven't seen this yet, it may be troublesome as well.
Fixes:
651a3da1b59446a6e392321d1dbbc1891a0544a8
Closes: #5470
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13299>
Bas Nieuwenhuizen [Tue, 12 Oct 2021 01:23:21 +0000 (03:23 +0200)]
amd/common: Add fallback for misreported clocks for RGP.
Traces with clock = 0 are totally useless due to RGP getting very
confused.
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13301>
Connor Abbott [Mon, 4 Oct 2021 11:38:57 +0000 (13:38 +0200)]
ir3: Fold ldc src immediates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Mon, 4 Oct 2021 11:20:53 +0000 (13:20 +0200)]
ir3: Fix handling cat6 immediates
We were treating them the same as regular cat2/cat3/cat4 immediates, but
that's not right because cat6 sources are only 8 bits.
Our bindless code was handling this before for bindless resources, and
it was disabled for most other things, so this was mostly harmless, but
fixing it will be necessary for handling ldc offsets.
In addition enable tests for this that were just commented out, and add
a custom test making sure that the immediate source is treated as
unsigned.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Mon, 4 Oct 2021 10:03:25 +0000 (12:03 +0200)]
ir3: Fix check for immediate range
This would incorrectly allow both e.g. 0x2000 and 0xffffe000 to be
encoded as 0x2000.
Fixes:
f0a1f3de278 ("freedreno/ir3: cp small negative integers too")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Wed, 29 Sep 2021 14:19:10 +0000 (16:19 +0200)]
ir3/legalize: handle WAR for special regs
In particular many cat5/cat6 instructions read a1.x, and we need to add
a (ss) before any mova1 instruction afterwards, as the blob does.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Wed, 29 Sep 2021 14:17:31 +0000 (16:17 +0200)]
ir3: Handle special regs in regmask
Use the same hack as post-RA scheduling.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Wed, 29 Sep 2021 14:04:36 +0000 (16:04 +0200)]
ir3: Remove separate regmask.h
Inline it into its one user. There's no point in keeping it separate,
and in order to handle special registers it will have to become a bit
more intertwined with core ir3.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Wed, 29 Sep 2021 11:52:34 +0000 (13:52 +0200)]
ir3: Always create barycentrics in the input block
Otherwise, when there are uses in multiple blocks the collect may not
dominate some of the uses.
This is a bugfix, but before it would've mattered only in weird
scenarios with interpolateAt*. When we start moving prefetch textures
into the block before the preamble it will start to matter more, because
it will need to read the barycentrics from a different block than the
bary.f instructions.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Wed, 29 Sep 2021 11:24:43 +0000 (13:24 +0200)]
ir3: Make ir3_create_collect() take a block
There's no reason to make this any different from the other builders,
since it just creates a collect instruction, and in the next commit
we'll need to create a collect in the first block for prefetch textures.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Fri, 24 Sep 2021 17:00:22 +0000 (19:00 +0200)]
ir3: Fix printing branch type
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Mon, 27 Sep 2021 14:17:42 +0000 (16:17 +0200)]
nir/lower_ubo_vec4: Fix align_mul=8 special case
In order for the load to never straddle the load can't extend past 8
bytes, not 16. For example a vec2 load with align_mul = 8 and
align_offset = 4 can straddle.
Fixes assertion failures when we stop pushing UBOs in the preamble on
a6xx.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Fri, 24 Sep 2021 16:51:58 +0000 (18:51 +0200)]
ir3/cp: Fix inlining 32->16 const into meta instructions
We shouldn't return early here, because we still need to actually do the
conversion. Fixes an infinite loop.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Connor Abbott [Mon, 27 Sep 2021 13:52:23 +0000 (15:52 +0200)]
ir3/cp: Add missing const promotion check
We need to check the source type for moves when the destination type is
u16, just like the f16 check above.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
Joshua Ashton [Mon, 11 Oct 2021 05:59:20 +0000 (06:59 +0100)]
radv: Do early and late tests for fast clears
We don't know some information regarding DCC image stores and therefore fast clears until we know the surface info.
We should work towards eliminating this, but the cases where this will hit on GFX10_3 is basically 0.
Finally fixes a perf regression in Doom Eternal.
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13283>
Samuel Pitoiset [Tue, 17 Aug 2021 07:05:09 +0000 (09:05 +0200)]
radv: implement VK_KHR_format_feature_flags2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13194>
Samuel Pitoiset [Tue, 17 Aug 2021 06:56:02 +0000 (08:56 +0200)]
radv: switch to VK_FORMAT_FEATURE_2_XXX/VkFormatProperties3KHR
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13194>
Samuel Pitoiset [Thu, 7 Oct 2021 08:26:46 +0000 (10:26 +0200)]
radv: remove duplicated code about NGG passthrough determination
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
Samuel Pitoiset [Thu, 7 Oct 2021 08:23:51 +0000 (10:23 +0200)]
radv: do not initialize is_ngg_passthrough for geometry shaders
Geometry shaders can't be NGG passthrough at all.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
Samuel Pitoiset [Thu, 7 Oct 2021 08:18:43 +0000 (10:18 +0200)]
aco: cleanup setup_vs_output_info()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
Samuel Pitoiset [Thu, 7 Oct 2021 07:50:33 +0000 (09:50 +0200)]
radv: stop gathering output GS info for vertex shaders
This has no effect.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
Samuel Pitoiset [Wed, 6 Oct 2021 12:18:01 +0000 (14:18 +0200)]
radv: rename needs_multiview_view_index to uses_view_index
To avoid confusion with radv_pipeline_key::has_multiview_view_index.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
Samuel Pitoiset [Wed, 6 Oct 2021 12:11:50 +0000 (14:11 +0200)]
radv: remove no-op about the view index in the shader info pass
The view index is always lowered to map the layer ID for fragment
shaders. This was never reached.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
Samuel Pitoiset [Wed, 6 Oct 2021 12:06:59 +0000 (14:06 +0200)]
radv,aco: remove nir_intrinsic_load_layer_id
This was never used because the layer ID isn't a system value.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>
Bas Nieuwenhuizen [Thu, 16 Sep 2021 22:45:11 +0000 (00:45 +0200)]
radv: Handle copying zero queries.
Looks like this is allowed.
Fixes:
8475a14302e ("radv: Implement pipeline statistics queries.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12907>
Esme Xuan Lim [Mon, 11 Oct 2021 18:09:38 +0000 (02:09 +0800)]
docs/panfrost: Fix link to use rst syntax
Currently the link uses markdown syntax to direct users to IRC, switch
to IRC to render this correctly.
Fixes:
e39929663bb ("docs/panfrost: Add web chat link")
Signed-Off by: Esme Xuan Lim <esmethedev@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13296>
Vinson Lee [Sun, 10 Oct 2021 22:46:21 +0000 (15:46 -0700)]
freedreno: Add valgrind dependency.
Fix a build error.
In file included from ../src/util/u_queue.h:38,
from ../src/freedreno/drm/freedreno_ringbuffer.h:33,
from ../src/freedreno/ds/fd_pps_driver.h:13,
from ../src/freedreno/ds/fd_pps_driver.cc:7:
../src/util/simple_mtx.h:35:12: fatal error: valgrind.h: No such file or directory
35 | # include <valgrind.h>
| ^~~~~~~~~~~~
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13280>
Iván Briano [Thu, 7 Oct 2021 18:53:27 +0000 (11:53 -0700)]
vulkan: Generate defines for aliases of promoted enums
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13264>
Iván Briano [Thu, 7 Oct 2021 18:21:51 +0000 (11:21 -0700)]
vulkan: fix handling of aliases in enum members
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13264>
Connor Abbott [Thu, 30 Sep 2021 12:52:44 +0000 (14:52 +0200)]
ir3/ra: Use killed sources in register eviction
Let's assume we have a vec2 collect instruction with killed sources that
are non-contiguous and the entire rest of the register file is blocked,
which can happen when our register target is very tight. It's impossible
to just insert move instructions to resolve this, but we can make space
by swapping one of the killed sources with the value next to the other,
assuming it's also scalar.
This commit implements that idea, preventing us from falling back to the
terrible shuffle-everything approach in this case.
total instructions in shared programs: 1566648 -> 1565117 (-0.10%)
instructions in affected programs: 13332 -> 11801 (-11.48%)
helped: 30
HURT: 5
helped stats (abs) min: 6 max: 535 x̄: 51.77 x̃: 25
helped stats (rel) min: 2.67% max: 33.63% x̄: 12.28% x̃: 9.58%
HURT stats (abs) min: 1 max: 6 x̄: 4.40 x̃: 6
HURT stats (rel) min: 0.18% max: 5.13% x̄: 2.41% x̃: 2.13%
95% mean confidence interval for instructions value: -75.05 -12.43
95% mean confidence interval for instructions %-change: -13.18% -7.18%
Instructions are helped.
total mov in shared programs: 77336 -> 76683 (-0.84%)
mov in affected programs: 2135 -> 1482 (-30.59%)
helped: 29
HURT: 5
helped stats (abs) min: 2 max: 227 x̄: 23.31 x̃: 10
helped stats (rel) min: 6.06% max: 72.73% x̄: 31.83% x̃: 30.00%
HURT stats (abs) min: 2 max: 9 x̄: 4.60 x̃: 4
HURT stats (rel) min: 14.29% max: 69.23% x̄: 34.00% x̃: 27.78%
95% mean confidence interval for mov value: -33.21 -5.20
95% mean confidence interval for mov %-change: -32.94% -11.35%
Mov are helped.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13143>
Connor Abbott [Thu, 30 Sep 2021 09:12:37 +0000 (11:12 +0200)]
ir3/ra: Don't reset round-robin start for each block
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13143>
Connor Abbott [Thu, 30 Sep 2021 09:53:14 +0000 (11:53 +0200)]
ir3: Initialize local size earlier
We need the local size in RA for occupancy calculations. Not
initializing these had the unfortunate consequence of
ir3_get_reg_independent_max_waves() returning 0 for compute shaders with
shared variables, disabling the register limiting logic.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13143>
Lionel Landwerlin [Wed, 7 Jul 2021 16:15:15 +0000 (19:15 +0300)]
anv: implement VK_KHR_format_feature_flags2
v2: fix SAMPLED_IMAGE_DEPTH_COMPARISON_BIT_KHR (Ivan)
v3: Fixup VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR setting (Ivan)
Add missing drm-modifiers/android bits (Lionel)
v4: Avoid duplicating get_ahw_buffer_format_properties() (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>
Lionel Landwerlin [Tue, 5 Oct 2021 18:39:04 +0000 (21:39 +0300)]
anv: start computing KHR_format_features2 flags for storage images
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>