Tom Rini [Wed, 6 Jul 2022 13:17:08 +0000 (09:17 -0400)]
Merge tag 'efi-2022-07-rc7' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2022-07-rc7
UEFI:
* correct verification of signed UEFI binaries
Tom Rini [Wed, 6 Jul 2022 13:15:36 +0000 (09:15 -0400)]
Merge branch '2022-07-05-more-Kconfig-migrations' into next
- Migrate more CONFIG symbols to Kconfig, remove some dead code and
clean-up arch/Kconfig.nxp slightly more.
Tom Rini [Mon, 20 Jun 2022 12:07:58 +0000 (08:07 -0400)]
Convert CONFIG_KIRKWOOD_PCIE_INIT et al to Kconfig
This converts the following to Kconfig:
CONFIG_KIRKWOOD_EGIGA_INIT
CONFIG_KIRKWOOD_PCIE_INIT
CONFIG_KIRKWOOD_RGMII_PAD_1V8
CONFIG_KM_DISABLE_PCIE
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:57 +0000 (08:07 -0400)]
qemu-ppce500: Move CONFIG_SYS_PCI_MAP_{START, END} to board code
These CONFIG options are only used on this board, in the board file
itself. Remove these from the CONFIG namespace and define in the board
file.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:56 +0000 (08:07 -0400)]
Convert CONFIG_SYS_FSL_PCI_VER_3_X to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_FSL_PCI_VER_3_X
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:55 +0000 (08:07 -0400)]
Convert CONFIG_PCI_MSC01 to Kconfig
This converts the following to Kconfig:
CONFIG_PCI_MSC01
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:54 +0000 (08:07 -0400)]
socrates: Rework CONFIG_PCI_CLK_FREQ
The symbol CONFIG_PCI_CLK_FREQ is local to this board. Provide equal
clarity in the code by referencing the numeric value directly and move
the explanatory comment to the code, just prior to use.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:53 +0000 (08:07 -0400)]
Convert CONFIG_SH7751_PCI to Kconfig
This converts the following to Kconfig:
CONFIG_SH7751_PCI
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:52 +0000 (08:07 -0400)]
MPC837XERDB: Remove unused PCI defines
These defines aren't referenced in code today, remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:51 +0000 (08:07 -0400)]
m68k: Remove unused PCI code
The only mcf5445x platform does not enable PCI, drop this code.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:50 +0000 (08:07 -0400)]
Convert CONFIG_PCI_CONFIG_HOST_BRIDGE to Kconfig
This converts the following to Kconfig:
CONFIG_PCI_CONFIG_HOST_BRIDGE
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:49 +0000 (08:07 -0400)]
Convert CONFIG_PCI_GT64120 to Kconfig
This converts the following to Kconfig:
CONFIG_PCI_GT64120
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:48 +0000 (08:07 -0400)]
Convert CONFIG_PCI_SCAN_SHOW to Kconfig
This converts the following to Kconfig:
CONFIG_PCI_SCAN_SHOW
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:47 +0000 (08:07 -0400)]
pci: Remove pci_sh4 and related defines.
This driver is not enabled anywhere, remove it. Also remove definitions
of symbols only used in this driver, on platforms that did not enable
it.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:46 +0000 (08:07 -0400)]
Convert CONFIG_PCIE_IMX to Kconfig
This converts the following to Kconfig:
CONFIG_PCIE_IMX
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:45 +0000 (08:07 -0400)]
Convert CONFIG_PCIE1 et al to Kconfig
This converts the following to Kconfig:
CONFIG_PCIE1
CONFIG_PCIE2
CONFIG_PCIE3
CONFIG_PCIE4
CONFIG_PCI1
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:44 +0000 (08:07 -0400)]
Convert CONFIG_LAYERSCAPE_NS_ACCESS to Kconfig
This converts the following to Kconfig:
CONFIG_LAYERSCAPE_NS_ACCESS
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:43 +0000 (08:07 -0400)]
lcd: Remove legacy CONFIG_FB_ADDR code
No platforms set both CONFIG_LCD and CONFIG_FB_ADDR at this time, drop
this legacy code.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 20 Jun 2022 12:07:42 +0000 (08:07 -0400)]
Convert CONFIG_FSL_FIXED_MMC_LOCATION et al to Kconfig
This converts the following to Kconfig:
CONFIG_FSL_FIXED_MMC_LOCATION
CONFIG_ESDHC_HC_BLK_ADDR
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 17 Jun 2022 20:24:34 +0000 (16:24 -0400)]
powerpc: Clean up CHAIN_OF_TRUST related options
As things stand currently, there is only one PowerPC platform that
enables the options for CHAIN_OF_TRUST. From the board header files,
remove a number of never-set options. Remove board specific values from
arch/powerpc/include/asm/fsl_secure_boot.h as well. Rework
include/config_fsl_chain_trust.h to not abuse the CONFIG namespace for
constructing CHAIN_BOOT_CMD. Migrate all of the configurable addresses
to Kconfig.
If any platforms are re-introduced with secure boot support, everything
required should still be here, but now in Kconfig, or requires migration
of an option to Kconfig.
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 17 Jun 2022 20:24:33 +0000 (16:24 -0400)]
nxp: config_fsl_chain_trust.h: Clean up and remove unused portions
The way that secure boot is implemented today on NXP ARM platforms does
not reuse the elements found in include/config_fsl_chain_trust.h to
construct CONFIG_SECBOOT but instead board header files have their
environment setup as needed and then fsl_setenv_chain_of_trust() will
set secureboot in the environment. Remove a large number of unused
defines here.
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 17 Jun 2022 20:24:32 +0000 (16:24 -0400)]
fsl_validate: Migrate SPL_UBOOT_KEY_HASH to Kconfig
Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig. As
part of this, change fsl_secboot_validate(...) to check that it is
passed a non-empty string, rather than non-NULL.
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 17 Jun 2022 20:24:31 +0000 (16:24 -0400)]
arch/Kconfig.nxp: Re-organize slightly
Make all of the CHAIN_OF_TRUST options be under a single menu and add a
comment for the rest, so the resulting config file reads more clearly.
Remove duplicate CHAIN_OF_TRUST options from
board/congatec/common/Kconfig. Remove duplicate NXP_ESBC config
questions and move to arch/Kconfig.nxp.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 16 Jun 2022 18:04:40 +0000 (14:04 -0400)]
Convert CONFIG_SYS_FSL_SFP_BE et al to Kconfig
This converts the following to Kconfig:
CONFIG_KEY_REVOCATION
CONFIG_SYS_FSL_SFP_BE
CONFIG_SYS_FSL_SFP_LE
CONFIG_SYS_FSL_SFP_VER_3_0
CONFIG_SYS_FSL_SFP_VER_3_2
CONFIG_SYS_FSL_SFP_VER_3_4
CONFIG_SYS_FSL_SRK_LE
This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for
when CHAIN_OF_TRUST is enabled.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 16 Jun 2022 18:04:39 +0000 (14:04 -0400)]
Convert CONFIG_SYS_FSL_SEC_MON et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_FSL_SEC_MON
CONFIG_SYS_FSL_SEC_MON_BE
CONFIG_SYS_FSL_SEC_MON_LE
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 16 Jun 2022 18:04:38 +0000 (14:04 -0400)]
Convert CONFIG_ESDHC_DETECT_QUIRK to Kconfig
This converts the following to Kconfig:
CONFIG_ESDHC_DETECT_QUIRK
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 16 Jun 2022 18:04:37 +0000 (14:04 -0400)]
Convert CONFIG_ESBC_HDR_LS et al to Kconfig
This converts the following to Kconfig:
CONFIG_ESBC_HDR_LS
CONFIG_ESBC_ADDR_64BIT
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 16 Jun 2022 18:04:36 +0000 (14:04 -0400)]
nxp: Rename board/freescale/common/Kconfig to arch/Kconfig.nxp
Now that board/freescale/common/Kconfig is safe to be included once,
globally, rename this to arch/Kconfig.nxp to better reflect that it
contains options that are valid on multiple architectures and SoC
families, and not specific to NXP reference platforms either.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 16 Jun 2022 18:04:35 +0000 (14:04 -0400)]
nxp: Make board/freescale/common/Kconfig safe to include once in arch/Kconfig
The way that we use this file currently means that we have to guard it
in every platform Kconfig. But it is also required in all NXP
platforms, including non-reference platforms. Make all options in it
have appropriate dependencies so that we can include it a single time
under arch/Kconfig
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 16 Jun 2022 18:04:34 +0000 (14:04 -0400)]
Convert CONFIG_HETROGENOUS_CLUSTERS et al to Kconfig
This converts the following to Kconfig:
CONFIG_HETROGENOUS_CLUSTERS
CONFIG_SYS_MAPLE
CONFIG_SYS_CPRI
CONFIG_PPC_CLUSTER_START
CONFIG_DSP_CLUSTER_START
CONFIG_SYS_CPRI_CLK
CONFIG_SYS_ULB_CLK
CONFIG_SYS_ETVPE_CLK
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 16 Jun 2022 18:04:33 +0000 (14:04 -0400)]
Convert CONFIG_EXTRA_CLOCK to Kconfig
This converts the following to Kconfig:
CONFIG_EXTRA_CLOCK
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:55 +0000 (12:03 -0400)]
Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_DDR_RAW_TIMING
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:54 +0000 (12:03 -0400)]
Convert CONFIG_SYS_SPD_BUS_NUM to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_SPD_BUS_NUM
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:53 +0000 (12:03 -0400)]
Convert CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR to Kconfig
This converts the following to Kconfig:
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:52 +0000 (12:03 -0400)]
Convert CONFIG_USB_GADGET_DWC2_OTG_PHY to Kconfig
This converts the following to Kconfig:
CONFIG_USB_GADGET_DWC2_OTG_PHY
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:51 +0000 (12:03 -0400)]
Convert CONFIG_USE_ONENAND_BOARD_INIT to Kconfig
This converts the following to Kconfig:
CONFIG_USE_ONENAND_BOARD_INIT
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:50 +0000 (12:03 -0400)]
Convert CONFIG_SAMSUNG_ONENAND to Kconfig
This converts the following to Kconfig:
CONFIG_SAMSUNG_ONENAND
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Rini [Wed, 15 Jun 2022 16:03:49 +0000 (12:03 -0400)]
Rename CONFIG_PWM to CONFIG_PWM_S5P and move to Kconfig
We rename the S5P specific "CONFIG_PWM" to CONFIG_PWM_S5P and move it to
Kconfig. Given the usage of CONFIG_PWM_NX, we have that select this new
symbol.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Rini [Wed, 15 Jun 2022 16:03:48 +0000 (12:03 -0400)]
smdkc100: Remove some unused options
There are a few options we test and set and then never reference, remove
them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:47 +0000 (12:03 -0400)]
nxp: Cleanup some emulator related options.
- Drop the emulator CONFIG test from include/configs/ls1088ardb.h
- Migrate CONFIG_SYS_FSL_DDR_EMU to a select'able option in
drivers/ddr/fsl/Kconfig
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:46 +0000 (12:03 -0400)]
watchdog: designware: Make this depend on WDT
As this driver can dynamically determine the values set in
CONFIG_DW_WDT_BASE when using WDT, so make this depend on WDT rather
than migrate CONFIG_DW_WDT_BASE to Kconfig.
Cc: Chee Tien Fong <tien.fong.chee@intel.com>
Cc: Chin-Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinh.nguyen@intel.com>
Cc: Holger Brunck <holger.brunck@hitachienergy.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Stefan Roese <sr@denx.de>
Cc: hee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Wed, 15 Jun 2022 16:03:45 +0000 (12:03 -0400)]
Convert CONFIG_ENABLE_36BIT_PHYS to Kconfig
This converts the following to Kconfig:
CONFIG_ENABLE_36BIT_PHYS
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:44 +0000 (12:03 -0400)]
net: designware: Rename CONFIG_DW_GMAC_DEFAULT_DMA_PBL to GMAC_DEFAULT_DMA_PBL
This value is always used at the default, rename it for now. This
likely should come from the device tree if non-default, moving forward.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 15 Jun 2022 16:03:43 +0000 (12:03 -0400)]
Convert CONFIG_DW_ALTDESCRIPTOR to Kconfig
This converts the following to Kconfig:
CONFIG_DW_ALTDESCRIPTOR
Signed-off-by: Tom Rini <trini@konsulko.com>
AKASHI Takahiro [Tue, 5 Jul 2022 05:48:15 +0000 (14:48 +0900)]
test/py: efi_secboot: add a test for a forged signed image
In this test case, a image binary, helloworld.efi.signed, is willfully
modified to print a corrupted message while the signature itself is
unchanged.
This binary must be rejected under secure boot mode.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
AKASHI Takahiro [Tue, 5 Jul 2022 05:48:14 +0000 (14:48 +0900)]
efi_loader: image_loader: add a missing digest verification for signed PE image
At the last step of PE image authentication, an image's hash value must be
compared with a message digest stored as the content (of SpcPeImageData type)
of pkcs7's contentInfo.
Fixes: commit
4540dabdcaca ("efi_loader: image_loader: support image authentication")
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
AKASHI Takahiro [Tue, 5 Jul 2022 05:48:13 +0000 (14:48 +0900)]
efi_loader: image_loader: replace EFI_PRINT with log macros
Now We are migrating from EFI_PRINT() to log macro's.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
AKASHI Takahiro [Tue, 5 Jul 2022 05:48:12 +0000 (14:48 +0900)]
efi_loader: signature: export efi_hash_regions()
This function is used to calculate a message digest as part of
authentication process in a later patch.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
AKASHI Takahiro [Tue, 5 Jul 2022 05:48:11 +0000 (14:48 +0900)]
lib: crypto: add mscode_parser
In MS authenticode, pkcs7 should have data in its contentInfo field.
This data is tagged with SpcIndirectData type and, for a signed PE image,
provides a image's message digest as SpcPeImageData.
This parser is used in image authentication to parse the field and
retrieve a message digest.
Imported from linux v5.19-rc, crypto/asymmetric_keys/mscode*.
Checkpatch.pl generates tones of warnings, but those are not fixed
for the sake of maintainability (importing from another source).
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Tom Rini [Tue, 5 Jul 2022 01:30:23 +0000 (21:30 -0400)]
Merge tag 'fsl-qoriq-2022-7-3' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
Several patches from Pali
- fsl_elbc detection fix
- sort p2020 dts node, drop duplicated node
- p1_p2_rdb_pc board cleanup
- simplify mpc85xx _start_cont jumping code
Tom Rini [Mon, 4 Jul 2022 12:18:33 +0000 (08:18 -0400)]
Prepare v2022.07-rc6
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 4 Jul 2022 12:15:34 +0000 (08:15 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Andre Przywara [Sat, 2 Jul 2022 00:45:10 +0000 (01:45 +0100)]
usb: host: ehci-generic: Fix error check
Commit
81755b8c20fe ("usb: host: ehci-generic: Make resets and clocks
optional") improved the error check to cover the reset property being
optional. However this was using the wrong error variable for the
check, so would now never fail.
Use the correct error variable for checking the result of
reset_get_bulk(), to actually report genuine errors.
Fixes:
81755b8c20fe ("usb: host: ehci-generic: Make resets and clocks optional")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Pali Rohár [Tue, 28 Jun 2022 15:54:00 +0000 (17:54 +0200)]
powerpc: mpc85xx: Simplify jump to _start_cont in flash code
After more patches code for jumping to _start_cont symbol in flash memory
involved to code with useless mathematical operations. Currently it does:
r3 := CONFIG_SYS_MONITOR_BASE + ABS(_start_cont) - CONFIG_SYS_MONITOR_BASE
jump to r3
Which is equivalent of just:
r3 := ABS(_start_cont)
jump to r3
The purpose of that code is just to jump to _start_code symbol,
independently of program counter. So branch must be done to absolute
address. Trying to write:
ba _start_cont
just cause linker error:
LD u-boot
powerpc-linux-gnuspe-ld.bfd: arch/powerpc/cpu/mpc85xx/start.o: in function `switch_as':
(.bootpg+0x4b8): relocation truncated to fit: R_PPC_ADDR24 against symbol `_start_cont' defined in .text section in arch/powerpc/cpu/mpc85xx/start.o
make: *** [Makefile:1801: u-boot] Error 1
Probably by the fact that absolute address cannot be expressed by 24-bits.
So write the code via mtlr+blr pattern as it was before and load general
purpose register with absolute address of the symbol:
lis r3,_start_cont@h
ori r3,r3,_start_cont@l
mtlr r3
blr
Seems that gcc and gnu ld linker support symbol@h and symbol@l syntax like
number@h and number@l without any problem. And disassembling of compiler
u-boot binary proved that lis+ori instructions are called with numbers
which represent halves of absolute address of _start_cont symbol.
Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Thu, 23 Jun 2022 16:22:21 +0000 (18:22 +0200)]
board: freescale: p1_p2_rdb_pc: Remove mapping for TDM-PMC card
From whole P1/P2 family of RDB boards is TDM-PMC card (PCI Mezzanine Card,
Freescale PQ-MDS-T1) available only on P1021RDB and P1025RDB boards.
So address mapping for TDM-PMC card on LBC should not be enabled on any
other P1/P2 RDB board as there is no device at that TDM-PMC address.
Support for P1021RDB and P1025RDB boards was already removed from mainline
U-Boot in commits
6d1dd76afe85 ("board/freescale: Remove P1021RDB board
support") and
d521cece5adb ("board/freescale: Remove P1025RDB board
support").
So do not enable TDM-PMC address mapping on remaining P1/P2 RDB boards and
remove all macros related to TDM-PMC address mappings.
Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Thu, 23 Jun 2022 13:25:36 +0000 (15:25 +0200)]
board: freescale: p1_p2_rdb_pc: Allow to compile without __SW_BOOT_SD macro
Add #ifdef guard for __SW_BOOT_SD macro like there are guards for all other
__SW_BOOT_* macros.
Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Thu, 23 Jun 2022 13:18:52 +0000 (15:18 +0200)]
board: freescale: p1_p2_rdb_pc: Allow to compile without BOARD_NAME
Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Thu, 23 Jun 2022 12:39:04 +0000 (14:39 +0200)]
powerpc: dts: p2020: Remove duplicate pic@40000 node
DT node pic@40000 is defined explicitly in p2020-post.dtsi file and also
transitionally via include file pq3-mpic.dtsi. Remove duplicate definition
from p2020-post.dtsi.
No change in final DTB file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Thu, 23 Jun 2022 12:39:03 +0000 (14:39 +0200)]
powerpc: dts: p2020: Sort DT nodes by their addresses
No functional change.
Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Mon, 20 Jun 2022 11:07:03 +0000 (13:07 +0200)]
mtd: rawnand: fsl_elbc: Fix detection when nand_scan_ident() has not selected ecc.mode
ecc.mode is set to 0 (aliased to NAND_ECC_NONE) either when function
nand_scan_ident() has not selected ecc.mode or when it selected it to none
ecc mode.
Distinguish between these two states by checking of node property
"nand-ecc-mode" which function nand_scan_ident() uses for filling ecc.mode.
This change fixes usage of none ecc mode if it is specified in DTS file.
Fixes:
c9ea9019c5aa ("mtd: rawnand: fsl_elbc: Use ECC configuration from device tree")
Signed-off-by: Pali Rohár <pali@kernel.org>
Tom Rini [Sat, 2 Jul 2022 13:55:26 +0000 (09:55 -0400)]
Merge tag 'efi-2022-07-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2022-07-rc6
UEFI:
* Fix EFI_IO_BLOCK_PROTOCOL: read correct blocks on partitions
Other:
* Honor CONFIG_SYS_64BIT_LBA in the disk uclass
Tom Rini [Sat, 2 Jul 2022 13:54:46 +0000 (09:54 -0400)]
Merge branch '2022-07-01-additional-critical-fixes-and-updates'
- Update some MAINTAINERS entries, fix a regression on FIT images
Paul Barbieri [Thu, 30 Jun 2022 11:02:04 +0000 (07:02 -0400)]
EFI: Fix ReadBlocks API reading incorrect sector for UCLASS_PARTITION devices
The requsted partition disk sector incorrectly has the parition start
sector added in twice for UCLASS_PARTITION devices. The efi_disk_rw_blocks()
routine adds the diskobj->offset to the requested lba. When the device
is a UCLASS_PARTITION, the dev_read() or dev_write() routine is called
which adds part-gpt_part_info.start. This causes I/O to the wrong sector.
Takahiro Akashi suggested removing the offset field from the efi_disk_obj
structure since disk-uclass.c handles the partition start biasing. Device
types other than UCLASS_PARTITION set the diskobj->offset field to zero
which makes the field unnecessary. This change removes the offset field
from the structure and removes all references from the code which is
isolated to the lib/efi_loader/efi_disk.c module.
This change also adds a test for the EFI ReadBlocks() API in the EFI
selftest code. There is already a test for reading a FAT file. The new
test uses ReadBlocks() to read the same "disk" block and compare it to
the data read from the file system API.
Signed-Off-by: Paul Barbieri <plb365@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 2 Jul 2022 12:07:48 +0000 (14:07 +0200)]
disk: honor CONFIG_SYS_64BIT_LBA
Without the patch for qemu-x86_defconfig:
* sizeof(lbaint_t) = 4 in dev_read()
* sizeof(lbaint_t) = 8 in blkcache_read()
CONFIG_SYS_64BIT_LBA is defined in common.h via
include/configs/x86-common.h:22.
We have to include common.h before including blk.h.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Joel Stanley [Mon, 20 Jun 2022 07:01:17 +0000 (16:31 +0930)]
image: fit: Use stack allocation macro
The documentation above the DEFINE_ALIGN_BUFFER says it's for use
outside functions, but we're inside one.
Instead use ALLOC_CACHE_ALIGN_BUFFER, the stack based macro, which also
includes the cache alignment.
Fixes:
b583348ca8c8 ("image: fit: Align hash output buffers")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Tested-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Michael Trimarchi [Wed, 29 Jun 2022 15:57:51 +0000 (17:57 +0200)]
MAINTAINERS: Add Dario and Michael as NAND maintainers
Both of us are working on NAND subsystem on several architectures and
we have boards and projects to improve the subsystem in uboot. The idea
is to guarantee quick feedback on patches sent on mailing list and most
of the time the possibilities to test them.
Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Tom Rini <trini@konsulko.com>
Hannes Schmelzer [Wed, 29 Jun 2022 10:11:40 +0000 (12:11 +0200)]
board/BuR/*: replace maintainer of BuR boards
Since I'm leaving the company with end of June, the maintainership will
be transferred to Wolfgang Wallner.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tom Rini [Fri, 1 Jul 2022 19:55:54 +0000 (15:55 -0400)]
chameleonv3: Add MAINTAINERS file
This file was missing, add.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 1 Jul 2022 13:14:32 +0000 (09:14 -0400)]
Merge commit '
ef5ba2cef4a08b68caaa9215fcac142d3025bbf7' of https://github.com/tienfong/uboot_mainline
Tom Rini [Fri, 1 Jul 2022 13:13:58 +0000 (09:13 -0400)]
Merge tag 'u-boot-amlogic-
20220701' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- search dtb for meson-axg-usb-ctrl on board axg
Teik Heng Chong [Wed, 29 Jun 2022 05:51:50 +0000 (13:51 +0800)]
drivers: clk: Update license for Intel N5X device
All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel,
update the license to use both GPL2.0 and BSD-3 Clause because this
copy of code may used for open source and internal project.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:26 +0000 (12:47 +0200)]
socfpga: arria10: Allow dcache_enable before relocation
Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).
Since commit
503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:25 +0000 (12:47 +0200)]
socfpga: arria10: Wait for fifo empty after writing bitstream
For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:24 +0000 (12:47 +0200)]
socfpga: arria10: Improve bitstream loading speed
Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):
* Change the size of the first fs read, so that all the subsequent
reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
This value was chosen so that in subsequent reads the fat fs driver
doesn't have to allocate a temporary buffer in get_contents
(assuming 8KiB clusters).
* Change the buffer size to a larger value when reading to ddr
(but not too large, because large transfers cause a stack overflow
in the dwmmc driver).
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:23 +0000 (12:47 +0200)]
socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:22 +0000 (12:47 +0200)]
sysreset: socfpga: Use parent device for reading base address
This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:21 +0000 (12:47 +0200)]
misc: atsha204a: Increase wake delay by tWHI
From the ATSHA204A datasheet (document DS40002025A):
Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.
tWHI value can be found in table 7-2.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:20 +0000 (12:47 +0200)]
config: Add Chameleonv3 config
Add defconfig and Kconfig files for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:19 +0000 (12:47 +0200)]
board: Add Chameleonv3 board dir
Add board directory for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:18 +0000 (12:47 +0200)]
arm: dts: Add Chameleonv3 devicetrees
Add devicetrees for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:17 +0000 (12:47 +0200)]
arm: dts: Add Chameleonv3 handoff headers
Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Fri, 17 Jun 2022 10:47:16 +0000 (12:47 +0200)]
arm: dts: Add Mercury+ AA1 devicetrees
Devicetree headers for Mercury+ AA1 module
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 1 Jul 2022 02:36:41 +0000 (22:36 -0400)]
Merge tag 'u-boot-rockchip-
20220630' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Fix for rk3328 nonopi-r2s boot env;
- Fix for rk8xx pmic boot on power plug-in;
- Fix for tee.bin support in fit image;
- rk3288 board dts update or fix;
- Some rk3399 board fix;
Tom Rini [Thu, 30 Jun 2022 19:21:52 +0000 (15:21 -0400)]
Merge tag 'u-boot-at91-2022.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2022.10 cycle:
This feature set includes mostly fixes and alignments: DT alignment with
Linux for sama7g5, removal of invalid eeprom compatibles, removal of
extra debug_uart_init calls for all at91 boards, support for pio4 driver
pioE bank, and other minor fixes and enhancements for sam9x60 and
sama5d2_icp boards.
Tom Rini [Thu, 30 Jun 2022 13:32:15 +0000 (09:32 -0400)]
Merge tag 'versal-qspi-for-v2022.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Versal QSPI/OSPI changes for v2022.10
- Add new flash types
- Add cadence ospi driver for Xilinx Versal
Mihai Sain [Wed, 25 May 2022 10:32:08 +0000 (13:32 +0300)]
gpio: atmel_pio4: add support for PIO_PORTE
Add support for gpio PORT E, which is available on e.g. sama7g5 SoC.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Tom Rini [Wed, 29 Jun 2022 13:54:02 +0000 (09:54 -0400)]
Merge branch '2022-06-28-Kconfig-migrations' into next
- Convert a large number of CONFIG symbols to Kconfig. Of note is a
large chunk of USB symbols (and dead code removal), ensuring all
SPL/TPL/VPL symbols have an appropriate dependency, largely (but not
entirely) removing the testing of CONFIG_SPL_BUILD in board headers,
and allowing CONFIG_EXTRA_ENV_TEXT and CONFIG_EXTRA_ENV_SETTINGS to
co-exist as this facilities migration of many platforms.
T Karthik Reddy [Thu, 12 May 2022 10:05:35 +0000 (04:05 -0600)]
spi: cadence-qspi: Fix programming ospi flash speed
When the requested flash speed is 0, the baudrate division for the
requested speed causing drop in the performance. So set the ospi flash
to operate at max frequency when requested speed is zero.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-6-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
T Karthik Reddy [Thu, 12 May 2022 10:05:34 +0000 (04:05 -0600)]
spi: cadence_qspi: Enable apb linear mode for apb read & write operations
On versal platform, enable apb linear mode for apb read and write
execute operations amd disable it when using dma reads. This is done by
xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled,
else we use direct raw reads and writes in case of mini U-Boot.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
T Karthik Reddy [Thu, 12 May 2022 10:05:33 +0000 (04:05 -0600)]
spi: cadence-qspi: reset qspi flash for versal platform
When flash operated at non default mode like DDR, flash need to be reset
to operate in SDR mode to read flash ids by spi-nor framework. Reset the
flash to the default state before using the flash. This reset is handled
by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we
do raw read and write access by the registers.
Versal platform utilizes spi calibration for read delay programming, so
incase by default read delay property is set in DT. We make sure not to
use read delay from DT by overwriting read_delay with -1.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
T Karthik Reddy [Thu, 12 May 2022 10:05:32 +0000 (04:05 -0600)]
arm64: versal: Add versal specific cadence ospi driver
Add support for cadence ospi driver for Versal platform. This driver
provides support for DMA read operation which utilizes cadence qspi
driver.
If "cdns,is-dma" DT property is specified use dma for read operation
from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in
cadence_ospi_versal driver add a weak function defination in
cadence_qspi driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
T Karthik Reddy [Thu, 12 May 2022 10:05:31 +0000 (04:05 -0600)]
spi: cadence-qspi: move cadence qspi macros to header file
Move all the cadence macros from cadence_qspi_apb.c to cadence_qspi.h
file.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-2-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Wed, 25 May 2022 05:17:12 +0000 (10:47 +0530)]
mtd: spi-nor-ids: Add support for flashes tested by xilinx
Add support for various flashes from below manufacturers which are tested
by xilinx for years.
EON:
en25q128b
GIGA:
gd25lx256e
ISSI:
is25lp008
is25lp016
is25lp01g
is25wp008
is25wp016
is25wp01g
is25wx256
MACRONIX:
mx25u51245f
mx66u1g45g
mx66l2g45g
MICRON:
mt35xl512aba
mt35xu01g
SPANSION:
s70fs01gs_256k
SST:
sst26wf016b
WINBOND:
w25q16dw
w25q16jv
w25q512jv
w25q32bv
w25h02jv
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Andrea Scian [Tue, 21 Jun 2022 20:05:10 +0000 (22:05 +0200)]
mtd: mxs_nand_spl: fix nand_command protocol violation
mxs_nand_command() implementation assume that it's working with a
LP NAND, which is a common case nowadays and thus uses two bytes
for column address.
However this is wrong for NAND_CMD_READID and NAND_CMD_PARAM, which
expects only one byte of column address, even for LP NANDs.
This leads to ONFI detection problem with some NAND manufacturer (like
Winbond) but not with others (like Samsung and Spansion)
We fix this with a simple workaround to avoid the 2nd byte column address
for those two commands.
Also align the code with nand_base to support 16 bit devices.
Tested on an iMX6SX device with:
* Winbond W29N04GVSIAA
* Spansion S34ML04G100TF100
* Samsung K9F4G08U00
Tested on imx8mn device with:
* Windbond W29N04GV
Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
CC: Stefano Babic <sbabic@denx.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Peter Robinson [Sun, 12 Jun 2022 14:25:29 +0000 (15:25 +0100)]
rockchip: pinebook-pro: sync PBP dtb to 5.18
Sync the pinebook pro to upstream 5.18, in particular this brings
brings in a fix so the DP is disabled so Linux will actually boot.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Sun, 12 Jun 2022 13:52:25 +0000 (14:52 +0100)]
rockchip: rockpro64: enable leds
The Rockpro64 has some GPIO leds so let's enable them so the
user gets some output in early boot.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Sun, 12 Jun 2022 13:47:14 +0000 (14:47 +0100)]
rockchip: pinebook-pro: minor SPI flash fixes
Set a default offset for environment so it doesn't write it to
unexpected locations, drop unneeded mtd config option.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Fri, 27 May 2022 18:18:20 +0000 (13:18 -0500)]
rockchip: Add option to prevent booting on power plug-in
For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.
This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.
This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/
20220121133732.2397273-1-andre.przywara@arm.com/
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Chris Morgan [Fri, 27 May 2022 18:18:19 +0000 (13:18 -0500)]
power: pmic: rk8xx: Support sysreset shutdown method
Add support for sysreset shutdown for this PMIC. The values were pulled
from the various datasheets, but for now it has only been tested on
the rk817 (for an Odroid Go Advance).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jerome Forissier [Wed, 11 May 2022 15:35:14 +0000 (17:35 +0200)]
mach-rockchip: make_fit_atf.py: support OP-TEE tee.bin v1 format
This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip
platforms.
Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format
in addition to the ELF data. They are essential information for proper
initialization of the TEE core, such as the size of the memory region
covered by the TEE or a compact representation of runtime relocation
data when ASLR is enabled.
With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin'
MUST be used instead. Ignoring this recommendation can lead to crashes
as described in [3].
Link: [1] https://github.com/OP-TEE/optee_os/commit/
5dd1570ac5b0f6563b1a9c074533a19107b8222d
Link: [2] https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-L302
Link: [3] https://github.com/OP-TEE/optee_os/issues/4542
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>