r600/sfn: Rework query for indirect access in alu instr and opt

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>

r600/sfn: Add address and index registers creation to ValueFactory

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>

r600/sfn/tests: Cleanup and move some code around

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>

r600/sfn: Handle MOVA_INT in sfn assembler

To properly emit ALU clauses we have to make sure the backend doesn't
add instructions for the address emission.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>

r600/sfn: don't track address registers in live ranges

There is only one address register, and for the index registers we
don't do a special register allocation, so no need to track these
either.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>

r600/sfn: Add a type for address registers

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>

pvr: Fully declare support for VK_EXT_private_data

Fixes: dEQP-VK.api.info.get_physical_device_properties2.features
  .private_data_features

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22738>

pvr: Fix static assert check

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22595>

pvr: Change push_constants_shader_stages to type pvr_stage_allocation

Previously the code was saving the mask as a VkShaderStageFlags
but when allocating shareds it checked against pvr_stage_allocation.
This causes problems as only the vertex bit matches the
VkShaderStageFlagBits so the push constants utilized in fragment
shaders weren't picked up properly.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22731>

pvr: Fix pvr_csb_bake() list return.

The list logic checks for list->next->next (+ some other checks)
to point to the list itself to determine that there is just one
single element.

 ┌───────────────────────┐
 └< { HEAD } >─< { E0 } >┘

When the list_head is copied as was being done previously, the
list element's next pointer still points at the old head so
the `list_is_singular()` check fails.

Fixes pvr_cmd_buffer.c:605:`list_is_singular(&bo_list)` assertion
dEQP-VK.api.image_g.core.clear_color_attachment.cube_layers.b8g8r8a8_unorm

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22730>

docs: Add INTEL_DEBUG_BATCH_FRAME_START/_STOP

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>

iris: Enable INTEL_DEBUG_BATCH_FRAME_START/_STOP

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>

anv: Enable INTEL_DEBUG_BATCH_FRAME_START/_STOP

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>

intel/debug: Control start/stop frame of batch debug

When using INTEL_DEBUG=bat, INTEL_DEBUG_BATCH_FRAME_START and
INTEL_DEBUG_BATCH_FRAME_STOP can limit dumping of batches for
particular frame ranges. Batch dumps are huge. Smart filtering
allows debugging of single frames during game play. Initial
commit to debug infrastructure.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>

aco: allow no export instruction for gfx10+ fs

radeonsi will generate no export instruction when no
discard and no output.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22727>

aco: get scratch addr from symbol for radeonsi

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22727>

aco,radv: support symbol relocation in aco

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22727>

dzn: Expose core VK1.2 extensions that aren't optional

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22745>

dzn: Expose core VK1.1 extensions that aren't optional

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22745>

clc: Add clang frontendhlsl module to fix build of  microsoft-clc with llvm 16+

Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22741>

clc: Add clangASTMatchers to fix static llvm build of  microsoft-clc with LLVM 16+

Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22741>

compiler/clc: Fix embedded clang headers (microsoft-clc)  for LLVM 16+

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7742

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22741>

v3d: fix tfu_supports_tex_format() param type, and document why

tex_format should be `enum V3DX(Texture_Data_Formats)`, but using that enum
type in the header requires including `v3dx_pack.h`, which triggers circular
include dependencies issues, so use a `uint32_t` for now.

"fix" the one place that was using the correct enum, because doing so
triggers `-Wenum-int-mismatch` in GCC 13 as the function declaration
doesn't match the function definition.

Reported-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22739>

ir3: documents (ss) flag for cat7 instructions

Blob produces "lock" instructions with (ss), so our past guess that
cat7 supports (ss) is true.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>

ir3/a7xx: Add definitions for (last) src GPR attribute

A new attribute on source GPRs reflecting if a certain usage of a
value is the last usage of it was added in A7xx. This is seemingly
a performance hint and doesn't affect anything when not applied.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>

ir3/a7xx: Document "alias" instruction

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>

ir3: Document that stc has higher DST upper bound than we defined

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>

ir3/a7xx: Add STSC definition

STore Shared Const - loads SIZE dwords from HLSQ_SHARED_CONSTS_IMM
starting from HLSQ_SHARED_CONSTS_IMM[SRC] and writing them to c[DST]

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>

ir3/a7xx: Add new form of stg.a/ldg.a addressing

The new stg.a/ldg.a addressing form supersedes the a6xx's one.

The new form is:
 ldg.a.f32 r4.y, g[c0.z+r4.y+2], 4

There are no shift comparing to the a6xx:
 ldg.a.f32 r4.y, g[r0.z+(r4.y)<<2], 4

Also on a7xx the first src is allowed to be both const and gpr.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>

ir3/a7xx: Add new lock/unlock CS instructions

Seen at the end of every compuite shader:

 %shader_assmebly%
 lock
 unlock
 end

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>

ir3/a7xx: NOPs may have some no-op bits set

[00000001x_00000000x] nop ; dontcare bits in nop: 0000000100000000
[00000002x_00000000x] nop ; dontcare bits in nop: 0000000200000000

Doesn't seem to make them different from ordinary nops.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>

freedreno: Early exit in device matching if id doesn't have chip_id

Assert was wrong and caused issues when there are devices defined
after devices that are matched by chip_id.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>

intel/fs: fix per vertex input clamping

Only apply the clamp in multi patch mode (where the input vertices
vary between [1, 32]).

The clamp NIR pass operates on lowered intrinsics so we need to call
it after the inputs have been lowered.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e25e17dd0c ("intel/fs: clamp per vertex input accesses to patchControlPoints")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8912
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22701>

draw: fix robust ubo size calc

if the size of the constant buffer + stride overflows UINT32_MAX,
DIV_ROUND_UP will return 0, which is, in some sense, extremely robust,
but for general functionality it's not actually very robust

cc: mesa-stable

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22720>

dri/android: Fix MSAA resolve

Commit f9a074dd550 ("dri2/android: Bypass throttling") dropped
unnecessary throtting in the SwapBuffers() path for android.  But
unfortunately MSAA resolve got tangled up in the throttle reason
flag.  So add a new flag that indicates "no throttingling, but yes
please do MSAA resolve".

Fixes: f9a074dd550 ("dri2/android: Bypass throttling")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22719>

zink: set when pipeline dirty flag when multisample changes

Sets `gfx_pipeline_state.dirty` appropriately when
`gfx_pipeline_state.multisample` changes

Fixes: 14d58926099 ("zink: add to multisample field to `zink_gfx_pipeline_state`")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22736>

tgsi: use locale independent float and double parsing

The atof and strtod functions use the locale of the user when
determining if a decimal is a comma, ',' or a period, '.'. Thanks to
@fzwoch for helping find the cause of a shader-related issue.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5760
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22699>

util: check and initialize locale before using it

Cc: mesa-stable
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22699>

mesa/main: rework locale setup/teardown

Cc: mesa-stable
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22699>

frontends/va: define va av1 encoding caps

by having va av1 caps enabled, av1 vaapi encoding
is enabled.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: use PIPE_ENC_FEATURE enum

Merge PIPE_H265_ENC_FEATURE into PIPE_ENC_FEATURE enum
because those are common flags, and it will be
used in AV1 encoder as well.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

frontends/va: adding va av1 encoding functions

supported features:
- 8/10 bit encoding
- multi-layer (up to 4) encoding
- vbr/cbr rate control mode

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: add av1 encoding ib packages and get_info

add av1 encoding ib packages and enable the
get_info functions.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: add some av1 encoding function

preparation for enabling av1 encoding in radeonsi,
adding the entropy related functioin.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: add av1 enc data structure

add av1 encoding related data structure.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

gallium/pipe: add av1 encoding data structure in pipe

add pipe av1 encoding data structure

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: add av1 dpb variables and cdf table

add av1 dpb variables and cdf table.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: remove extra zero bytes from bitstream

reason:
   extra bytes are not needed and not necessary
   in h264/h265 bitstreams, because they are in
   between NALs, the only problem is they consumed
   extra bits. And for av1 streams, that could be
   explained to something else, especially in
   multi-layer cases, that can cause syntax errors.

   ptr[6] represents the bitstream size,
   ptr[8] represents the extra zero bytes.

   The total number of bytes of the output
   should be ptr[6] - ptr[8]

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: merge get_output_format_param function

reason:
so far, the output_format_param function can be shared
by different encoders, and just for h264 encoder, there
is no 10bit encoding supported. This is to reduce
the repeated code before having av1 encoder.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: enable swizzle mode in encoding ref frames.

swizzle mode in ref frames could potentially
improve encoding performance, the main reason
is just because linear mapping is the worst mode
for reference frames comparing to block level
mapping.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: enable 2 pass search center map

2 pass search map is a feature supported by VCN,
the main purpose is to enlarge motion search
range that in pre-encoding path the center global
motion vectors could be obtained and used in the
final path as a block center base. When 2pass is
used, this feature will be automatically enabled.

2 pass feature can be enabled by ffmpeg command
line "-compression_level 1"

and also correct some typos and move quality
package from vcn3.0 to vcn2.0 since it is availabe
in vcn2.0 and vcn3.0 can use it directly. Correct
vcn3.0 hevc spec misc IB package.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

radeonsi/vcn: add macros used in av1 encoding

add macros used in av1 encoding.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>

aco: don't move exec writes around exec writes

Not sure if this is possible, but we should avoid it anyway.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22714>

anv: Take into consideration physical device max heap size to set maxStorageBufferRange

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22721>

pvr: drop unused variable

Fixes: 71fe789d354d ("pvr: Support ipf_creq_pf in pvr_isp_ctrl_stream()")

Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22709>

mesa: remove unused bools

ShareGroupReset and DisjointOperation where only set in the code
removed in the previous commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>

mesa: don't share reset status across contexts

If Driver.GetGraphicsResetStatus exists for one context, other contexts
will be able to use it; so there's no need to inherit reset status from
the other contexts.

This also prevented implementing the spec correctly: we're supposed to
report GL_NO_ERROR when the reset is completed (after reporting GL_*_RESET
at least once):

    If a reset status other than NO_ERROR is returned and subsequent
    calls return NO_ERROR, the context reset was encountered and
    completed. If a reset status is repeatedly returned, the context may
    be in the process of resetting.

With the existing code, the contexts will report INNOCENT_CONTEXT_RESET
forever.

Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>

winsys/amdgpu: use the no-op helper to detect if reset completion

On older kernel the completion of the reset isn't signalled to userspace,
yet we need it to implement the EXT_robustness extension correctly.

In this situation, try to create a new context and submit a no-op job. If
the reset isn't done the kernel will reject the submission (-ECANCELED);
otherwise the submission will go through and we'll know that the reset is
done.

Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>

winsys/amdgpu: add a helper function to submit a no-op job

This will be used in the next commit.

Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>

radeonsi: stop reporting reset to app once gpu recovery is done

This way apps know they can recreate their contexts when
the status go back to NO_ERROR.

This depends on new UAPI in the kernel; for older kernel, radeonsi
will stop reporting a reset after 3 seconds. Apps will be able to
create new contexts but they'll have to handle not being able to
submit tasks.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7460
Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>

amd: update amdgpu_drm.h

Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>

ac/rgp: update SQTT_FILE_CHUNK_TYPE_ASIC_INFO to minor version 5

To match PAL. I don't know what the active_pixel_packer_mask field
is used for.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22677>

ac/rgp: update SQTT_FILE_CHUNK_TYPE_API_INFO to minor version 2

To match PAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22677>

ac/sqtt: add missing EventUnknown to rgp_sqtt_marker_event_type

To match XGL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22677>

ac/sqtt: add new bits to rgp_sqtt_marker_barrier_end

To match XGL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22677>

radv/sqtt: add support for queue info

RGP uses that to report the various queue timings info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>

radv/sqtt: sample CPU/GPU clocks before starting the trace

RGP seems to use that to calibrate timestamps. This also introduces
a new helper to reset thread data between captures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>

ac/sqtt: initialize clock calibration/queue info/queue event records

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>

ac/sqtt: add helpers for initializing ac_thread_trace_data

This is common between RADV and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>

ac/sqtt: add a helper for adding clock calibration records

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>

wgl: Remove needless `if (1) { ... }`.

Noticed by Craig Scott on https://gitlab.freedesktop.org/mesa/mesa/-/issues/4427#note_857876

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22706>

wgl: Fix unintentional assignment on assert.

Spotted by Nanley Chery.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4427
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22706>

anv: enable shaderUniformBufferArrayNonUniformIndexing

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>

anv: fix anv_nir_lower_ubo_loads pass

In order to use load_global_const_block_intel we need to ensure the
64bit address in src[0] is uniform. This is not the case in the
vkd3d-proton test_bindless_cbv tests for example.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>

nir/divergence: add missing load_global_constant_* intrinsics

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>

broadcom/compiler: try harder to merge thread switch earlier

We have been stopping as soon as we find a conflict but that doesn't
mean we can't merge it in an earlier slot, so keep going. Going by
shader-db, this sometimes allows us to merge the final thrsw a bit
earlier and avoid emitting NOP instructions at the program end to
make up for its delay slots. I have not observed cases where this
helps with regular thrsw though, but it doesn't hurt to try with
those too.

total instructions in shared programs: 11526876 -> 11526354 (<.01%)
instructions in affected programs: 10760 -> 10238 (-4.85%)
helped: 236
HURT: 0
Instructions are helped.

total max-temps in shared programs: 2231705 -> 2231677 (<.01%)
max-temps in affected programs: 276 -> 248 (-10.14%)
helped: 27
HURT: 0
Max-temps are helped.

total inst-and-stalls in shared programs: 11545177 -> 11544655 (<.01%)
inst-and-stalls in affected programs: 10777 -> 10255 (-4.84%)
helped: 236
HURT: 0
Inst-and-stalls are helped.

total nops in shared programs: 321624 -> 321152 (-0.15%)
nops in affected programs: 751 -> 279 (-62.85%)
helped: 236
HURT: 0
Nops are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22679>

radv/sqtt: Add RGP Markers for Mesh Shaders

This change updates the sqtt layer to add mesh shader specific RGP
instrumentation logic. This should allow RGP to correctly identify GPU
work derived from vkCmdDrawMeshTasksEXT, vkCmdDrawMeshTasksIndirectEXT,
and vkCmdDrawMeshTasksIndirectCountEXT API calls.

This change also updates the mesa-to-RGP shader stage translation logic
to handle the mesh & task stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21917>

ac/sqtt: Add RGP Definitions for Mesh Shaders

This commit adds RGP marker definitions for the following mesh shader
functions:

- vkCmdDrawMeshTasksEXT
- vkCmdDrawMeshTasksIndirectCountEXT
- vkCmdDrawMeshTasksIndirectEXT

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21917>

ac/spm: rename ac_spm_trace_data to ac_spm

This is shorter and it's the main struct that controls SPM, while
ac_spm_trace contains the generated data only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22707>

ac/spm: introduce ac_spm_trace and ac_spm_get_trace()

For more code isolation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22707>

radv: only enable extendedDynamicState3ConservativeRasterizationMode on GFX9+

If extendedDynamicState3ConservativeRasterizationMode is enabled,
VK_EXT_conservative_rasterization is mandatory.

Fixes recent updates in dEQP-VK.info.device_mandatory_features.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22681>

nir: clean up white-space in deref-printing

Without this, we get some trailing spaces in some cases, and some
double space in some other cases. Let's clean that up a bit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22550>

radv/video: start adding gfx11 vcn decoder

On gfx11 the vcn decoder moved into the vcn encoder ring,
now known as the unified vcn ring.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>

radv/video: fix dpb surface programming

This just programs the dpb fields directly from the image surface.

Makes things happier on navi33

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>

radv/video: add a video addr gfx mode

This will be different on gfx11+ so add a settable field for it

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>

radv/winsys: handle encoder queue padding/submits.

The encoder queue doesn't like padding at all, don't pad in the sysmem
paths for encoder queue.

The encoder queue will be using on gfx11 for decoding.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>

radv: set a video decode ip block in physical device.

This makes it easier to add navi 3x

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>

radv/video: add missing gfx family

This is compatible with rdna2 but was just missing.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>

radeonsi/ac: move some vcn defines to common

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>

zink: enable EXT_shader_object for generic precompiles

this should match the functionality of GPL, but it should also (theoretically)
have significantly less CPU overhead, so I've enabled this to be the new
default when available

currently I'm not changing any of the requirements for shader object enablement,
so this is probably only be usable on desktops

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: make zink_shader_spirv_compile public

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: use zink_shader_object for pipeline compiles from zink_gfx_program

this matches up the rest of the codebase using zink_shader_object

zink_gfx_program::objects is left in place for shader binding so that
the entire array can always be bound in one call

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: add a union to zink_gfx_pipeline_cache_entry for gpl

just code motion for now

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: avoid accessing zink_gfx_program::modules during pipeline compile

this allows a different array of modules to be passed in

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: allow zink_shader_module to be either a shobj or a mod using a bool

this allows shader modules to more accurately represent the contents of
the zink_shader_object for which they are containers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: store spirv onto zink_shader_object structs

this makes it convenient for reuse

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: use zink_destroy_shader_module() for compute to deduplicate code

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: use zink_shader_object for zink_shader_module

this streamlines a bit more code, though nothing changes functionally

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: delete redundant conditional

this is checked literally 2 lines above

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>

zink: deduplicate separable program replacement handling

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22725>