Elmar Albert [Wed, 6 Apr 2022 11:39:50 +0000 (13:39 +0200)]
clk: imx8mp: Add ECSPI clocks
Add clock tables required for bing up ECSPI interfaces
Signed-off-by: Elmar Albert <ealbert@data-modul.com>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Signed-off-by: Elmar Albert <ealbert@data-modul.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Heiko Thiery [Fri, 18 Feb 2022 20:48:42 +0000 (21:48 +0100)]
include: configs: *imx8*: remove IMX_FEC_BASE
The IMX_FEC_BASE value is not used when CONFIG_DM_ETH is configured. So this
value can be removed.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-By: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Heiko Thiery [Wed, 16 Feb 2022 12:25:15 +0000 (13:25 +0100)]
kontron-pitx-imx8m: change environment address variables
Currently the space between kernel_addr_r and the fdt_addr_r is only 32MB.
To have enought space to load kernel images bigger than 32MB change the
variables to a feasible value.
The new environment variables layout is based on the scheme from
"include/configs/ti_armv7_common.h".
The CONFIG_SYS_LOAD_ADDR value is set to 0x42000000. With that we have
the same value as for the kernel_addr_r.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Marek Vasut [Fri, 8 Apr 2022 00:15:01 +0000 (02:15 +0200)]
ARM: dts: imx8mm: Add i.MX8M Mini Toradex Verdin based Menlo board
Add new board based on the Toradex Verdin iMX8M Mini SoM, the MX8Menlo.
The board is a compatible replacement for i.MX53 M53Menlo and features
USB, multiple UARTs, ethernet, LEDs, SD and eMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Jesse Taube [Thu, 17 Mar 2022 18:33:21 +0000 (14:33 -0400)]
board: freescale: imxrt10..-evk: Fix missing include of serial.h
If FALCON mode is enabled we have a missing include in spl_start_uboot.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Jesse Taube [Thu, 17 Mar 2022 18:33:20 +0000 (14:33 -0400)]
ARM: dts: imxrt10..-evk: Linux moved pins-imxrt1020 to dts
The Linux kernel moved dt-bindings/pinctrl/pins-imxrt to the device tree
This patch move it in U-Boot as well.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Jesse Taube [Thu, 17 Mar 2022 18:33:19 +0000 (14:33 -0400)]
configs/*imxrt10*: SYS_MALLOC_LEN is too large
1M of heap is more than internal ram making booting without SDRAM not
possible now it is 256k
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Jesse Taube [Thu, 17 Mar 2022 18:33:18 +0000 (14:33 -0400)]
clk: imxrt: Use dts for anatop base address
In Linux IMX and IMXRT use the device tree to hold the anatop address.
The anatop is used in clock drivers as it controls the internal PLLs
This will move the macro from asm/arch-imxrt to the device tree.
This presumably should also be done with the other IMX boards as well.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Marek Vasut [Thu, 10 Mar 2022 20:27:04 +0000 (21:27 +0100)]
mmc: fsl_esdhc_imx: Add i.MX8MP compatible string
Add compatible string for i.MX8MP, which permits i.MX8MP to use
HS400ES mode, just like all the other i.MX8M.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Haibo Chen <haibo.chen@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Wed, 9 Mar 2022 16:09:45 +0000 (17:09 +0100)]
ARM: imx: romapi: Repair FlexSPI NOR boot offset
The FlexSPI NOR boot offset does not require any special handling,
the image_offset is correct in either case (0x1000 for FlexSPI NOR
and 0x8000 for SD/eMMC) and the offset of u-boot.itb from the start
of flash.bin is always 0x58000 on MX8MN/MX8MP, which matches the
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000 in case
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300, which is always the
case on MX8MN/MX8MP.
The CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is really overloaded in
case of the MX8MN/MX8MP, but fixing that needs additional plumbing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut [Wed, 9 Mar 2022 03:19:34 +0000 (04:19 +0100)]
ARM: dts: imx: Add flexspi node to i.MX8MP
Add flexspi DT node matching Linux kernel as of commit
d7cd74466651e ("arm64: dts: imx8mp: Reorder flexspi clock-names entry")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Wed, 9 Mar 2022 03:18:57 +0000 (04:18 +0100)]
spi: nxp_fspi: Add i.MX8MP compatible string
The i.MX8M Mini and i.MX8M Plus flexspi IPs are compatible with one
another, however the linux kernel DT uses separate compatible string
for each SoC. Add the missing i.MX8MP compatible into this driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tim Harvey [Tue, 8 Mar 2022 18:47:44 +0000 (10:47 -0800)]
board: gateworks venice: add support for GPY111 phy
The TI DP83867 phy has been replaced with the MaxLinear GPY111 phy due
to part availability.
Add support for it by adding LED config and dt-prop based internal delay
config tx-delay/rx-delay per PHY ID.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Tim Harvey [Tue, 8 Mar 2022 18:45:39 +0000 (10:45 -0800)]
board: venice: add spl_board_loader_name
Implement spl_board_loader_name to provide more meaningful device names
vs MMC1 and MMC2.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Tue, 8 Mar 2022 18:44:43 +0000 (10:44 -0800)]
imx8m{m,n}-venice-gw7902: add GSC ADC rail for VDD_5P0
The GW7902-C revision adds an ADC for the VDD_5P0 voltage rail.
Add register definitions for it.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Tim Harvey [Fri, 18 Feb 2022 23:20:17 +0000 (15:20 -0800)]
imx8m{m,n}_venice: update boot_net script to load fdt
Update the 'boot_net' script to load the fdt with the kernel.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Heinrich Schuchardt [Mon, 11 Apr 2022 09:45:29 +0000 (11:45 +0200)]
ARM: renesas: reduce rcar3_salvator-x image size
rcar3_salvator-x u-boot.img is very close to the 0x100000 size limit.
Enable linked time optimization (LTO).
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Marek Vasut [Tue, 12 Apr 2022 15:26:01 +0000 (17:26 +0200)]
ARM: dts: imx: Add support for Data Modul i.MX8M Mini eDM SBC
Add support for Data Modul i.MX8M Mini eDM SBC board. This is an
evaluation board for various custom display units. Currently
supported are serial console, ethernet, eMMC, SD, SPI NOR,
USB host and USB OTG.
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Tue, 12 Apr 2022 16:05:39 +0000 (13:05 -0300)]
imx8mm-cl-iot-gate: Add redundand environment support
Add redundand environment support as it is required
by SWUpdate.
While at it, also adjust the CONFIG_ENV_OFFSET to a more appropriate
larger offset as done on other i.MX8M defconfigs.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Fabio Estevam [Tue, 12 Apr 2022 16:05:38 +0000 (13:05 -0300)]
imx8mm-cl-iot-gate: Retrieve the serial number from EEPROM
The serial number is located at offset 0x14 of the EEPROM
under i2c0 bus at address 0x54.
To print the serial number in Linux:
SERNUM=$(cat /proc/device-tree/serial-number)
echo $SERNUM
Signed-off-by: Fabio Estevam <festevam@denx.de>
Fabio Estevam [Tue, 12 Apr 2022 16:05:37 +0000 (13:05 -0300)]
imx8mm-cl-iot-gate: Retrieve the MAC address from EEPROM
Currently the eth0 MAC address is randomly assigned.
Retrieve the MAC address from EEPROM.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Fabio Estevam [Tue, 12 Apr 2022 16:05:36 +0000 (13:05 -0300)]
imx8mm-cl-iot-gate: Retrieve the DDR type from EEPROM
Currently, the DDR type is retrieved by iteracting inside an array
of possible DDR types.
This may take saveral attempts, which slows the overall U-Boot process
and does not provide a good user experience:
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000)
DDRINFO: Cfg attempt: [ 1/6 ]
DDRINFO(M): mr5-8 [ 0xff000010 ]
DDRINFO(T): mr5-8 [ 0x5000010 ]
resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000)
DDRINFO: Cfg attempt: [ 2/6 ]
DDRINFO(M): mr5-8 [ 0xff000010 ]
DDRINFO(T): mr5-8 [ 0x1061010 ]
resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000)
DDRINFO: Cfg attempt: [ 3/6 ]
DDRINFO(M): mr5-8 [ 0xff000010 ]
DDRINFO(T): mr5-8 [ 0xff000010 ]
Normal Boot
WDT: Not starting
Trying to boot from MMC2
NOTICE: BL31: v2.5(release):v2.5
NOTICE: BL31: Built : 07:12:44, Jan 24 2022
Improve the boot time by retrieving the correct DDR information from
the EEPROM:
U-Boot SPL 2022.04-rc4-00045-g6d02bc40d58c (Mar 19 2022 - 08:22:29 -0300)
DDRINFO(D): Kingston 4096G
DDRINFO(M): mr5-8 [ 0xff000010 ]
DDRINFO(E): mr5-8 [ 0xff000010 ]
Normal Boot
WDT: Started watchdog@
30280000 with servicing (60s timeout)
Trying to boot from MMC2
NOTICE: BL31: v2.5(release):v2.5
NOTICE: BL31: Built : 22:28:11, Mar 15 2022
Based on the original code from Compulab's U-Boot.
Tested on a imx8mm-cl-iot-gate board populated with 4GB of RAM.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Fabio Estevam [Tue, 12 Apr 2022 16:05:35 +0000 (13:05 -0300)]
imx8mm-cl-iot-gate: Add SPL EEPROM support
imx8mm-cl-iot-gate supports multiple DDR sizes and models.
The DDR type can be retrieved from the EEPROM, so add SPL code
that can be used to get the DDR information.
Based on the original code from Compulab's U-Boot.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Ariel D'Alessandro [Tue, 12 Apr 2022 13:31:38 +0000 (10:31 -0300)]
bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
Introduce BSH SystemMaster (SMM) S2 board family, which consists of:
iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards.
Add support for iMX8MN BSH SMM S2 board:
- 256 MiB DDR3 RAM
- 512MiB Nand
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet
Add support for iMX8MN BSH SMM S2 PRO board:
- 512 MiB DDR3 RAM
- 8 GiB eMMC
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Michael Trimarchi [Tue, 12 Apr 2022 13:31:37 +0000 (10:31 -0300)]
net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver
Add driver for the NXP TJA1100 and TJA1101 PHYs. These PHYs are special
BroadRReach 100BaseT1 PHYs used in automotive.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Ariel D'Alessandro [Tue, 12 Apr 2022 13:31:36 +0000 (10:31 -0300)]
net: phy: Add phy_modify() accessor
Add read-modify-write unlocked accessor for accessing a PHY register.
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Ariel D'Alessandro [Tue, 12 Apr 2022 13:31:35 +0000 (10:31 -0300)]
iopoll: Extend read_poll_timeout macro to support variable parameters
This macro currently supports only one parameter. Based on Linux iopoll,
let's extend read_poll_timeout common API to allow multiple variable
parameters.
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Ariel D'Alessandro [Tue, 12 Apr 2022 13:31:34 +0000 (10:31 -0300)]
phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific
This driver supports NXP C45 TJA11XX PHYs, but there're also other NXP
TJA11XX PHYs. Let's rename functions in this driver to be c45 variant
specific, so further drivers can be introduced adding support for NXP
TJA11XX PHYs.
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Michael Trimarchi [Tue, 12 Apr 2022 13:31:33 +0000 (10:31 -0300)]
imx8m: add init_nand_clk
Add init_nand_clk to enable gpmi nand clock. Since i.MX8M not use CCF,
so we still use legacy mode to configure the clock.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Michael Trimarchi [Tue, 12 Apr 2022 13:31:32 +0000 (10:31 -0300)]
imx8m: add regs used by GPMI
Add regs used by GPMI
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Marek Vasut [Mon, 11 Apr 2022 20:39:44 +0000 (22:39 +0200)]
ARM: imx8mm: verdin-imx8mm: Drop superfluous header
The power/bd71837.h should no longer be included, since V1.1 SoM
uses only the PCA9450 PMIC and the BD71837 support was removed.
Drop the header too.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tommaso Merciai [Sat, 26 Mar 2022 11:19:08 +0000 (12:19 +0100)]
driver: pwm: pwm-imx: separe dm from non dm implementation
Separe dm implementation from non dm implementation of pwm-imx
driver using CONFIG_DM_PWM
Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Tommaso Merciai [Sat, 26 Mar 2022 11:19:05 +0000 (12:19 +0100)]
drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx
Move pwm_imx_get_parms, pwm_id_to_reg functions into pwm-imx.c
and drop off pwm-imx-util.c
Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Peng Fan [Mon, 11 Apr 2022 10:02:16 +0000 (18:02 +0800)]
imx: mx7dsabresd: enable DM_SERIAL
Enable CONFIG_DM_SERIAL, and `dm tree` could show:
serial 1 [ ] serial_mxc | |-- serial@
30a80000
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 10 Apr 2022 04:18:27 +0000 (12:18 +0800)]
imx8mq: soc: Set the BYPASS ID SWAP bit (GPR10 bit 1)
Set the BYPASS ID SWAP bit (GPR10 bit 1).
The ID SWAP function randomly make TZASC grant non-secure access to
secure memory. TZASC ID SWAP should be bypassed by setting the bit
TZASC_ID_SWAP_BYPASS(bit 1) in IOMUX_GPR10 register.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Marcel Ziswiler [Fri, 8 Apr 2022 10:28:21 +0000 (12:28 +0200)]
board: colibri-imx6ull: fix detecting sd card
Turns out on certain carrier boards (e.g. Iris V2) and under certain
circumstances (e.g. after a software reset) the SD card may have been
left in a strange state which later failed as follows:
Colibri iMX6ULL # mmc dev 0
Card did not respond to voltage select! : -110
Fix this as follows:
- Re-name the signaling voltage rail regulator from vmmc to vqmmc.
- Fix the name of the GPIO property to gpios.
- Specify 4-bit bus width, no write-protect capability and no 1.8
volt signaling voltage capability.
- Fix the clock vs. command pull-up vs. push-pull configuration.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marcel Ziswiler [Fri, 8 Apr 2022 10:28:15 +0000 (12:28 +0200)]
configs: colibri-imx6ull/-emmc: use micrel ksz8xxx phy driver
Use the Micrel KSZ8xxx specific Ethernet PHY driver rather than the
generic one.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marcel Ziswiler [Fri, 8 Apr 2022 10:27:41 +0000 (12:27 +0200)]
colibri-imx6ull: fix nand bch geometry
Fix NAND BCH geometry as otherwise the following errors are observed
upon boot:
...
Loading Environment from NAND... NAND read from offset 380000 failed -74
...
NAND read from offset 800 failed -74
...
ubi0 error: ubi_io_read: error -74 (ECC error) while reading 64 bytes
from PEB 0:0, read 64 bytes
...
Fixes:
ed48490f8d3f
("mtd: gpmi: fix the bch setting backward compatible issue")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Oleksii Bidnichenko [Fri, 8 Apr 2022 08:07:13 +0000 (10:07 +0200)]
disk: part: add the device search failed log msg
Add missing error message to blk_get_device_part_str.
Signed-off-by: Oleksii Bidnichenko <oleksii.bidnichenko@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Philippe Schenker [Fri, 8 Apr 2022 08:07:11 +0000 (10:07 +0200)]
board: colibri-imx6ull: fix detecting ethernet phy
Now that it is possible to use regulator-fixed-clock make use
of it. This makes U-Boot detect the PHY on first cold-boot.
This commit also adjusts the code in setup_fec and follows
how it is done in mx6ullevk.c
This commit also slows down the boot-process by about 150ms
as it now waits for the regulator-fixed-clock voltage that
drives the PHY to go up.
If you rely on very fast boot-speeds and don't need ethernet
for your boot-process you can safely revert the changes on
imx6ull-colibri.dtsi
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Philippe Schenker [Fri, 8 Apr 2022 08:07:10 +0000 (10:07 +0200)]
regulator: fixed: add possibility to enable by clock
This commit adds the possibility to choose the compatible
"regulator-fixed-clock" in devicetree.
This is a special case of regulator-fixed where a clock has to
be used to switch the regulator on and off.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Philippe Schenker [Fri, 8 Apr 2022 08:07:08 +0000 (10:07 +0200)]
board: colibri-imx6ull: Do not leave variant variable unset
Toradex uses the variable variant to distinguish between modules with
eMMC, NAND with wifi and NAND without wifi.
This variable is set on every boot. Set this variable also if we have a
NAND module without wifi to prevent issues.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Denys Drozdov [Fri, 8 Apr 2022 08:07:07 +0000 (10:07 +0200)]
apalis-tk1: avoid save environment unasked
U-Boot should never save the environment unasked.
This also avoids storing broken fdt_module to flash.
Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Denys Drozdov [Fri, 8 Apr 2022 08:07:06 +0000 (10:07 +0200)]
apalis-imx6: avoid save environment unasked
U-Boot should never save the environment unasked.
This also avoids storing broken ftd_file to eMMC.
Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Oleksandr Suvorov [Fri, 8 Apr 2022 08:07:03 +0000 (10:07 +0200)]
colibri-imx6ull: drop vidargs and remove video= settings
Since we envision using overlays for display interfaces, the video=
settings within vidargs are obsolete. Remove these settings from the
U-Boot.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Philippe Schenker [Fri, 8 Apr 2022 08:07:02 +0000 (10:07 +0200)]
include: colibri_vf: add missing tdxargs variable
All the other NAND-based boards have tdxargs specified for setting
manual kernel command-line arguments.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marcel Ziswiler [Fri, 8 Apr 2022 08:06:57 +0000 (10:06 +0200)]
configs: verdin-imx8mm: verdin-imx8mp: enable dm serial
Enable driver model for serial.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marcel Ziswiler [Fri, 8 Apr 2022 08:06:56 +0000 (10:06 +0200)]
arm64: dts: imx8mm-u-boot.dtsi: imx8mp-u-boot.dtsi: use atf-bl31 type
Explicitly use the atf-bl31 type for the bl31.bin atf-blob. This uses
the path from the BL31 environment variable, if defined.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marek Vasut [Fri, 8 Apr 2022 00:15:00 +0000 (02:15 +0200)]
ARM: imx8mm: verdin-imx8mm: Rework board_early_init()
Rename board_early_init_f() to board_early_init(), since this function
has nothing to do with actual board_early_init_f() as used throughout
U-Boot. The board_early_init() is function local to this board used to
configure UART and WDT pinmux. Wrap init_uart_clk() into this function
so that early UART init would be all in one place. Turn the function
into __weak one, so it could be overridden in case custom carrier board
uses different UART or needs custom IOMUX settings.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Ye Li [Thu, 7 Apr 2022 07:55:56 +0000 (15:55 +0800)]
imx8m: soc: Relocate u-boot to the top DDR in 4GB space
The EFI memory init uses gd->ram_top for conventional memory. In
current implementation, the ram_top is below optee address. This cause
grub failed to allocation memory for initrd.
The change updates DDR bank setup functions to place the u-boot at top
DDR in 4GB space.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 7 Apr 2022 07:55:55 +0000 (15:55 +0800)]
imx8m: soc: drop phy-reset-gpios for fec
Need to drop phy-reset-gpios before booting linux, this property
is legacy property and replaced with reset-gpios.
If provide both, kernel would failed to request the same gpio twice
and cause fec not work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 7 Apr 2022 07:55:54 +0000 (15:55 +0800)]
imx: imx8m: soc: runtime drop extcon property from usbotg node
The extcon is an decrepted property and not used by upstream Linux and
NXP 5.10 kernel, so we remove it before kicking linux in case it is in
dts. Otherwise distro kernel will not able to have usb function.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 7 Apr 2022 07:55:53 +0000 (15:55 +0800)]
imx: imx8mp: disable fused IP for UltraLite
Beside the fused modules on iMX8MP Lite, this part has also fused
GPU3D/2D, LVDS and MIPI DSI.
So we have to disable them for kernel and also disable MIPI DSI
in u-boot DTS for splash screen at runtime.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 7 Apr 2022 07:55:52 +0000 (15:55 +0800)]
imx: imx8mp: detect i.MX8MP UltraLite when get cpu rev
Detect i.MX8MP UltraLite in get_cpu_variant_type
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 7 Apr 2022 07:55:51 +0000 (15:55 +0800)]
imx: imx8mp: Add iMX8MP UltraLite Part cpu type
Add i.MX8MP UltraLite Part CPU type
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Francesco Dolcini [Wed, 6 Apr 2022 11:53:25 +0000 (13:53 +0200)]
mx6: ddr: Wait before issuing the first MRS cmd
Wait 1ms before issuing the first MRS command to write DDR3 Mode
registers.
There is a requirement to wait a minimum time before issuing command to
the DDR3 device, according to the JEDEC standard this time is 500us
(after RESET_n is de-asserted until CKE becomes active) + tXPR (Reset
CKE Exit time, maximum value 360ns).
It seems that for some reason this is not enforced by the MMDC
controller.
Without this change we experienced random memory initialization failures
with about 2% boot failure rate on specific problematic boards, after
this change we were able to do more than 10.000 power-cycle without a
single failure.
Fixes:
fe0f7f7842e1 ("mx6: add mmdc configuration for MX6Q/MX6DL")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Francesco Dolcini [Wed, 6 Apr 2022 11:53:24 +0000 (13:53 +0200)]
mx6: ddr: Restore ralat/walat in write level calibration
The current DDR write level calibration routine always overwrite
the ralat/walat fields to their maximum value, just save
the existing values at the beginning of the calibration routine
and restore it at the end.
In case the delay is estimated by the user to be more than one cycle the
walat should be configured according to that, this is not
automatically done. From the i.MX6 RM:
The user should read the results of the associated delay-line at
MPWLDECTRL#[WL_DL_ABS_OFFSET#] and in case the user estimates that the
reasonable delay may be above 1 cycle then the user should indicate it at
MPWLDECTRL#[WL_CYC_DEL#]. Moreover the user should indicate it in
MDMISC[WALAT] field. For example, if the result of the write leveling calibration
is 100/256 parts of a cycle, but the user estimates that the delay is above 2 cycles
then MPWLDECTRL#[WL_CYC_DEL#] should be configured to 2, so the total
delay will be 2 and 100/256 parts of a cycle
Probably it would just possible to not overwrite the mdmisc register in
the first place, since this is not present in the write_level_calib() example
in NXP AN4467 nor in the i.MX6 RM (44.11.6.1 Hardware Write Leveling
Calibration).
Fixes:
d339f16911c7 ("arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Wed, 6 Apr 2022 06:30:31 +0000 (14:30 +0800)]
misc: imx8ulp: Update fuse driver
- According to S400 API, the fuse bank 25 (Testconfig2) is able to
access. Add it into driver's mapping table.
- According to FSB words list, the reserved 48 words are ahead of
the bank 5 and bank 6. Fix the wrong position.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:30 +0000 (14:30 +0800)]
imx: imx8ulp_evk: Enable multiple env storage devices
Enable multiple storages for u-boot env:
MMC or SPI flash or NOWHERE for usb
so u-boot can runtime select the storage flash according to boot device.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:29 +0000 (14:30 +0800)]
imx: imx8ulp_evk: enlarge CONFIG_NR_DRAM_BANKS
When TEE is present, the DRAM maybe split to two parts,
so enlarge CONFIG_NR_DRAM_BANKS
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ji Luo [Wed, 6 Apr 2022 06:30:28 +0000 (14:30 +0800)]
imx: imx8ulp: reserve tee memory
The TEE memory should be reserved when TEE is present, so need
to runtime update dram bank and memory information according to
tee present or not.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:27 +0000 (14:30 +0800)]
imx: imx8ulp: enable wdog_ad interrupt in CMC1
Enable wdog_ad interrupt being triggered by CMC1 to CM33 to let CM33
know A35 reset and reinitialize rpmsg.
Clear wdog_ad and AD_PERIPH reset interrupt after A35 up, otherwise
M33 will always receive interrupt.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:26 +0000 (14:30 +0800)]
imx: imx8ulp_evk: Enable SD/MMC port auto detect
Enable the SD/MMC port auto detect.
The mmc relevant env can be reset when auto detect is enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:25 +0000 (14:30 +0800)]
imx: dynamic setting mmcdev and mmcroot
Dynamic setting mmcdev and mmcroot.
Then when boot linux, we can have correct "root=/dev/mmcblk[x]p2"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:23 +0000 (14:30 +0800)]
imx: imx8ulp_evk: call the handshake with M33
If M33 handshake is successful, TPM and DSI panel MUX setting is
done by M33, no need to set them.
If handshake is failed or M33 is not booted, continue the TPM
and DSI panel MUX setting
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:22 +0000 (14:30 +0800)]
imx: imx8ulp_evk: Update LPDDR4 PHY settings
Update DDR PHY settings to support LPDDR4 mode only by adjusting
DQ VREF ctrl, ODT and pads drive strength.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Clement Faure [Wed, 6 Apr 2022 06:30:21 +0000 (14:30 +0800)]
imx: imx8ulp: release CAAM for the Cortex-A35
Release the CAAM for the A35 from the SPL.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:20 +0000 (14:30 +0800)]
misc: S400_API: Update S400 API for buffer dump
Add ahab_dump_buffer API to dump AHAB buffer for debug purpose
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Clement Faure [Wed, 6 Apr 2022 06:30:19 +0000 (14:30 +0800)]
misc: S400_API: add ahab_release_caam
Add ahab_release_caam() function to the S400 API.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:18 +0000 (14:30 +0800)]
imx: imx8ulp: Load the lposc fuse for dual boot
Found the lposc fuse loading having impact to cpu idle in kernel.
Without the loading in dual boot mode, kernel will hang after idle
for a while.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:17 +0000 (14:30 +0800)]
imx: imx8ulp: Change LPAV assignment for dual boot
Assign the LPAV owner to RTD, and assign LPAV masters and peripherals
to APD. So except the masters and peripherals, other resources
(like DDR, cgc2, pcc5) in LPAV won't be reset during reboot and suspend.
No needs to initialize DDR again after reboot.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:16 +0000 (14:30 +0800)]
misc: imx8ulp: Add OEM SRK Hash fuse support
Since latest S400 firmware has supported to read OEM SRK Hash, add
it to the driver's table
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:15 +0000 (14:30 +0800)]
imx: imx8ulp: enable MU0_B clk by default
Enable MU0_B clk by default. When M33 image is loaded by Jlink,
the previous method not enable MU0_B clk and not able to communicate
with M33, so let's enable it by default.
And we not put it under kernel dts, because it conflicts with i.MX8QM
suspend/resume logic which requires large change.
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:14 +0000 (14:30 +0800)]
imx: imx8ulp: cgc: Switch to NICLPAV to FRO192 before PLL4 init
When reset with dual boot mode, the LPAV domain won't power down
due to its master is not assigned to APD. So the NICLPAV keeps the
last setting to use PLL4PFD1. So before SPL initialize the PLL4,
we need to switch NICLPAV to FRO192, otherwise system will hang.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:13 +0000 (14:30 +0800)]
imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode
When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:12 +0000 (14:30 +0800)]
imx: imx8ulp: add ND/LD clock
Add a new ddr script, defconfig for ND
Configure the clock for ND mode
changing A35 to 960MHz for OD mode
Update NIC CLK for the various modes
Introduce clock_init_early/late, late is used after pmic voltage
setting, early is used in the very early stage for upower mu, lpuart and
etc.
Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with
cpuidle enabled now.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:11 +0000 (14:30 +0800)]
imx: imx8ulp_evk: Remove PMIC Bucks PWM mode settings
This workaround is not needed on i.MX8ULP proto-1B EVK as board has
fixed the problem. Because we don't support proto-1A any longer,
remove the PMIC settings.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:10 +0000 (14:30 +0800)]
imx: imx8ulp: add CAAM clock entry
Add CAAM clock entry in PCC3
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Clark Wang [Wed, 6 Apr 2022 06:30:09 +0000 (14:30 +0800)]
imx: imx8ulp: clock: Add clock support for i3c controller
Add i3c controller clock enable/disable function for imx8ulp.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:08 +0000 (14:30 +0800)]
imx: imx8ulp: Add M33 handshake functions
Add functions to check if M33 image is booted and handshake with M33
image via MU. A core notifies M33 to start init by FCR F0, then wait
M33 init done signal by checking FSR F0.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 6 Apr 2022 06:30:07 +0000 (14:30 +0800)]
imx: imx8ulp: include pcc/cgc header in clock header
With this change, we no need to include pcc/cgc header files both.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 6 Apr 2022 06:30:06 +0000 (14:30 +0800)]
imx: imx8ulp: Set COUNTER_FREQUENCY to 1Mhz
The COUNTER_FREQUENCY is missed in 8ulp configs, it will cause SPL
and u-boot not set the cntfrq_el0. For u-boot, this is ok, because
ATF has set it. But for SPL, it will lead delay and get_timer
not working.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Fri, 1 Apr 2022 01:18:31 +0000 (03:18 +0200)]
phy: phy-imx8mq-usb: Add support for i.MX8MP USB PHY
Add initial support for i.MX8MP USB PHY, i.MX8MP USB is similar to
the i.MX8MQ, except for clock and power domain design customization.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
Marek Vasut [Fri, 1 Apr 2022 01:17:29 +0000 (03:17 +0200)]
clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock
Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Clément Péron [Wed, 30 Mar 2022 11:49:30 +0000 (13:49 +0200)]
arm: imx: parse-container: add some missing end of line
Some printf() have strings that doesn't terminate with end of line
and make the output hard to read.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Angus Ainslie [Tue, 29 Mar 2022 14:02:40 +0000 (07:02 -0700)]
clk: imx8m: reduce rate table duplication
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common place")
Signed-off-by: Angus Ainslie <angus@akkea.ca>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon
Angus Ainslie [Tue, 29 Mar 2022 14:02:39 +0000 (07:02 -0700)]
clk: imx8mq: Add a clock driver for the imx8mq
This is a DM clock driver based off the imx8mm u-boot driver and the linux
kernel driver.
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
Signed-off-by: Angus Ainslie <angus@akkea.ca>
Acked-by: Sean Anderson <seanga2@gmail.com>
Angus Ainslie [Tue, 29 Mar 2022 14:02:38 +0000 (07:02 -0700)]
dt-bindings: imx8mq-clock: add mainline definitions
Sync the clock ids with the mainline kernel
077de6e1c9f ("clk: imx8mq: add PLL monitor output")
Signed-off-by: Angus Ainslie <angus@akkea.ca>
Reviewed-by: Marek Vasut <marex@denx.de>
Ye Li [Mon, 28 Mar 2022 09:14:07 +0000 (17:14 +0800)]
mtd: nand: mxs_nand_spl: Remove the page aligned access
The mxs_nand_spl driver can support to read from page unaligned offset,
so don't need to set bl_len to ask spl_load_simple_fit to handle
the page unaligned access.
Actually spl_load_simple_fit has two parts of reading:
spl_simple_fit_read and spl_load_fit_image.
The spl_load_fit_image can handle the page unaligned offset,
but the spl_simple_fit_read can't do it. spl_simple_fit_read requires
the FIT location at page aligned offset.
Hence, remove the nand_get_mtd overwrite function from mxs_nand_spl
to use page unaligned read by driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Tim Harvey <tharvey@gateworks.com> #gw_ventana
Tommaso Merciai [Sat, 26 Mar 2022 11:19:10 +0000 (12:19 +0100)]
configs: imx8mm_evk: add pwm backlight support
Enable support for backlight/pwm-imx driver
Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Tommaso Merciai [Sat, 26 Mar 2022 11:19:09 +0000 (12:19 +0100)]
arm: dts: imx8mm_evk: add pwm1/backlight support
Add pwm1/backlight support nodes for imx8mm_evk board
Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Tommaso Merciai [Sat, 26 Mar 2022 11:19:07 +0000 (12:19 +0100)]
driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms
Introduce pwm_dm_imx_get_parms, dm version of pwm_imx_get_parms.
This function get clock rate using clk dm api
Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Tommaso Merciai [Sat, 26 Mar 2022 11:19:06 +0000 (12:19 +0100)]
driver: pwm: pwm-imx: get and enable per/ipg clock using dm
Get and enable ipg/per pwms clocks using dm api into imx_pwm_of_to_plat
and imx_pwm_probe driver function
Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Tommaso Merciai [Sat, 26 Mar 2022 11:19:04 +0000 (12:19 +0100)]
clk: imx8mm: add pwm clocks support
Add clocks support for the PWM controllers. This is ported from
Linux v5.17-rc8.
Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Tommaso Merciai [Sat, 26 Mar 2022 11:19:03 +0000 (12:19 +0100)]
arch: mach-imx: imx8m: add pwm_regs struct in imx-regs
Add pwm_regs struct for i.MX8MM SOC
Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Tommaso Merciai [Sat, 26 Mar 2022 11:19:02 +0000 (12:19 +0100)]
arch: mach-imx: imx8m: add pwm ctrl registers fields defines
Add pwm control registers fields defines into imx-regs.h:
- prescaler
- dozeen
- waiten
- dbgen
- clksrc_ipg_high
- clksrc_ipg, en field
References:
- iMX8MMRM.pdf p 3884
Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Marek Vasut [Fri, 25 Mar 2022 17:59:28 +0000 (18:59 +0100)]
ARM: imx: Decode ECSPI env location from i.MX8M ROMAPI tables
Decode ECSPI boot device in env_get_location() from i.MX8M ROMAPI tables.
This is necessary to correctly identify env is in SPI NOR when the system
boots from SPI NOR attached to ECSPI.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 19 Mar 2022 15:45:16 +0000 (10:45 -0500)]
arm: imx: imx8mn_beacon: Remove unnecessary configs
Because the Beacon imx8mn board uses device tree
for MMC/SD and Ethernet, there is no need to have some of the
config options. It's handled by the device tree.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 19 Mar 2022 15:45:15 +0000 (10:45 -0500)]
arm: imx: imx8mm_beacon: Remove unnecessary configs
Because the Beacon imx8mm board uses device tree
for MMC/SD and Ethernet, there is no need to have some of the
config options. It's handled by the device tree.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Ye Li [Fri, 18 Mar 2022 07:50:18 +0000 (15:50 +0800)]
imx8ulp: Disable SPL exception vector
Disable SPL exception vector which causes issue to ROM patch execution
when SPL calling ROM API.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>