Philipp Tomsich [Tue, 6 Jun 2017 13:42:31 +0000 (15:42 +0200)]
rockchip: dts: rk3399: enable HDMI output in the DTS
This commit enables HDMI output in the DTS by adding the necessary
nodes to vopl/vopb and by adding the HDMI node.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 6 Jun 2017 13:42:29 +0000 (15:42 +0200)]
usb: dwc2-otg: make regs_otg (in platdata) a uintptr_t
The regs_otg field in uintptr_t of the platform data structure for
dwc2-otg has thus far been an unsigned int, but will eventually be
casted into a void*.
This raises the following error with GCC 6.3 and buildman:
../drivers/usb/gadget/dwc2_udc_otg.c: In function 'dwc2_udc_probe':
../drivers/usb/gadget/dwc2_udc_otg.c:821:8: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
^
This changes regs_otg to a uintptr_t to ensure that it is large enough
to hold any valid pointer (and fix the associated warning).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Tue, 6 Jun 2017 07:15:15 +0000 (09:15 +0200)]
rockchip: defconfig: puma-rk3399: update defconfig with video-support
With HDMI output for the RK3399 working, this update the RK3399-Q7
(Puma) defconfig for the new functionality:
1. enables PMIC command (to check if the HDMI voltages are correct)
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
2. enables video-output (via HDMI)
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
3. turns on the 'dcache'-command (for a dcache flush) for our QA to
fill the framebuffer using 'mw.l'
+CONFIG_CMD_CACHE=y
4. turns on the 'bmp'-command
+CONFIG_CMD_BMP=y
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 6 Jun 2017 07:15:14 +0000 (09:15 +0200)]
rockchip: video: rk_hdmi: fix implicit definition warnings
When enabling CONFIG_DISPLAY_ROCKCHIP_HDMI, compile-time warning for
the following implicitly defined functions are raised due to a missing
include directive:
drivers/video/rockchip/rk_hdmi.c: In function 'rk_hdmi_probe':
drivers/video/rockchip/rk_hdmi.c:150:2: warning: implicit declaration of function 'rk_setreg' [-Wimplicit-function-declaration]
rk_setreg(&priv->grf->soc_con6, 1 << 15);
^~~~~~~~~
drivers/video/rockchip/rk_hdmi.c:153:2: warning: implicit declaration of function 'rk_clrsetreg' [-Wimplicit-function-declaration]
rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
^~~~~~~~~~~~
This change fixes this by including <asm/hardware.h> in rk_hdmi.c.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 6 Jun 2017 13:42:28 +0000 (15:42 +0200)]
rockchip: rk3328: don't implement usb_gadget_handle_interrupts twice
The usb_gadget_handle_interrupts()-function is already implemented by
drivers/usb/gadget/dwc2_udc_otg.c, so we need to avoid defining it
in the evb-rk3328.c board-specific file.
This change fixes the following build error (from buildman):
drivers/usb/gadget/built-in.o: In function `usb_gadget_handle_interrupts':
build/../drivers/usb/gadget/dwc2_udc_otg.c:850: multiple definition of `usb_gadget_handle_interrupts'
board/rockchip/evb_rk3328/built-in.o:build/../board/rockchip/evb_rk3328/evb-rk3328.c:37: first defined here
make[1]: *** [u-boot] Error 1
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Meng Dongyang [Thu, 1 Jun 2017 11:22:45 +0000 (19:22 +0800)]
rockchip: usb: host: xhci-rockchip: add support for rk3328
Add the compatible "rockchip,rk3328-xhci" in match table
for rk3328 to probe xhci controller. Use fixed regulator
to control the voltage of vbus and turn off vbus when
usb stop.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Thu, 1 Jun 2017 10:01:31 +0000 (18:01 +0800)]
rockchip: Add basic support for evb-rv1108 board
Add basic support for rv1108 evb, whith this patch we
can boot into u-boot console.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Thu, 1 Jun 2017 10:00:55 +0000 (18:00 +0800)]
rockchip: Add core Soc start-up code for rv1108
RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core
from Rockchip. It is designed for varies application scenario such
as car DVR, sports DV, secure camera and UAV camera.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Thu, 1 Jun 2017 10:00:36 +0000 (18:00 +0800)]
rockchip: clk: Add rv1108 clock driver
Add clock driver support for Rockchip rv1108 soc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Thu, 1 Jun 2017 10:00:10 +0000 (18:00 +0800)]
rockchip: pinctrl: Add rv1108 pinctrl driver
Add pinctrl support for Rockchip rv1108 soc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Thu, 1 Jun 2017 09:58:31 +0000 (17:58 +0800)]
rockchip: mkimage: Add support for RV1108
Add support to mkimage for rv1108 soc, the max
spl code size for rv1108 is 6kb, and the spl
code should be packed by rksd, wether boot from
emmc or spi nor flash.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 31 May 2017 16:18:50 +0000 (18:18 +0200)]
rockchip: defconfig: puma-rk3399: do not filter clock-names for SPL
For the RK3399-Q7 module, we use full OF_CONTROL (i.e. not
OF_PLATDATA) for SPL. In this configuration, the rockchip_dw_mmc
driver retrieves one of its clocks via clk_get_by_name and fails if
this is not possible. For this reason, we can not filter clock-names
from the device-tree nodes used for the configuration of the SPL
stage.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 31 May 2017 16:18:49 +0000 (18:18 +0200)]
rockchip: defconfig: puma-rk3399: enable I2C
The RK3399-Q7 exposes I2C on its edge connector and uses it as one of
the interfaces towards the on-module STM32 (for the emulated RTC and
fan-controller).
Enable I2C and CMD_I2C support in the defconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 31 May 2017 16:18:48 +0000 (18:18 +0200)]
rockchip: defconfig: puma-rk3399: enable CONFIG_PHY_MICREL_KSZ9031
The RK3399-Q7 has a KSZ9031 GbE PHY. Enable support for it in defconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 31 May 2017 16:18:46 +0000 (18:18 +0200)]
rockchip: defconfig: puma-rk3399: enable RK808 support
On the RK3399-Q7, we need PMIC support (for the RK808) to enable HDMI
output, as one of the required powerrails is not enabled on boot.
For this, we need to enable the RK808 driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 3
- With the recent upstream changes to the RK808 (PMIC) driver, the
associated configuration options have been renamed to RK8XX. Track
this change in the RK3399-Q7 defconfig.
Reviewed-by: Simon Glass <sjg@chromium.org>
Klaus Goger [Wed, 31 May 2017 16:17:59 +0000 (18:17 +0200)]
rockchip: dts: rk3399-puma: set spl-payload-offset
defines the spl-payload to 256k (0x40000)
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 31 May 2017 16:17:58 +0000 (18:17 +0200)]
rockchip: dts: rk3399-puma: release reset of on-module USB3 hub via vbus-gpio
On the RK3399-Q7, the on-module USB3 hub is held in reset at boot-up
to save power and needs to be woken up using GPIO4A3.
Note that this is not a negated reset-signal (due to a level shifter
being needed for this signal anyway), but a negated enable-signal:
to enable, we need to output LOW (i.e. 0)... so we mark this as an
ACTIVE_LOW signal.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 31 May 2017 16:17:57 +0000 (18:17 +0200)]
rockchip: dts: rk3399-puma: make the debug serial dm-pre-reloc
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 31 May 2017 16:16:36 +0000 (18:16 +0200)]
rockchip: dts: rk3399-puma: Add DDR3-1866 timings
With the validation done for DDR3-1866 (i.e. 933 MHz bus clock), we
can now add the timings (rk3399-sdram-ddr3-1866.dtsi) for boards built
with the DDR3-1866 option.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 31 May 2017 16:16:35 +0000 (18:16 +0200)]
rockchip: arm64: rk3399: support DDR3-1866 (i.e. 933MHz clock)
The RK3399 is capable of driving DDR3 at 933MHz (i.e. DDR3-1866),
if the PCB layout permits and appropriate memory timings are used.
This changes the sanity checks to allow a DTS to request DDR3-1866
operation.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Philipp Tomsich [Wed, 31 May 2017 16:16:34 +0000 (18:16 +0200)]
rockchip: arm64: rk3399: revise timeout-handling for DRAM PHY lock
Revise the loop watching for a timeout on obtaining a DRAM PHY lock to
clearly state a timeout in milliseconds and use get_timer (based on
the ARMv8 architected timer) to detect a timeout.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 30 May 2017 21:32:10 +0000 (23:32 +0200)]
rockchip: mkimage: set init_boot_size to avoid confusing the boot ROM
This change restores the earlier setting of init_boot_size to include
the maximum area covered by the the boot ROM of each chip for resolve
issues with back-to-bootrom functionality reported by Kever and Heiko.
To ensure that we don't run into the same issue again in the future,
I have updated the comments accordingly and added a reference to the
mailing list archive (there's some very helpful info from Andy Yan
that provides background on the BootROM requirements regarding these
fields).
See https://lists.denx.de/pipermail/u-boot/2017-May/293267.html for
some background (by Andy Yan) of how the BootROM processes this field.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 30 May 2017 21:32:09 +0000 (23:32 +0200)]
rockchip: mkimage: force 2KB alignment for init_size
The Rockchip BootROM relies on init_size being aligned to 2KB
(see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html).
This pads the image to 2KB both for SD card images and SPI images
and uses a common symbolic constant for the alignment.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 30 May 2017 21:32:08 +0000 (23:32 +0200)]
rockchip: mkimage: add support for verify_header/print_header
The rockchip image generation was previously missing the ability to
verify the generated header (and dump the image-type) without having
to resort to hexdump or od. Experience in our testing has showed it
to be very easy to get the rkspi and rksd images mixed up and the
lab... so we add the necessary support to have dumpimage tell us
what image type we're dealing with.
This change set adds the verify_header and print_header capability
to the rksd/rkspi image drivers (through shared code in rkcommon).
As of now, we only support images fully that are not RC4-encoded for
the SPL payload (i.e. header1 and payload). For RC4-encoded payloads,
the outer header (header0) is checked, but no detection of whether
this is a SD/MMC or SPI formatted payload takes place.
The output of dumpsys now prints the image type (spl_hdr), whether it
is a SD/MMC or SPI image, and the (padded) size of the image:
$ ./tools/dumpimage -l ./spl.img
Image Type: Rockchip RK33 (SD/MMC) boot image
^^^^^^ SD/MMC vs. SPI indication
^^^^ spl_hdr indicated by the image
Data Size: 79872 bytes
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Tue, 23 May 2017 07:01:15 +0000 (15:01 +0800)]
rockchip: evb-rk3328: update board maintainer
Update maintainer to Kever Yang for William Zhang is not
work for this board now.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Tue, 23 May 2017 07:01:14 +0000 (15:01 +0800)]
MAINTAINERS: rockchip: add board/rockchip as maintained entry
Directory board/rockchip/ are all boards for Rockchip SoCs,
so add it to maintained entry.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Tue, 23 May 2017 07:01:13 +0000 (15:01 +0800)]
MAINTAINERS: git-mailrc: update maintainer for Rockchip
Send patch to Kever Yang instead of Lin Huang for Rockchip patches,
for Lin is not always working on upstream U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Changed , to : in subject:
Signed-off-by: Simon Glass <sjg@chromium.org>
Meng Dongyang [Wed, 17 May 2017 10:25:28 +0000 (18:25 +0800)]
rockchip: dts: rk3328: support and enable xhci
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Meng Dongyang [Wed, 17 May 2017 10:21:47 +0000 (18:21 +0800)]
configs: rk3328: config xhci controller
Add config of max root ports and add config to enable xhci
controller.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Meng Dongyang [Wed, 17 May 2017 10:21:46 +0000 (18:21 +0800)]
rockchip: dts: rk3328: add ehci and ohci node and enable host0 port
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Meng Dongyang [Wed, 17 May 2017 10:21:45 +0000 (18:21 +0800)]
configs: rk3328: add support for usb and config ehci and ohci driver
Add defconfig for usb and ehci and ohci controller, config maximal
number of ports of the root hub for ohci driver.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Wed, 17 May 2017 03:44:44 +0000 (11:44 +0800)]
rockchip: pinctrl: rk3328: do not set io routing
In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3 choice(setting in com_iomux):
- M0 which mux with GPIO1A0/GPIO1A1
- M1 which mux with GPIO2A0/GPIO2A1
- usb2phy which mux with USB2.0 DP/DM pin.
We should not decide which group to use in pinctrl driver,
for it may be different in different board, it should goes to board
file, and the pinctrl file should setting correct iomux depends on
the com_iomux value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Wed, 17 May 2017 03:44:43 +0000 (11:44 +0800)]
rockchip: pinctrl: move rk3328 grf reg definition in header file
Move GRF register bit definition into GRF header file, remove
'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 15 May 2017 12:52:17 +0000 (20:52 +0800)]
rockchip: rk3036: clean mask definition for grf reg
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
definition in grf header file and pinctrl driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 15 May 2017 12:52:16 +0000 (20:52 +0800)]
rockchip: clock: rk3036: some fix according TRM
- hclk/pclk_div range should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 15 May 2017 12:52:15 +0000 (20:52 +0800)]
rockchip: rk3036: clean mask definition for cru reg
Embeded the shift in mask MACRO definition in cru header file
and clock driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Mon, 15 May 2017 09:54:48 +0000 (17:54 +0800)]
rockchip: rk3368: Add PX5 Evaluation board
PX5 EVB is designed by Rockchip for automotive field
with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
HDMI video input/output interface, audio codec ES8396,
WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity
sensor STK3410.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andreas Färber [Mon, 15 May 2017 09:54:26 +0000 (17:54 +0800)]
rockchip: rk3368: Add initial support for RK3368 based GeekBox
The GeekBox is a TV box from GeekBuying, based on an MXM3 module.
The module can be used with base boards such as the GeekBox Landingship.
This adds basic support to chain-load U-Boot from Rockchip's miniloader.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Mon, 15 May 2017 09:53:50 +0000 (17:53 +0800)]
rockchip: rk3368: add Sheep board
Sheep board is designed by Rockchip as a EVB for rk3368.
Currently it is able to boot a linux kernel and system
to console with the miniloader run as fist level loader.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Andy Yan [Mon, 15 May 2017 10:19:42 +0000 (18:19 +0800)]
rockchip: rk3368: Add sysreset driver
Add sysreset driver to reset rk3368 SOC.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andreas Färber [Mon, 15 May 2017 09:51:18 +0000 (17:51 +0800)]
rockchip: rk3368: Add core start-up code for RK3368
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Mon, 15 May 2017 09:50:35 +0000 (17:50 +0800)]
rockchip: rk3368: Add pinctrl driver
Add driver to support iomux setup for the most commonly
used peripherals on rk3368.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Mon, 15 May 2017 09:49:56 +0000 (17:49 +0800)]
rockchip: rk3368: Add clock driver
Add driver to setup the various PLLs and peripheral
clocks on the RK3368.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mark Kettenis [Sat, 13 May 2017 18:17:05 +0000 (20:17 +0200)]
regulator: pwm: Fix handling of missing init voltage
Since priv->init_voltage is an unsigned integer it can never be
negative. So the current code fails to detect a missing
'regulator-init-microvolt' property and instead misconfigures the
PWM device. Fix this by making the relevant members of
'struct pwm_regulator_info' signed integers.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Heiko Stübner [Sat, 6 May 2017 19:21:29 +0000 (21:21 +0200)]
power: rk808: fix ldo register offset
Till now get_ldo_reg did a return &rk808_ldo[num - 1]; to return
the ldo register offset but didn't take into account that its
calling functions already created the ldo as ldo = dev->driver_data - 1.
This resulted in the setting for ldo8 writing to the register of ldo7
and so on. So fix this and get the correct ldo register data.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 5 May 2017 17:22:54 +0000 (19:22 +0200)]
rockchip: board: puma_rk3399: build FIT image via u-boot.itb
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 5 May 2017 17:21:41 +0000 (19:21 +0200)]
rockchip: defconfig: puma-rk3399: enable RK3399 efuse driver
With everything in place (i.e. the new efuse driver, the clk-support
for the non-secure efuse block, and the board-specific functions to
derive 'serial#' from the cpu-id within the efuses), enable this in
the RK3399-Q7 defconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Klaus Goger [Fri, 5 May 2017 17:21:40 +0000 (19:21 +0200)]
rockchip: board: puma_rk3399: derive ethaddr from cpuid
Generate a MAC address based on the cpuid available in the efuse
block: Use the first 6 byte of the cpuid's SHA256 hash and set the
locally administered bits. Also ensure that the multicast bit is
cleared.
The MAC address is only generated and set if there is no ethaddr
present in the saved environment.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 5 May 2017 17:21:39 +0000 (19:21 +0200)]
rockchip: board: puma_rk3399: add support for serial# and cpuid# via efuses
With our efuse driver for the RK3399 ready, we can add the
board-specific code that consumes the cpuid from the efuse block and
postprocesses it into the system serial (using the same CRC32 based
derivation as in Linux).
We expose the cpuid via two distinct environment variables:
serial# - the serial number, as derived in Linux
cpuid# - the raw 16 byte CPU id field from the fuse block
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 5 May 2017 17:21:38 +0000 (19:21 +0200)]
rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block
This adds a simple driver for reading the efuse block of the RK3399.
It should be easy enough to add drivers for other devices (e.g. the
RK3328, RK3368, etc.) by passing the device details via driver_data.
Unlike the kernel driver (using the nvmem subsystem), we don't expose
the efuse as multiple named cells, but rather as a linear memory that
can be read using misc_read(...).
The primary use case (as of today) is the generation of a 'serial#'
(and a 'cpuid#') environment variable for the RK3399-Q7 (Puma)
system-on-module.
Note that this adds a debug-only (i.e. only if DEBUG is defined)
command 'rk3399_dump_efuses' that dumps the efuse block's content.
N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to
include a SoC-name (together with a comment in the function) to
remind whoever adds support for additional SoCs that this
function currently makes assumptions regarding the size of the
fuse-box based on the RK3399. The hope is that the function is
adjusted to reflect any changes resulting from generalising the
driver for multiple SoCs and is then renamed.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 5 May 2017 06:50:56 +0000 (14:50 +0800)]
rockchip: rk8xx: allocate priv structure for driver
The rk8xx_priv structure need to allocate for driver, or else
it will cause data abort when CPU access it.
This is a bug fix for below patch set:
https://www.mail-archive.com/u-boot@lists.denx.de/msg247345.html
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 5 May 2017 03:01:43 +0000 (11:01 +0800)]
rockchip; rk3399: disable SRAM security region
Some host like SD and eMMC may use DMA to transter data to SRAM,
set memory to non-secure to make sure the address can be accessed.
The security of SRAM in OS suppose to initialized in ATF bl31, and
the SPL is before the bl31.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Wed, 3 May 2017 23:29:13 +0000 (01:29 +0200)]
defconfig: firefly-rk3399: fix pinctrl config option
The option is named PINCTRL_ROCKCHIP_RK3399 not ROCKCHIP_RK3399_PINCTRL.
Set the correct option.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 6 Jun 2017 11:13:39 +0000 (07:13 -0400)]
Merge git://git.denx.de/u-boot-ubi
Siva Durga Prasad Paladugu [Tue, 30 May 2017 12:29:06 +0000 (14:29 +0200)]
fs: usbifs: Fix warning in ubifs
This patch fixes the below warning by typecasting it properly
fs/ubifs/ubifs.c: In function 'ubifs_load':
fs/ubifs/ubifs.c:942:29: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
err = ubifs_read(filename, (void *)addr, 0, size, &actread);
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tom Rini [Tue, 6 Jun 2017 01:05:51 +0000 (21:05 -0400)]
Merge git://git.denx.de/u-boot-usb
Tom Rini [Tue, 6 Jun 2017 00:40:22 +0000 (20:40 -0400)]
Prepare v2017.07-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
Phil Edworthy [Thu, 1 Jun 2017 06:33:29 +0000 (07:33 +0100)]
armv7m: Fix larger builds
The branch instruction only has an 11-bit relative target address, which
is sometimes not enough.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Phil Edworthy [Thu, 1 Jun 2017 06:33:28 +0000 (07:33 +0100)]
arm: Add Kconfig symbols used for Linux asm compatibility
Rather than change asm files that come from Linux, add the symbols
to Kconfig. Since one of the symbols is for thumb2 builds, make
CPU_V7M always select them.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Michal Simek [Wed, 31 May 2017 09:28:30 +0000 (11:28 +0200)]
arm64: hikey: Fix instructions in readme
Fix inaccurate instructions in README.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Patrice Chotard [Tue, 30 May 2017 13:06:31 +0000 (15:06 +0200)]
drivers: ram: stm32: fix compilation issue
If CONFIG_CLK flag is not set, compilation raises the
following error message:
drivers/ram/stm32_sdram.c: In function 'stm32_fmc_probe':
drivers/ram/stm32_sdram.c:154:2: error: 'ret' undeclared (first use in this function)
ret = stm32_sdram_init(dev);
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
cc: Vikas Manocha <vikas.manocha@st.com>
Michal Simek [Mon, 29 May 2017 08:26:53 +0000 (10:26 +0200)]
arm64: Add NOLOAD attribute NOLOAD to .bss sections
Mark explicitly bss sections to not be loaded at
run time.
The similar patch was done in past by:
"Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections"
(sha1:
64134f011254123618798ff77c42ba196b2ec485)
The problem is related to latest toolchain added to Xilinx
v2017.1 design tools where jtag loader is trying to access
ununitialized memory.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 29 May 2017 07:11:32 +0000 (09:11 +0200)]
ARMv8: Add support for poweroff via PSCI
Add support for calling poweroff in case of psci is wired.
Based on the same solution as is used for reset.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Move all logic in to fwcall.c as other ARMs implement poweroff
via PMIC]
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 28 May 2017 12:49:51 +0000 (08:49 -0400)]
cmd/ethsw: Disable implicit enum conversion warning
With clang-3.8 we see warnings like:
cmd/ethsw.c:304:6: warning: implicit conversion from
enumeration type 'enum ethsw_keyword_opt_id' to different enumeration type
'enum ethsw_keyword_id' [-Wenum-conversion]
ethsw_id_pvid_no,
^~~~~~~~~~~~~~~~
Because we have one enum for ethsw_keyword_id and a second enum for
ethsw_keyword_opt_id. This ends up being safe as ethsw_keyword_opt_id
explicitly starts after ethsw_keyword_id enum ends. Disable the
warning here rather than collapse these into one enum and rely on
comments to denote where optional keywords begin.
Cc: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Pantelis Antoniou [Thu, 25 May 2017 16:24:06 +0000 (19:24 +0300)]
malloc: Turn on DEBUG when enabling unit tests
Unit tests require mallinfo which in turn requires DEBUG on
dlmalloc to be enabled.
The dependancy on CONFIG_SANDBOX is wrong.
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Pantelis Antoniou [Thu, 25 May 2017 16:23:58 +0000 (19:23 +0300)]
arm: Always keep the dtb section on objcopy
The dtb blob section must always be present in the resulting image.
Either if OF_EMBEDED is used or if unit tests include dtb blobs.
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Keerthy [Thu, 25 May 2017 10:07:34 +0000 (15:37 +0530)]
board: ti: am571-idx: Add vcores support
Update vcores for am571-idk board.
Reported-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 24 May 2017 15:04:03 +0000 (11:04 -0400)]
scripts/Makefile.lib: Only apply u-boot.dtsi files in the target directory
We only want to apply files such as 'omap5-u-boot.dtsi', which resides
in arch/arm/dts/ to other files in arch/arm/dts/ and not say
test/overlay/. Rework the make logic to check for -u-boot.dtsi files in
the same directory as their target dts.
Cc: Simon Glass <sjg@chromium.org>
Reported-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Wed, 24 May 2017 10:08:27 +0000 (12:08 +0200)]
ARM: ti: Update layout for MMC and eMMC (env and dfu)
The problems with the current DFU layout are:
MMC: The space allocated for u-boot is too small for the latest u-boot
(>750KB). We need to increase it. eMMC uses a much bigger area (2MB).
eMMC: region "u-boot.img.raw" overlaps the environment area and the region
"spl-os-image.raw".
both: region "spl-os-image.raw" is quite small and can't handle android
kernels
Fixing this requires growing some regions and moving others.
Care has been taken to leave some room for further growth of
"spl-os-args.raw".
Also the "env" now appears in the dfu so that it's apparent that the
region is not free space that can be used to grow "u-boot.img.raw".
The MLO region is 0x100 sectors wide but the 0x100 are unused in case the
MLO comes too overflow this areas.
The total space allocated for those raw binaries is 16MB, of which 13+MB
are reserved for the kernel image.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tom Rini [Mon, 22 May 2017 19:21:57 +0000 (19:21 +0000)]
common/spl/Kconfig: Use 'if SPL' / 'if TPL' guards
Much of the entries here simply depend on SPL (or TPL). Instead of this
redundancy use if SPL / if TPL to guard the rest of the choices and only
show them when we have the relevant option enabled.
Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Mon, 22 May 2017 11:05:36 +0000 (05:05 -0600)]
bootstage: Record time taken to set up the live device tree
This time is interesting as a comparision with the flat device tree time.
Add it to the record.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:35 +0000 (05:05 -0600)]
bootstage: Support SPL
At present bootstage only supports U-Boot proper. But SPL can also consume
boot time so it is useful to have the record start there.
Add bootstage support to SPL. Also support stashing the timing information
when SPL finishes so that it can be picked up and reported by U-Boot
proper. This provides a full boot time record, excluding only the time
taken by the boot ROM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:34 +0000 (05:05 -0600)]
bootstage: Adjust to use const * where possible
There are a few places that should use const *, such as
bootstage_unstash(). Update these to make it clearer when parameters are
changed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:33 +0000 (05:05 -0600)]
bootstage: Tidy up error return values
We should return a proper error number instead of just -1. This helps the
caller to determine what when wrong. Update a few functions to fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:32 +0000 (05:05 -0600)]
bootstage: Record the time taken to set up driver model
Driver model is set up ones before relocation and once after. Record the
time taken in each case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:31 +0000 (05:05 -0600)]
bootstage: Init as early as possible
At present we don't allow use of bootstage before driver model is running.
This means we cannot time the init of driver model itself.
Now that bootstage requires its own board-specific timer, we can move its
init to earlier in the sequence, both before and after relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:30 +0000 (05:05 -0600)]
bootstage: Support relocating boostage data
Some boards cannot access pre-relocation data after relocation. Reserve
space for this and copy it during preparation for relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:29 +0000 (05:05 -0600)]
bootstage: Use debug() for stashing messages
We don't normally want to see these messages. Change them to debug-only.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:28 +0000 (05:05 -0600)]
bootstage: Show records with a zero time
We can now use the record count to determine whether a record is valid or
not. Drop the test for a zero time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:27 +0000 (05:05 -0600)]
bootstage: Use rec_count as the array index
At present bootstage has a large array with all possible bootstage IDs
recorded. It adds times to the array element indexed by the ID. This is
inefficient because many IDs are not used during boot. We can save space
by only recording those IDs which actually have timestamps.
Update the array to use a record count, which increments with each
addition of a new timestamp. This takes longer to record a time, since it
may involve an array search. Such a search may be particularly expensive
before relocation when the CPU is running slowly or the cache is off. But
at that stage there should be very few records.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:26 +0000 (05:05 -0600)]
bootstage: Fix up code style and comments
There are several code style and comment nits. Fix them and also remove
the comment about passing bootstage to the kernel being TBD. This is
already supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:25 +0000 (05:05 -0600)]
bootstage: Convert to use malloc()
At present bootstage uses the data section of the image to store its
information. There are a few problems with this:
- It does not work on all boards (e.g. those which run from flash before
relocation)
- Allocated strings still point back to the pre-relocation data after
relocation
Now that U-Boot has a pre-relocation malloc() we can use this instead,
with a pointer to the data in global_data. Update bootstage to do this and
set up an init routine to allocate the memory.
Now that we have a real init function, we can drop the fake 'reset' record
and add a normal one instead.
Note that part of the problem with allocated strings remains. They are
reallocated but this will only work where pre-relocation memory is
accessible after relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:24 +0000 (05:05 -0600)]
bootstage: Change CONFIG_BOOTSTAGE_USER_COUNT to an int
There is no good read to make this hex, and integer is more natural for
this type of setting. Update it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:23 +0000 (05:05 -0600)]
bootstage: Require timer_get_boot_us() to be defined
At present we provide a default version of this function for use by
bootstage. However it uses the system timer and therefore likely requires
driver model. This makes it impossible to time driver-model init.
Drop the function and require boards to provide their own. Add a sandbox
version also. There is a default implememtation in lib/time.c for boards
which use CONFIG_SYS_TIMER_COUNTER.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 22 May 2017 11:05:22 +0000 (05:05 -0600)]
bootstage: Provide a default timer function
If CONFIG_SYS_TIMER_COUNTER is used we can provide a default microsecond
timer implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Lokesh Vutla [Sat, 20 May 2017 00:19:27 +0000 (05:49 +0530)]
ARM: k2g: Fix passing main pll info for higher speeds
Main pll is marked as arm plls for higher speeds. Fix this.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tom Rini [Thu, 18 May 2017 21:03:07 +0000 (17:03 -0400)]
cmd/elf.c: Support passing arguments with bootelf
The bootelf command could, but does not, pass additional arguments along
on the command line. Make do_bootelf consume bootelf/flags/address as
needed and then pass along anything else to the ELF application we've
launched.
Reported-by: Thomas Doerfler <thomas.doerfler@embedded-brains.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Patrice Chotard [Thu, 18 May 2017 07:58:00 +0000 (09:58 +0200)]
reset: sti: add deassert counter in reset channel descriptor
This deassert counter allow to manage "shared" reset lines
encountered in some specific case. On STiH410 SoC, DWC3,
EHCI and OHCI are all using a respective PHY, but all of
these PHYs shared a "global" reset.
Currently, during command "usb stop", all host controller are
stopped (XHCI, EHCI and OHCI). XHCI is first shutdowned, which
means that PHY global reset is asserted. Then EHCI is shutdowned,
but its PHY reset has already been asserted which make handshake()
call failed in ehci_shutdown().
This counter allows to really assert a reset lines only when the
"last" user is asserting it.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Thu, 18 May 2017 07:23:15 +0000 (09:23 +0200)]
test: py: hush: Add echo dependency
Some tests depends on echo command to be present.
Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 18 May 2017 07:23:14 +0000 (09:23 +0200)]
test: py: Use global pytestmark for hush tests
All tests in test_hush_if_test depends on hush parser to be
present. This patch simplify test dependencies by using global
pytestmark.
Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Uri Mashiach [Wed, 17 May 2017 14:29:28 +0000 (17:29 +0300)]
arm: am57xx: cl-som-am57x: adjust default env to the installation system
The SD card automatic installation system depends on the default
environment of the previous U-Boot.
Add the missing environment variables.
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Uri Mashiach [Wed, 17 May 2017 14:29:27 +0000 (17:29 +0300)]
ARM: am57xx: cl-som-am57x: support for AM5718
Disable SDRAM controller EMIF2 for single core SOC
Set SDRAM size size to 1GB
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Uri Mashiach [Wed, 17 May 2017 14:29:26 +0000 (17:29 +0300)]
arm: am57xx: cl-som-am57x: change the shell prompt
Change the shell prompt to "U-Boot# ".
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Uri Mashiach [Wed, 17 May 2017 14:29:25 +0000 (17:29 +0300)]
arm: am57xx: cl-som-am57x: support for FS boot
Supported boot devices are raw QSPI and raw SD card.
Add support for a FAT16/32 file system for SD card.
The SOC's boot ROM only supports FAT file system.
Therefore remove the SPL support for the EXT file system.
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 17 May 2017 14:23:11 +0000 (08:23 -0600)]
common: microblaze: Drop arch-specific declarations
These are not needed and should not be in common.h. Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 17 May 2017 14:23:10 +0000 (08:23 -0600)]
common: arm: freescale: layerscape: Move header files out of common.h
We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 17 May 2017 14:23:09 +0000 (08:23 -0600)]
common: arm: davinci: Move header file out of common
We should not have an arch-specific header file in common.h. Instead, use
the asm/hardware.h header to provide the required declarations, and drop
the common.h changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 17 May 2017 14:23:08 +0000 (08:23 -0600)]
common: ep93xx: Move arch-specific declarations out of common
These declarations should not be in common. Remove those that are not
needed and move the others to an arch-specific location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 17 May 2017 14:23:07 +0000 (08:23 -0600)]
common: freescale: Move arch-specific imx code to arch-imx
These declarations should not be in common.h. Move them to an
arch-specific header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 17 May 2017 14:23:06 +0000 (08:23 -0600)]
common: freescale: Move arch-specific declarations
The declarations should not be in common.h. Move them to the arch-specific
headers.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <trini@konsulko.com>