Emma Anholt [Sun, 11 Sep 2022 05:45:48 +0000 (22:45 -0700)]
nouveau: Fix compiler warnings about silly address checks in ir_print.
in/out/sv are arrays, so &array[i] is a non-null pointer. Presumably
numSysVals/Inputs/Outputs are only incremented when there's data in the
arrays, anyway.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18536>
Chia-I Wu [Tue, 30 Aug 2022 07:10:54 +0000 (00:10 -0700)]
turnip: reduce MAX_STORAGE_BUFFER_RANGE
Reduce MAX_STORAGE_BUFFER_RANGE from (1<<29) to (1<<27). While (1<<28)
is fine based on my tests, let's match what the latest version of the
blob does.
Tested on a618 and a635.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18322>
Karol Herbst [Tue, 13 Sep 2022 15:48:45 +0000 (17:48 +0200)]
rusticl/device: print error when libclc fails to load
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18580>
Alyssa Rosenzweig [Sun, 11 Sep 2022 15:07:50 +0000 (11:07 -0400)]
asahi: Handle blending with MRT
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Sat, 10 Sep 2022 21:56:10 +0000 (17:56 -0400)]
asahi: Don't crash on <4 channel render targets
It doesn't matter what we put in the swizzle for the unused components,
but if we try to stuff out-of-bounds PIPE_SWIZZLE_0/1/NONE values,
we'll crash in GenXML. Fixes failing tests in
dEQP-GLES3.functional.fragment_out.basic.fixed.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Sun, 11 Sep 2022 15:17:15 +0000 (11:17 -0400)]
agx: Don't use nir_find_variable_with_driver_location
io_semantics is the preferred alternative.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 21:01:10 +0000 (17:01 -0400)]
agx: Lower txs to a descriptor crawl
There's no native txs instruction... but we can emulate one :-) This is
heavy on shader ALU, but in the production driver, it'll all be hoisted
up to the preamble shader and so it shouldn't matter much. This
keeps the driver itself simple and low overhead, with a completely
obvious generalization to bindless.
Passes dEQP-GLES3.functional.shaders.texture_functions.texturesize.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 20:59:23 +0000 (16:59 -0400)]
agx: Implement load_global(_constant)
Found in compute shaders, maps to a subset of device_load, and will be
used for some lowerings soon.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 18:32:32 +0000 (14:32 -0400)]
agx: Implement txd
Handles all cases except for cube maps, which don't seem to work
properly, so those are lowered.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Thu, 8 Sep 2022 22:59:35 +0000 (18:59 -0400)]
agx: Implement texture offsets and comparators
Texture offsets and shadow comparison values get grouped into a vector
passed by register. Comparison values are provided as-is (fp32). Texture
offsets are packed into nibbles, but we can do this on the CPU, as
nonconstant offsets are forbidden in GLSL at least. They're also
forbidden in Vulkan/SPIR-V without ImageGatherExtended/
shaderImageGatherExtended. I'm happy kicking the NIR lowering can down
the line, this commit is complicated enough already.
Passes dEQP-GLES3.functional.shaders.texture_functions.texture.* and
dEQP-GLES3.functional.shaders.texture_functions.textureoffset.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 18:32:01 +0000 (14:32 -0400)]
agx: Make p_combine take a dynamic src count
For larger vectors.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 21:00:47 +0000 (17:00 -0400)]
agx,asahi: Implement nir_intrinsic_load_texture_base_agx
Save off what we pass to BIND_TEXTURE.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 20:59:56 +0000 (16:59 -0400)]
nir: Add nir_intrinsic_texture_base_agx sysval
For non-bindless textures, get the base address of the texture
descriptor array, so we can crawl descriptors in the shader. For
bindless, this isn't needed (since the bindless handle will be the
address itself).
jekstrand suggested the idea of the descriptor crawl. It worked out
pretty well, all considered.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Mon, 27 Jun 2022 14:19:47 +0000 (10:19 -0400)]
panfrost: Honour cso->req_local_mem
Fixes api.min_max_local_mem_size.
nir->info.shared_size can't be trusted in OpenCL.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18559>
Alyssa Rosenzweig [Tue, 5 Jul 2022 19:11:59 +0000 (15:11 -0400)]
panfrost: Respect buffer offset for OpenCL
This is so dumb. Panfrost port of
d98b82a1039 ("iris/cs: take buffer offsets
into account for CL")
Fixes buffer.sub_buffers_read_write
Fixes:
80b90a0f2b8 ("panfrost: Implement panfrost_set_global_binding")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18560>
Sarah Walker [Thu, 28 Jul 2022 09:05:57 +0000 (10:05 +0100)]
pvr: Update FWIF 3d and compute register structures
This matches changes made in FW 1.17.OS@6285007.
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18440>
Karmjit Mahil [Thu, 11 Aug 2022 14:33:45 +0000 (15:33 +0100)]
pvr: Emit cs words for load op on vkCmdBeginRenderPass().
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18569>
Sarah Walker [Fri, 27 May 2022 13:51:39 +0000 (14:51 +0100)]
pvr: Remove STRIP_RENDERING members from FWIF
This matches changes made in FW 1.17.OS@6256262.
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18490>
Rajnesh Kanwal [Thu, 11 Aug 2022 09:59:17 +0000 (10:59 +0100)]
pvr: Implement vkCmdDrawIndexedIndirect API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18486>
Rajnesh Kanwal [Fri, 5 Aug 2022 09:45:10 +0000 (10:45 +0100)]
pvr: Implement vkCmdDrawIndirect API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18486>
Eric Engestrom [Tue, 13 Sep 2022 08:16:19 +0000 (09:16 +0100)]
docs: move rusticl readme into docs/
And convert it from Markdown to rST.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18568>
Rajnesh Kanwal [Fri, 12 Aug 2022 15:23:05 +0000 (16:23 +0100)]
pvr: Implement vkGetPhysicalDeviceImageFormatProperties2 API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18487>
Georg Lehmann [Mon, 12 Sep 2022 09:50:21 +0000 (11:50 +0200)]
radv: Enable VK_EXT_load_store_op_none.
VK_ATTACHMENT_STORE_OP_NONE_EXT is already supported through
VK_KHR_dynamic_rendering.
It doesn't seem like we need to do anything special for
VK_ATTACHMENT_LOAD_OP_NONE_EXT.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7246
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18545>
David Heidelberg [Tue, 30 Aug 2022 16:03:21 +0000 (18:03 +0200)]
ci: uprev piglit 2022-09-08
Main change is new traces YAML format!
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Thu, 1 Sep 2022 20:50:38 +0000 (22:50 +0200)]
ci: introduce update_traces_checksum.py
Invoking this script takes checksums from all failed jobs and update
them in $driver-traces.yml files.
```
.gitlab-ci/bin/update_traces_checksum.py --rev $(git rev-parse HEAD)
```
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Wed, 7 Sep 2022 21:32:19 +0000 (23:32 +0200)]
ci: split ci_run_n_monitor into script and shared parts
These parts will be shared with the update checksum script.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Sat, 3 Sep 2022 22:35:01 +0000 (00:35 +0200)]
ci: export whole results/ directory for all traces jobs
We use `results/results.json.bz2` in `update_traces_checksum.py`.
Just few extra KiB.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Sat, 3 Sep 2022 18:54:40 +0000 (20:54 +0200)]
ci: performance traces: make use of no-perf label
Traces with label `no-perf` will be skipped in performance testing.
This commit adds the yq tool, which preprocesses the traces.yml file
before sending it to the piglit.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Sat, 3 Sep 2022 19:06:09 +0000 (21:06 +0200)]
ci: check traces.yml files with yamllint
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 20:23:07 +0000 (22:23 +0200)]
ci/crocus: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 20:10:32 +0000 (22:10 +0200)]
ci/i915: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 20:03:05 +0000 (22:03 +0200)]
ci/intel: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 19:43:33 +0000 (21:43 +0200)]
ci/radeonsi: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 19:25:49 +0000 (21:25 +0200)]
ci/panfrost: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 19:14:07 +0000 (21:14 +0200)]
ci/broadcom: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 19:01:25 +0000 (21:01 +0200)]
ci/lavapipe: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 18:59:05 +0000 (20:59 +0200)]
ci/llvmpipe: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 18:43:44 +0000 (20:43 +0200)]
ci/virgl: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Sat, 20 Aug 2022 21:59:46 +0000 (23:59 +0200)]
ci/freedreno: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
Karmjit Mahil [Fri, 26 Aug 2022 15:15:21 +0000 (16:15 +0100)]
pvr: Handle VK_CULL_MODE_FRONT_AND_BACK.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18550>
Samuel Pitoiset [Mon, 29 Aug 2022 16:38:01 +0000 (18:38 +0200)]
radv: advertise extendedDynamicState2PatchControlPoints
For less stuttering with Zink, also required by Zink for full GPL.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6584
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 15:11:57 +0000 (17:11 +0200)]
radv: implement dynamic patch control points
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Mon, 29 Aug 2022 16:35:52 +0000 (18:35 +0200)]
radv: move emitting GE_CNTL for non-NGG pipelines from the cmdbuf
GE_CNTL is the equivalent of IA_MULTI_VGT_PARAM on GFX9 and older.
Calling this function for every draw shouldn't really hurt in practice
because only non-NGG pipelines need this.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Mon, 29 Aug 2022 16:27:52 +0000 (18:27 +0200)]
radv: move emitting PRIMGROUP_SIZE for <= GFX9 from the cmdbuf
The number of tessellation patches that is computed from the number
of patch control points might change dynamically too.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Mon, 29 Aug 2022 16:12:23 +0000 (18:12 +0200)]
radv: pass the number of patch control points to si_get_ia_multi_vgt_param()
To prepare for dynamic patch control points.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 14:39:22 +0000 (16:39 +0200)]
radv: add ABI lowering support for dynamic patch control points
The number of patch control points (TCS) and the number of patches
(TCS/TES) is read from user SGPRs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 15:05:11 +0000 (17:05 +0200)]
radv: add shader arguments for dynamic patch control points
This introduces two new user SGPRS:
- tcs_offchip_layout: input patch size and number of patches in TCS
- tes_num_patches: number of patches in TES
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 15:49:34 +0000 (17:49 +0200)]
aco: prevent a division by zero when patch control points is dynamic
tess_input_vertices is zero if the state is dynamic.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Wed, 31 Aug 2022 13:01:02 +0000 (15:01 +0200)]
radv: set workgroup_size to 256 when patch control points is dynamic
It's the maximum possible value. This is to ensure that compilers
don't optimize away barriers, like in ACO when workgroup_size is less
than or equal to wave_size, s_barrier is considered a no-op.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Wed, 31 Aug 2022 13:00:43 +0000 (15:00 +0200)]
radv: skip computing some tess info when patch control points is dynamic
We don't know the value.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 14:34:14 +0000 (16:34 +0200)]
radv: add radv_pipeline_key::dynamic_patch_control_points
This will be used to compile different tessellation shaders when
patch control points is dynamic.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Wed, 31 Aug 2022 09:16:05 +0000 (11:16 +0200)]
radv: emit the LDS size for TCS directly from the pipeline on GFX9+
To be consistent with the LDS shader config for LS, and this will
be emitted from the cmdbuf for dynamic patch control points.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Wed, 31 Aug 2022 09:00:10 +0000 (11:00 +0200)]
radv: reword a comment about dynamic states when rasterization is disabled
Make it more generic instead of listing all states.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Erik Faye-Lund [Mon, 12 Sep 2022 12:12:29 +0000 (14:12 +0200)]
docs/zink: document rgtc requirement
OpenGL 3.0 requires RGTC support, and until we have emulation in place,
we should document that requirement.
Fixes:
d50e8554b99 ("zink: add feature-documentation")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18549>
Samuel Pitoiset [Thu, 1 Sep 2022 10:18:54 +0000 (12:18 +0200)]
radv: upload the PS epilog in the existing pipeline BO
This reduces the number of BOs needed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18363>
Samuel Pitoiset [Thu, 1 Sep 2022 10:14:11 +0000 (12:14 +0200)]
radv: store the binary to radv_shader_part
This is currently always freed after the upload but this will allow
to upload the PS epilog later.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18363>
Samuel Pitoiset [Thu, 1 Sep 2022 09:33:40 +0000 (11:33 +0200)]
radv: split upload_shader_part() in two parts
One that creates the radv_shader_part object and one that uploads it.
This will be used to upload the PS epilogs as part of the existing
pipeline BO.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18363>
Samuel Pitoiset [Thu, 1 Sep 2022 09:55:49 +0000 (11:55 +0200)]
radv: store the VS prologs/PS epilogs VA at upload time
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18363>
Samuel Pitoiset [Mon, 12 Sep 2022 06:18:37 +0000 (08:18 +0200)]
radv/ci: re-enable dEQP-VK.renderpass2.depth_stencil_resolve.*_samplemask
Since RADV switched to 100% dynamic rendering, image transitions for
attachments not used in a subpass are correctly performed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18542>
Samuel Pitoiset [Thu, 1 Sep 2022 11:56:34 +0000 (13:56 +0200)]
radv: add a pointer to radv_shader_binary in radv_shader
With GPL, we will have to keep the shader binary in the library for
uploading it later, so it's easier to have a pointer in radv_shader.
The shader binary will be freed when the library is destroyed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18515>
Caio Oliveira [Sat, 10 Sep 2022 18:09:15 +0000 (11:09 -0700)]
intel/compiler: Use brw_ud* helpers in thread payload code
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 9 Sep 2022 23:52:10 +0000 (16:52 -0700)]
intel/compiler: Add a few more brw_ud* helpers
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 30 Aug 2022 00:13:00 +0000 (17:13 -0700)]
intel/compiler: Make thread_payload struct abstract
Each shader stage has its own struct and will instantiate it, so the
base class doesn't need to be instantiated anymore.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 23 Aug 2022 04:47:02 +0000 (21:47 -0700)]
intel/compiler: Create and use struct for CS thread payload
Move subgroup_id, that's only used by CS for verx10 < 125, as part of
the payload too -- even though is not, strictly speaking.
Note the thread execution of Task/Mesh is similar enough, so we make
their common struct inherit from cs_thread_payload.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 30 Aug 2022 07:47:32 +0000 (00:47 -0700)]
intel/compiler: Export brw_get_subgroup_id_param_index()
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 26 Aug 2022 00:00:15 +0000 (17:00 -0700)]
intel/compiler: Create and use struct for Bindless thread payload
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 23 Aug 2022 06:02:34 +0000 (23:02 -0700)]
intel/compiler: Store start of ICP handles in GS thread payload struct
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 23 Aug 2022 05:23:17 +0000 (22:23 -0700)]
intel/compiler: Create and use struct for GS thread payload
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Mon, 22 Aug 2022 06:05:08 +0000 (23:05 -0700)]
intel/compiler: Create and use struct for TASK and MESH thread payloads
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Mon, 22 Aug 2022 04:22:12 +0000 (21:22 -0700)]
intel/compiler: Create and use struct for VS thread payload
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Mon, 22 Aug 2022 03:51:58 +0000 (20:51 -0700)]
intel/compiler: Create and use struct for TES thread payload
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Sat, 20 Aug 2022 00:31:37 +0000 (17:31 -0700)]
intel/compiler: Store start of ICP handles in TCS thread payload struct
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 19 Aug 2022 22:04:15 +0000 (15:04 -0700)]
intel/compiler: Store Primitive ID in TCS thread payload struct
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 19 Aug 2022 21:57:31 +0000 (14:57 -0700)]
intel/compiler: Store Patch URB output in TCS thread payload struct
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 19 Aug 2022 21:41:52 +0000 (14:41 -0700)]
intel/compiler: Create struct for TCS thread payload
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 19 Aug 2022 19:40:20 +0000 (12:40 -0700)]
intel/compiler: Use FS thread payload only for FS
Move the setup into the FS thread payload constructor. Consolidate
payload setup for that in brw_fs_thread_payload.cpp file.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 19 Aug 2022 19:18:21 +0000 (12:18 -0700)]
intel/compiler: Make a type for Thread Payload and FS variant
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Jordan Justen [Mon, 8 Nov 2021 22:20:24 +0000 (14:20 -0800)]
intel/devinfo: Add MTL platforms enums and intel_device_info_is_mtl()
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18482>
Alyssa Rosenzweig [Sat, 10 Sep 2022 20:08:13 +0000 (16:08 -0400)]
nir/lower_blend: Avoid emitting unnecessary fsats
The option struct passed to nir_lower_blend doesn't have a "blending
disabled" flag. Unless blending is skipped due to logic ops or
framebuffer formats, nir_lower_blend always blends, even if the blend
mode is "replace" (corresponding to the API level blend disable).
That's mostly okay, since NIR can optimize out the code, at the expense
of a little compile time. However, there's a catch: nir_lower_blend
emits fsat at the start of the shader (for UNORM framebuffers, or
fsat_signed for SNORM). We can expect hardware to saturate the input to
store_output itself, so these operations are redundant, but it's tricky
to optimize these instructions out otherwise. Don't even try: detect the
replace blend mode and don't call nir_blend in that case. Colour masking
is still applied as usual.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18535>
Timur Kristóf [Fri, 9 Sep 2022 16:26:15 +0000 (18:26 +0200)]
radv: Enable subgroup feature bits for mesh and task shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18520>
Timur Kristóf [Fri, 9 Sep 2022 16:35:09 +0000 (18:35 +0200)]
radv: Replace NV_mesh_shader macros with EXT.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18521>
Yiwei Zhang [Mon, 12 Sep 2022 18:00:50 +0000 (18:00 +0000)]
venus: avoid fixing pipeline if not derivative
Fixes:
33e791bc02a ("venus/pipeline: Ignore basePipelineHandle")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18555>
Yiwei Zhang [Mon, 12 Sep 2022 17:46:59 +0000 (17:46 +0000)]
venus: zero out the pipeline handles
We only have to zero out the handles on failure, which is missed. For
pipelines, we can just do it at the beginning for simplicity.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18555>
Yiwei Zhang [Mon, 12 Sep 2022 05:39:17 +0000 (05:39 +0000)]
venus: vn_ResetDescriptorPool to reset mutable type states
Fixes:
de5879447b4 ("Track bitset when create descriptor pool")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18555>
Yiwei Zhang [Mon, 12 Sep 2022 05:30:53 +0000 (05:30 +0000)]
venus: fix an oob in descriptor pool state restoration
Fixes:
de5879447b4 ("Track bitset when create descriptor pool")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18555>
Adam Jackson [Mon, 12 Sep 2022 18:37:50 +0000 (14:37 -0400)]
Revert "glx: Use XSaveContext, delete glxhash.c"
This reverts commit
057c58b39bae8317ffbec666366a526cb17d0160.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7242
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18556>
Pavel Ondračka [Sat, 27 Aug 2022 18:16:56 +0000 (20:16 +0200)]
r300: add special path for merging movs with the same source
This is quite rare but still helps few tesseract shaders and
is quite straightforward.
shader-db with RV530:
total instructions in shared programs: 135671 -> 135646 (-0.02%)
instructions in affected programs: 322 -> 297 (-7.76%)
helped: 13
HURT: 0
Reviewed-by: Filip Gawin <filip@gawin.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18288>
Pavel Ondračka [Thu, 11 Aug 2022 12:49:15 +0000 (14:49 +0200)]
r300: merge together MOV and MAD instructions
Assuming they write different channels of the same destination
and they share at least one source or one of the sources is
RC_FILE_NONE.
shader-db with RV530:
total instructions in shared programs: 136033 -> 135673 (-0.26%)
instructions in affected programs: 22987 -> 22627 (-1.57%)
total temps in shared programs: 18977 -> 18965 (-0.06%)
temps in affected programs: 74 -> 62 (-16.22%)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6188
Reviewed-by: Filip Gawin <filip@gawin.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18288>
Pavel Ondračka [Fri, 26 Aug 2022 12:57:25 +0000 (14:57 +0200)]
r300: run copy propagate once more after merging channels
The previous pass can actually create some new movs that are eligible
for copy propagation. There is some minor inctruction and temps
improvement but the biggest win is a gained gnome-shell shader.
Nine more still fail with too many instructions though.
GAINED: shaders/gnome-shell-42/6-1.shader_test FS
shader-db with RV530:
total instructions in shared programs: 136382 -> 135538 (-0.62%)
instructions in affected programs: 31021 -> 30177 (-2.72%)
total temps in shared programs: 18939 -> 18937 (-0.01%)
temps in affected programs: 563 -> 561 (-0.36%)
Reviewed-by: Filip Gawin <filip@gawin.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18288>
Tapani Pälli [Mon, 12 Sep 2022 10:18:39 +0000 (13:18 +0300)]
intel/compiler: fix assert from ver to verx10
Fixes:
027b8b42490 ("intel/compiler: Add helper for barrier message payload setup for gfx >= 125")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18546>
Jordan Justen [Thu, 8 Sep 2022 05:50:47 +0000 (22:50 -0700)]
intel/compiler: Use builder to allocate fs regs for gs control data bits
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18537>
Caio Oliveira [Sun, 11 Sep 2022 06:25:28 +0000 (23:25 -0700)]
intel/compiler: Use builder to allocate fs regs for TCS store output
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18537>
James Zhu [Mon, 29 Aug 2022 19:46:20 +0000 (15:46 -0400)]
amd/common: some ASICs with gfx9 use compute rings for render
Some ASICs with gfx9 use compute rings for render.
Fixes:
983223de5dc01f50 - ac/gpu_info: use the kernel-reported
GFX IP version to set gfx_level
-v2: update merge requests num
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18553>
Illia Polishchuk [Mon, 12 Sep 2022 07:36:17 +0000 (10:36 +0300)]
mesa: skip extra state updates for clear calls
The glClear call updates draw state in the same way as other draw calls
with _mesa_update_state func
If currently used shader uses textures, _mesa_update_state will try to
update the shader texture state
But if the texture not set yet, before glClear call, it will detect
incompleted texture and will create dummy texture with default values
(see the update_single_program_texture func).
And this will be complete waste of time for glClear
Closes: #7128
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18459>
Alyssa Rosenzweig [Sun, 11 Sep 2022 22:12:09 +0000 (18:12 -0400)]
pan/decode: Fix job cycle detection
We need to look at the job header pointers themselves, not the memory objects
that contain them, because there can be (and usually is) multiple jobs per BO.
Fixes:
3da8c9193c3 ("panfrost: Handle Job VA cycles when decoding a dump file")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18539>
Iago Toral Quiroga [Mon, 12 Sep 2022 08:54:52 +0000 (10:54 +0200)]
v3dv: expose VK_EXT_primitive_topology_list_restart
The hw supports restarts of list primmitives and we pass
all the relevant CTS tests.
We don't advertise patch list restarts because we don't support
tessellation shaders yet.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18544>
Oleksii Bozhenko [Thu, 8 Sep 2022 19:45:45 +0000 (22:45 +0300)]
anv: Allow aliasing with modifiers for WSI images
Ignore ALIAS_BIT when format comes from WSI because
we have the ability to bind the MEMORY_BINDING_PRIVATE
from the other WSI image.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7019
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18347>
Oleksii Bozhenko [Thu, 8 Sep 2022 19:44:40 +0000 (22:44 +0300)]
vulkan/wsi: Pass wsi_image_create_info into anv_GetPhysicalDeviceImageFormatProperties2
Signed-off-by: Oleksii Bozhenko <oleksii.bozhenko@globallogic.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18347>
Karmjit Mahil [Mon, 28 Mar 2022 12:02:44 +0000 (13:02 +0100)]
pvr: Add mid fragment pipeline barrier if needed.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18124>
Karmjit Mahil [Thu, 17 Mar 2022 11:25:54 +0000 (11:25 +0000)]
pvr: Implement clear ppp state emission from template.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18124>