Iago Toral Quiroga [Fri, 25 Feb 2022 08:18:34 +0000 (09:18 +0100)]
broadcom/compiler: don't sort nodes for register allocation
Nodes are allocated in order to registers so initially sorting
was used to ensure that nodes with smaller life ranges would
be assigned first and therefore be more likely to get
accumulators.
However, since
d81a6e5f1d now we don't rely on order to make
decisions about accumulators and instead we make policy decisions
based on actual liveness, so sorting is no longer strictly
relevant to this decision.
Furthermore, we are not re-sorting nodes after each spill either,
since that would probably require that we rebuild the interference
graph after each spill (the graph identifies nodes by their index).
Shader-db results show a significant improvement in instruction
counts, due to more optimal accumulator assignments. The reason for
this is that we use a round-robin policy for choosing the next
accumulator to assign. The idea behind this is preventing nearby
temps to be assigned to the same accumulator so that QPU scheduling
is more flexible, but if we sort our nodes, we are basically not
assigning temps in program order any more and the round-robin policy
becomes less effective:
total instructions in shared programs:
13000420 ->
12663189 (-2.59%)
instructions in affected programs:
11791267 ->
11454036 (-2.86%)
helped: 62890
HURT: 19987
total threads in shared programs: 415874 -> 415870 (<.01%)
threads in affected programs: 20 -> 16 (-20.00%)
helped: 2
HURT: 4
total uniforms in shared programs: 3711652 -> 3711624 (<.01%)
uniforms in affected programs: 43430 -> 43402 (-0.06%)
helped: 134
HURT: 173
total max-temps in shared programs: 2144876 -> 2138822 (-0.28%)
max-temps in affected programs: 123334 -> 117280 (-4.91%)
helped: 4112
HURT: 1195
total spills in shared programs: 3870 -> 3860 (-0.26%)
spills in affected programs: 1013 -> 1003 (-0.99%)
helped: 14
HURT: 12
total fills in shared programs: 5560 -> 5573 (0.23%)
fills in affected programs: 1765 -> 1778 (0.74%)
helped: 14
HURT: 17
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>
Iago Toral Quiroga [Wed, 23 Feb 2022 08:58:33 +0000 (09:58 +0100)]
broadcom/compiler: sink uniform loads
total instructions in shared programs:
13014428 ->
13000420 (-0.11%)
instructions in affected programs: 743624 -> 729616 (-1.88%)
helped: 1392
HURT: 611
total threads in shared programs: 415858 -> 415874 (<.01%)
threads in affected programs: 16 -> 32 (100.00%)
helped: 8
HURT: 0
total uniforms in shared programs: 3720410 -> 3711652 (-0.24%)
uniforms in affected programs: 113442 -> 104684 (-7.72%)
helped: 635
HURT: 29
total max-temps in shared programs: 2154268 -> 2144876 (-0.44%)
max-temps in affected programs: 61279 -> 51887 (-15.33%)
helped: 1124
HURT: 187
total spills in shared programs: 4002 -> 3870 (-3.30%)
spills in affected programs: 265 -> 133 (-49.81%)
helped: 6
HURT: 0
total fills in shared programs: 5788 -> 5560 (-3.94%)
fills in affected programs: 603 -> 375 (-37.81%)
helped: 6
HURT: 0
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>
Iago Toral Quiroga [Mon, 21 Feb 2022 12:03:54 +0000 (13:03 +0100)]
broadcom/compiler: move constants before their first user
For us they are basically uniforms too so we want to make their
lifespans short to facilitate allocating them to accumulators.
total instructions in shared programs:
13043585 ->
13015385 (-0.22%)
instructions in affected programs: 8326040 -> 8297840 (-0.34%)
helped: 24939
HURT: 19894
total threads in shared programs: 415860 -> 415858 (<.01%)
threads in affected programs: 4 -> 2 (-50.00%)
helped: 0
HURT: 1
total uniforms in shared programs: 3721953 -> 3720451 (-0.04%)
uniforms in affected programs: 96134 -> 94632 (-1.56%)
helped: 744
HURT: 435
total max-temps in shared programs: 2173431 -> 2154260 (-0.88%)
max-temps in affected programs: 264598 -> 245427 (-7.25%)
helped: 10858
HURT: 841
total spills in shared programs: 4005 -> 4010 (0.12%)
spills in affected programs: 700 -> 705 (0.71%)
helped: 5
HURT: 10
total fills in shared programs: 5801 -> 5817 (0.28%)
fills in affected programs: 1346 -> 1362 (1.19%)
helped: 6
HURT: 11
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>
Iago Toral Quiroga [Mon, 21 Feb 2022 10:43:48 +0000 (11:43 +0100)]
broadcom/compiler: disallow TMU spills if max tmu spills is 0
If we are compiling with a strategy that does not allow TMU spills
we should not allow spilling anything that is not a uniform.
Otherwise the RA cost/benefit algorithm may choose to spill a
temp that is not uniform and that will cause us to immediately
fail the strategy and fallback to the next one, even if we
could've instead chosen to spill more uniforms to compile the
program successfully with that strategy.
Some relevant shader-db stats:
total instructions in shared programs:
13040711 ->
13043585 (0.02%)
instructions in affected programs: 234238 -> 237112 (1.23%)
helped: 73
HURT: 172
total threads in shared programs: 415664 -> 415860 (0.05%)
threads in affected programs: 196 -> 392 (100.00%)
helped: 98
HURT: 0
total uniforms in shared programs: 3717266 -> 3721953 (0.13%)
uniforms in affected programs: 12831 -> 17518 (36.53%)
helped: 6
HURT: 100
total max-temps in shared programs: 2174177 -> 2173431 (-0.03%)
max-temps in affected programs: 4597 -> 3851 (-16.23%)
helped: 79
HURT: 21
total spills in shared programs: 4010 -> 4005 (-0.12%)
spills in affected programs: 55 -> 50 (-9.09%)
helped: 5
HURT: 0
total fills in shared programs: 5820 -> 5801 (-0.33%)
fills in affected programs: 186 -> 167 (-10.22%)
helped: 5
HURT: 0
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>
Iago Toral Quiroga [Mon, 21 Feb 2022 09:42:12 +0000 (10:42 +0100)]
broadcom/compiler: increase cost of TMU spills to 10
Our cost was 5 which matches the number of instructions we have to
add for a TMU spill (a fill is 4 instructions).
Uniform spills on the other hand add an extra instruction for each
fill and remove one instruction for the spill itself. These have
a cost of 1.
Therefore, if we have a single spill+fill, we end up with +9
instructions if it is a TMU spill and +0 instructions with a uniform
spill, so making the former only 5 times more costly is probably
not a good idea, and this is without even considering the added
latency of the TMU accesses.
Relevant shader-db changes show this causes as a marginal instruction
count increase in a few shaders but better thread counts and lower
TMU spilling overall:
total instructions in shared programs:
13037315 ->
13040711 (0.03%)
instructions in affected programs: 370106 -> 373502 (0.92%)
helped: 187
HURT: 321
total threads in shared programs: 415090 -> 415664 (0.14%)
threads in affected programs: 574 -> 1148 (100.00%)
helped: 287
HURT: 0
total uniforms in shared programs: 3706674 -> 3717266 (0.29%)
uniforms in affected programs: 63075 -> 73667 (16.79%)
helped: 40
HURT: 395
total max-temps in shared programs: 2176080 -> 2174177 (-0.09%)
max-temps in affected programs: 15838 -> 13935 (-12.02%)
helped: 316
HURT: 34
total spills in shared programs: 4247 -> 4010 (-5.58%)
spills in affected programs: 2599 -> 2362 (-9.12%)
helped: 107
HURT: 14
total fills in shared programs: 6121 -> 5820 (-4.92%)
fills in affected programs: 3622 -> 3321 (-8.31%)
helped: 108
HURT: 13
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15168>
Marek Olšák [Mon, 28 Feb 2022 20:37:48 +0000 (15:37 -0500)]
radeonsi: fix an assertion failure with register shadowing
The problem is that dirty_states must be 0 for any state that is NULL
in "queued". This code was flagging dirty_states for such states because
it was only looking at "emitted". It should have been looking at "queued".
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>
Marek Olšák [Sun, 27 Feb 2022 03:37:14 +0000 (22:37 -0500)]
radeonsi: fix register shadowing after the pm4 state size was decreased
Fixes:
946bd90a097e8 "radeonsi: decrease the size of si_pm4_state::pm4 except for cs_preamble_state"
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>
Marek Olšák [Tue, 1 Mar 2022 15:36:37 +0000 (10:36 -0500)]
ac: add an environment variable that parses IBs in files
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>
Marek Olšák [Tue, 1 Mar 2022 15:38:08 +0000 (10:38 -0500)]
ac: define PKT3_ATOMIC_MEM
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>
Marek Olšák [Wed, 23 Feb 2022 02:40:59 +0000 (21:40 -0500)]
ac: parse SET_SH_REG_INDEX packet
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>
Marek Olšák [Wed, 28 Jul 2021 15:18:59 +0000 (11:18 -0400)]
ac/llvm: update LLVM processor names for gfx10.3
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15209>
Marek Olšák [Tue, 1 Mar 2022 21:08:42 +0000 (16:08 -0500)]
ci: add point coord failures to d3d12
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Sat, 1 Jan 2022 10:50:05 +0000 (05:50 -0500)]
st/mesa: do nir_lower_io() for inputs & outputs with transform feedback info
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Mon, 3 Jan 2022 04:37:15 +0000 (23:37 -0500)]
gallium/aux: add helper nir_gather_stream_output_info
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Mon, 3 Jan 2022 10:42:08 +0000 (05:42 -0500)]
gallium/util: add util_dump_stream_output_info
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Tue, 4 Jan 2022 17:34:23 +0000 (12:34 -0500)]
nir: pass nir_shader into nir_recompute_io_bases instead of func_impl
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Mon, 3 Jan 2022 10:41:53 +0000 (05:41 -0500)]
nir: add nir_print_xfb_info
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Mon, 3 Jan 2022 04:38:00 +0000 (23:38 -0500)]
nir: add nir_gather_xfb_info_from_intrinsics for lowered IO
Drivers will use this.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Sat, 1 Jan 2022 10:32:14 +0000 (05:32 -0500)]
nir: add nir_lower_io_passes() with new transform feedback
moved from radeonsi without the vectorization, which won't be needed for
now. We will lower IO in st/mesa instead of radeonsi to get the transform
feedback info into store instructions.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Mon, 3 Jan 2022 00:46:45 +0000 (19:46 -0500)]
nir: add nir_io_semantics::no_varying, no_sysval_output, and helpers
This is for drivers that have separate store instructions for varyings,
system value outputs (such as clip distances), and transform feedback.
The flags tell the driver not to store the output to those locations.
This will be used by radeonsi initially, and then maybe by a new linker.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Sun, 19 Dec 2021 21:23:42 +0000 (16:23 -0500)]
nir: scalarize transform feedback info in nir_lower_io_to_scalar
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Sat, 1 Jan 2022 11:18:56 +0000 (06:18 -0500)]
nir: add shader_info::xfb_strides
NIR now fully contains pipe_stream_output_info in shader_info and IO
intrinsics if lower_io_variables is true. radeonsi will not use
pipe_stream_output_info after this, and other drivers are free to follow
that.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Sun, 19 Dec 2021 19:20:52 +0000 (14:20 -0500)]
nir: add transform feedback info into nir_intrinsic_store_output
This will allow compaction of transform feedback varyings because they
are no longer tied to varying slots with this information.
It will also make transform feedback info available to all NIR passes
after IO is lowered. It's meant to replace pipe_stream_output_info.
Other intrinsics are not used with transform feedback.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Sun, 2 Jan 2022 04:11:00 +0000 (23:11 -0500)]
nir: fix nir_io_semantics::gs_streams in nir_lower_io_to_scalar
gs_streams is relative to the component. Also clear the high bits.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Sun, 19 Dec 2021 20:32:08 +0000 (15:32 -0500)]
nir: validate write_mask for all intrinsics that have it
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14388>
Marek Olšák [Tue, 22 Feb 2022 21:46:28 +0000 (16:46 -0500)]
radeonsi: fix broken VK-GL buffer interop
Fixes:
ad9b5ac0a18 - radeonsi: more fixes for si_buffer_from_winsys_buffer for GL-VK interop
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6063
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15124>
Nanley Chery [Fri, 25 Feb 2022 01:16:37 +0000 (17:16 -0800)]
anv: Disable aux if the explicit modifier lacks it
For dmabuf imports, configure the primary surface without support for
compression if the modifier doesn't specify it. This helps to create VkImages
with memory requirements that are compatible with the buffers apps provide.
Suggested-by: Philip Langdale <philipl@overt.org>
Cc: 22.0 <mesa-stable>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5940
Tested-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15181>
Nanley Chery [Fri, 25 Feb 2022 17:50:13 +0000 (09:50 -0800)]
anv: Refactor anv_image_init_from_create_info
Use a variable to store the anv_image_create_info struct. We'll modify it for a
bug fix in the next patch.
Cc: 22.0 <mesa-stable>
Tested-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15181>
Nanley Chery [Fri, 25 Feb 2022 01:17:49 +0000 (17:17 -0800)]
anv: Change a parameter of the implicit layout fn
Replace the create_info parameter with isl_extra_usage_flags to more closely
match the parameters of explicit layout function.
Tested-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15181>
Alyssa Rosenzweig [Tue, 1 Mar 2022 19:14:12 +0000 (14:14 -0500)]
pan/va: Add missing copyright notice
Minor.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Fri, 19 Nov 2021 20:51:13 +0000 (15:51 -0500)]
pan/bi: Extract INSTRUCTION_CASE macro
Useful across multiple optimization tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Tue, 27 Jul 2021 00:19:48 +0000 (20:19 -0400)]
pan/bi: Adapt bi_lower_branch for Valhall
Disable the Bifrost optimization; it's not portable.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Mon, 2 Aug 2021 16:30:03 +0000 (12:30 -0400)]
pan/bi: Trade off registers/threads on Valhall
It's only v6 that's missing this feature.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Wed, 11 Aug 2021 20:34:46 +0000 (16:34 -0400)]
pan/bi: Add BI_SUBGROUP_SUBGROUP16 option
Valhall uses 16-wide warps.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Tue, 1 Mar 2022 19:13:53 +0000 (14:13 -0500)]
pan/bi: Wire Valhall disassembler into compiler
Useful when we grow Valhall support (soon!)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Mon, 22 Nov 2021 00:01:31 +0000 (19:01 -0500)]
pan/bi: Support standalone Valhall disassembly
$ bifrost_compiler disasm --gpu=G78 foo.bin
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Sun, 12 Dec 2021 21:45:16 +0000 (16:45 -0500)]
pan/bi: Allow CSE of preloaded registers
Needed to CSE `LEA_VARY` in varying shaders on Valhall.
No shader-db changes on Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Wed, 22 Dec 2021 18:22:21 +0000 (13:22 -0500)]
pan/bi: Use a progress loop for constant folding
Needed to fold the dependent patterns produced by texture instructions
during NIR->Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Sun, 9 Jan 2022 21:01:09 +0000 (16:01 -0500)]
pan/bi: Mark NOP as having no destinations
More accurate and more convenient.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Sun, 23 Jan 2022 21:09:18 +0000 (16:09 -0500)]
panfrost: Unify barrier+helper handling
These are unified in the hardware, so let's unify them in pan_shader_info.
Hoisting this logic to pan_shader.c avoids the need to duplicate this logic for
Midgard/Bifrost (RSD packing) and Valhall (SPD packing).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Tue, 1 Mar 2022 19:18:51 +0000 (14:18 -0500)]
panfrost: Set texel_interleave on Valhall
Instead of specifying the tiling on the texture descriptor, Valhall specifies it
on the plane descriptor. There is a new flag on the texture descriptor
specifying only whether the planes are interleaved or not.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Fri, 25 Feb 2022 21:42:28 +0000 (16:42 -0500)]
panfrost: Adapt estimate_texture_payload_size to Valhall
The plane descriptor is larger than earlier surface descriptors, so we need to
be somewhat careful here. This removes a memory micro-optimization in the
interest of simplifying the code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Thu, 3 Feb 2022 15:50:34 +0000 (10:50 -0500)]
panfrost: Don't emit compression tags on Valhall
Unnecessary. To avoid even more #if/#endif soup, merge the v4, v5-v8, and v9
paths together -- by returning 0 as the compression tag on v4 or v9.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Fri, 19 Nov 2021 04:38:50 +0000 (23:38 -0500)]
panfrost: Allow uploading fragment SPDs
SPDs don't have the state dependence that fragment RSDs do.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Sat, 29 Jan 2022 15:16:21 +0000 (10:16 -0500)]
panfrost: Don't pack blend constants with blend shaders
It's probably harmless, but it is logically meaningless. The DDK doesn't do it,
I don't see a reason for us to, either. In theory this should be a small
overhead win.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Fri, 28 Jan 2022 22:05:45 +0000 (17:05 -0500)]
panfrost: Generalize some is_bifrost users
Valhall would want these too. Regretting the is_bifrost check at all..
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Fri, 28 Jan 2022 21:18:34 +0000 (16:18 -0500)]
panfrost: Add PAN_MESA_DEBUG=dump option
To dump all graphics memory via the new pandecode_dump_mappings function(),
since for Valhall I have to do this often enough to warrant a dynamic flag.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Fri, 19 Nov 2021 04:37:41 +0000 (23:37 -0500)]
panfrost: Rename prepare_rsd->prepare_shader
This hook will be repurposed on Valhall to prepare the Shader Program
Descriptor, which takes the role of the RSD. Rename to avoid confusion.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Sat, 11 Dec 2021 23:08:47 +0000 (18:08 -0500)]
panfrost: Add an enum for Valhall resource tables
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Fri, 25 Feb 2022 20:15:35 +0000 (15:15 -0500)]
panfrost: Make Divisor E an integer on v9
For consistency with previous architecture's XML files. Logically this is an
1-bit unsigned integer, not a boolean.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Thu, 3 Feb 2022 00:43:10 +0000 (19:43 -0500)]
panfrost: Clarify contains descriptor? bit
Influences cache prefetching. I don't see a good reason to put anything other
than descriptors inside shader resources, meaning always setting this bit is
appropriate (at least for GLES).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Thu, 3 Feb 2022 00:29:35 +0000 (19:29 -0500)]
panfrost: Remove Invalidate Cache from Valhall job header
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Wed, 2 Feb 2022 23:31:18 +0000 (18:31 -0500)]
panfrost: Add Tile Render Order enum to fragment jobs
Not sure what this is needed for yet.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Alyssa Rosenzweig [Sun, 9 Jan 2022 18:38:23 +0000 (13:38 -0500)]
panfrost: Extend SPD size
There is software-defined state at the end we don't need. Model in the XML for
correct behaviour.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>
Thong Thai [Fri, 25 Feb 2022 17:12:07 +0000 (12:12 -0500)]
radeonsi: add check for graphics to si_try_normal_clear
Cc: mesa-stable
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15177>
Lionel Landwerlin [Sat, 19 Feb 2022 22:00:48 +0000 (00:00 +0200)]
anv: fix fast clear type value with external images
Disable fast clear if not supported by the external modifier.
v2: Set fast_clear value to NONE in case of import/export from/to external
v3: Move logic next to existing acquire/release checks (Nanley)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6056
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15096>
Oleksandr Gabrylchuk [Thu, 24 Feb 2022 11:06:48 +0000 (12:06 +0100)]
venus: Implement guest vram blob type.
Add support of GUEST_VRAM type of blob. These are dedicated heap memory
allocations required for vk support on hypervisors that don't support
runtime injections of host memory into guest physical address space.
The flow of usage:
1) Host VM reserves dedicated heap memory
2) Device get info about memory reservations and report it to guest
using mmio registers
3) Guest virtio-gpu driver on starts checks mmio registers for
physical address and length of reserved region. Then it reserves it
in guest.
4) On each call of vkAllocateMemory() guest driver gets chunk of
required memory and send it to host using sg list. It uses one sg
entry for 1 blob call. Heap is managed on guest using drm memory
manager (drm_mm).
Signed-off-by: Oleksandr.Gabrylchuk <Oleksandr.Gabrylchuk@opensynergy.com>
Signed-off-by: Andrii Pauk <Andrii.Pauk@opensynergy.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14536>
Marek Olšák [Thu, 24 Feb 2022 16:46:51 +0000 (11:46 -0500)]
amd: update addrlib
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
Marek Olšák [Thu, 24 Feb 2022 15:25:23 +0000 (10:25 -0500)]
amd: add support for gfx1036 and gfx1037 chips
Both are identified as GFX1036 for simplicity.
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
Marek Olšák [Sat, 9 Oct 2021 01:24:02 +0000 (21:24 -0400)]
ac: set correct cache size per TCC for Yellow Carp
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
Samuel Pitoiset [Tue, 1 Mar 2022 13:16:24 +0000 (14:16 +0100)]
radv: disable DCC for Fable Anniversary, Dragons Dogma, GTA IV and more
Also Starcraft 2 and The Force Unleashed II.
These games are known to be affected by the feedback loop issue. We will
fix this properly soon but as a hotfix disabling DCC should be enough.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4424
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15203>
Vadym Shovkoplias [Mon, 20 Dec 2021 11:39:21 +0000 (13:39 +0200)]
iris: Do not apply SCANOUT allocation flags for SHARED-only requests
It provides similar solution as in [1].
This was workaround for the users of gbm_bo_create_with_modifiers(),
which were unable to specify the buffer usage (GPU / GPU+DISPLAY).
But after the commit [2] this become possible. And forcing usage to
GBM_BO_USE_SCANOUT migrated directly into gbm_bo_create_with_modifiers
[3], allowing us to remove such workarounds from the drivers.
[1]:
ef3b31c9 ("v3d: Don't force SCANOUT for PIPE_BIND_SHARED requests")
[2]:
268e12c6 ("gbm: add gbm_{bo,surface}_create_with_modifiers2")
[3]:
ad50b47a ("gbm: assume USE_SCANOUT in create_with_modifiers")
Suggested-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5642
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14264>
Timur Kristóf [Sun, 27 Feb 2022 17:46:59 +0000 (18:46 +0100)]
ac/nir: Extract final mesh shader output counts to a separate function.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
Timur Kristóf [Sun, 27 Feb 2022 17:41:24 +0000 (18:41 +0100)]
aco: Remove superfluous code for mesh shader workgroup ID.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
Timur Kristóf [Sun, 27 Feb 2022 17:41:10 +0000 (18:41 +0100)]
ac/nir: Properly invalidate mesh shader metadata.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
Timur Kristóf [Sun, 27 Feb 2022 17:40:36 +0000 (18:40 +0100)]
ac/nir: Fix workgroup ID in mesh shader waves other than the first.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
Timur Kristóf [Sun, 27 Feb 2022 17:39:01 +0000 (18:39 +0100)]
ac/nir: Store mesh shader API and HW workgroup size in lowering state.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
Timur Kristóf [Sun, 27 Feb 2022 16:59:21 +0000 (17:59 +0100)]
ac/nir: Reuse existing nir_builder for emit_ms_finale.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
Timur Kristóf [Sun, 27 Feb 2022 16:58:46 +0000 (17:58 +0100)]
ac/nir: Use vertex count minus 1 to determine max index in mesh shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>
Charlie Turner [Mon, 21 Feb 2022 12:38:25 +0000 (12:38 +0000)]
ci, valve: Add the dEQP runners for Valve CI
v2.
- Build the runner image as part of the CI for the boot2container
project, rather than as a manually step using the build instructions
in valve-trigger.dockerfile.
- Depend on a non-default kernel build hosted in the valve-infra
package repository. This does reduce the current caching feature of
local artifacts, but makes it easier to chop and change kernels on a
per-project or even per-test basis.
v3.
- Depend on a kernel built and stored in the valve-infra generic
package repo.
- Build the runner container using ci-templates as part of the CI in
valve-infra.
- Now that the runner container is built in the valve-infra CI, I
dropped the source import of client.py and message.py. They are
built in the runner container.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
Charlie Turner [Mon, 10 Jan 2022 18:46:25 +0000 (18:46 +0000)]
amd, ci: Categorize the sections of the CI file.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
Charlie Turner [Mon, 10 Jan 2022 18:45:40 +0000 (18:45 +0000)]
amd, ci: Drop log level in SPIRV -> NIR code generator.
See
786fa3435c for the rationale of this variable, but the point is to
avoid many error reports for conformance conformance issues within the
VK-CTS shaders.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
Charlie Turner [Mon, 10 Jan 2022 18:45:26 +0000 (18:45 +0000)]
amd, ci: Remove unused runners.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
Charlie Turner [Thu, 17 Feb 2022 09:49:32 +0000 (09:49 +0000)]
ci, valve: Add support scripts for the Valve bare-metal farm.
- Add the scripts to the prepared Mesa artifacts for use in later
runner stages.
- Add a template generator (generate_b2c.py) which reads and
validates (very lightly for now) the Gitlab job environment and then
spits out a YAML file describing the necessary test workload to be
sent to a Valve CI gateway.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>
Samuel Pitoiset [Mon, 21 Feb 2022 14:47:46 +0000 (15:47 +0100)]
radv: remove color exports in presence of holes
If there is holes, eg. if only MRT0 and MRT2 are exported, we have to
set MRT1 to SPI_SHADER_32_R to avoid a GPU hang but the export can
still be removed from the fragment shader.
fossils-db (Sienna Cichlid):
Totals from 565 (0.42% of 134913) affected shaders:
VGPRs: 13328 -> 11456 (-14.05%)
CodeSize: 613232 -> 548224 (-10.60%); split: -11.13%, +0.53%
LDS: 284672 -> 296960 (+4.32%)
MaxWaves: 17624 -> 17684 (+0.34%)
Instrs: 113056 -> 100445 (-11.15%); split: -11.68%, +0.53%
Latency: 684327 -> 639348 (-6.57%); split: -7.17%, +0.60%
InvThroughput: 122877 -> 104382 (-15.05%); split: -15.18%, +0.13%
VClause: 2601 -> 2323 (-10.69%); split: -10.77%, +0.08%
SClause: 5629 -> 5443 (-3.30%); split: -3.91%, +0.60%
Copies: 9393 -> 8720 (-7.16%); split: -8.22%, +1.05%
PreSGPRs: 14623 -> 13666 (-6.54%); split: -6.76%, +0.22%
PreVGPRs: 9847 -> 8503 (-13.65%)
fossils-db (Polaris10):
Totals from 565 (0.42% of 135960) affected shaders:
SGPRs: 28064 -> 27104 (-3.42%)
VGPRs: 12516 -> 10544 (-15.76%); split: -15.79%, +0.03%
CodeSize: 516920 -> 456536 (-11.68%); split: -11.68%, +0.00%
MaxWaves: 4369 -> 4418 (+1.12%)
Instrs: 97771 -> 85903 (-12.14%); split: -12.14%, +0.00%
Latency: 767482 -> 708545 (-7.68%); split: -7.97%, +0.29%
InvThroughput: 280017 -> 235744 (-15.81%)
VClause: 2270 -> 2090 (-7.93%); split: -8.50%, +0.57%
SClause: 5185 -> 5012 (-3.34%); split: -3.86%, +0.52%
Copies: 8328 -> 7555 (-9.28%); split: -9.35%, +0.07%
Branches: 1143 -> 1113 (-2.62%)
PreSGPRs: 13816 -> 12725 (-7.90%); split: -7.92%, +0.02%
PreVGPRs: 9707 -> 8270 (-14.80%)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15108>
Rhys Perry [Fri, 25 Feb 2022 17:40:16 +0000 (17:40 +0000)]
ac/nir: remove TCS nir_var_shader_out memory barrier
nir_var_shader_out writes are only used for later TES invocations, so I
don't think there's any need for the TCS workgroup to wait for them.
fossil-db (Sienna Cichlid):
Totals from 1691 (1.04% of 162293) affected shaders:
Instrs: 710699 -> 709008 (-0.24%)
CodeSize: 3830168 -> 3823404 (-0.18%)
Latency: 3396997 -> 3007934 (-11.45%)
InvThroughput: 1212094 -> 1082823 (-10.67%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15195>
Caio Oliveira [Tue, 15 Feb 2022 00:13:28 +0000 (16:13 -0800)]
intel/compiler: Lower Task/Mesh I/O before SIMD specific lowering
These are the same for all variants, so just lower it before cloning
the nir_shader for each of them.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15019>
Danylo Piliaiev [Thu, 10 Feb 2022 13:35:59 +0000 (15:35 +0200)]
turnip: Implement VK_EXT_physical_device_drm
Copied from ANV and V3DV.
v1. Fix a build error for clang "unannotated fall-through between switch labels"
( Hyunjun Ko <zzoon.ko@igalia.com> )
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6011
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14971>
Pierre-Eric Pelloux-Prayer [Thu, 24 Feb 2022 08:59:51 +0000 (09:59 +0100)]
radeonsi/drirc: use force_gl_vendor for Maya
Otherwise OpenCL initialization fails with "unknown vendor id 0".
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15151>
Ilia Mirkin [Mon, 31 Jan 2022 05:45:52 +0000 (00:45 -0500)]
nouveau: add dEQP/GLCTS run failure info for GF108/GT215
I happened to have these plugged in. Ran them against mesa 21.3 and
recent VK-GL-CTS tree (shortly after vulkan-cts-1.2.8).
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14797>
Nanley Chery [Thu, 17 Feb 2022 18:34:17 +0000 (10:34 -0800)]
Revert "anv: Require the local heap for CCS on XeHP"
This reverts commit
382f6ccda8869f72134dbfa9c3cc68a229e01138.
The spec requires that all color images created with the same tiling
(and a few other properties) support the same memoryTypeBits. So this
wasn't a valid change. It also wasn't necessary - we already have a
mechanism in anv_BindImageMemory2 for disabling compression if the BO
doesn't support it.
With this, XeHP passes the tests in
dEQP-VK.memory.requirements.*tiling_optimal
Fixes:
382f6ccd ("anv: Require the local heap for CCS on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>
Nanley Chery [Fri, 18 Feb 2022 00:20:00 +0000 (16:20 -0800)]
anv: Add a perf warning in anv_BindImageMemory2
It reports: "BO lacks implicit CCS. Disabling the CCS aux usage."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>
Nanley Chery [Thu, 17 Feb 2022 18:26:34 +0000 (10:26 -0800)]
anv: Fall back to HiZ when disabling CCS on HiZ+CCS
When an image configured for HIZ_CCS/HIZ_CCS_WT is bound to a BO lacking
implicit CCS, we disable any compression it may have had. Such images
are still compatible with ISL_AUX_USAGE_HIZ however. Fall back to that
aux usage to retain the performance benefit.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>
Nanley Chery [Thu, 17 Feb 2022 18:26:34 +0000 (10:26 -0800)]
anv: Don't disable HiZ/MCS in anv_BindImageMemory2
When an image is bound to a BO lacking implicit CCS, we disable any
compression it may have had. This is unnecessary in the cases where the
compression type doesn't depend on the BO having implicit CCS support.
Avoid this disabling for ISL_AUX_USAGE_MCS and ISL_AUX_USAGE_HIZ.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>
Connor Abbott [Mon, 21 Feb 2022 18:25:40 +0000 (19:25 +0100)]
ir3: Use isam for bindless images
In the bindless case, we don't have to keep any shadow descriptors and
can just reuse the IBO descriptor as a texture descriptor. Now that
we're emitting the swizzle we can just flip this on.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
Connor Abbott [Mon, 21 Feb 2022 18:24:39 +0000 (19:24 +0100)]
tu: Call nir_opt_access
This adds some small optimizations, and enables lowering to isam in more
cases where the app didn't specify readonly.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
Connor Abbott [Tue, 22 Feb 2022 10:35:55 +0000 (11:35 +0100)]
ir3/nir: Fix 1d array readonly images
ncoords includes the array index, and the NIR source has the array index
as its last component, so we have to insert the extra y coordinate in
the middle in this case.
Fixes: 0bb0cac ("freedreno/ir3: handle image buffer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
Connor Abbott [Mon, 21 Feb 2022 18:18:19 +0000 (19:18 +0100)]
ir3: Don't always set bindless_tex with readonly images
Fixes: 274f381 ("ir3: Plumb through bindless support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
Connor Abbott [Mon, 21 Feb 2022 18:12:03 +0000 (19:12 +0100)]
freedreno/fdl: Set swizzle on storage descriptor
It appears to be unused by ldib/stib, but it will let us use isam on IBO
descriptors for bindless images.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
Connor Abbott [Mon, 21 Feb 2022 18:05:52 +0000 (19:05 +0100)]
freedreno: Replace A6XX_IBO with A6XX_TEX_CONST
Since these were reverse-engineered, it's become clear that IBO
descriptors are just a subset of texture descriptors, and bindless reads
of readonly images actually use isam on the IBO descriptor, further
confirming that the two are always compatible, even if not all of the
texture fields exist for IBOs. It's pointless to have a separate type
for IBOs, and just leads to things getting out-of-sync unnecessarily
which has already happened. Just remove it and use TEX_CONST insted.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
Connor Abbott [Mon, 21 Feb 2022 17:42:49 +0000 (18:42 +0100)]
ir3: Use CAN_REORDER instead of NON_WRITEABLE
CAN_REORDER takes volatile into account, and is closer to what we
actually require to use texture instructions, which is that we can
arbitrarily reorder loads.
Fixes: aa93896 ("freedreno/ir3: adjust condition for when to use ldib")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
Danylo Piliaiev [Tue, 15 Feb 2022 15:08:14 +0000 (17:08 +0200)]
turnip: Set drmFormatModifierTilingFeatures
From Vulkan spec for VkDrmFormatModifierProperties2EXT:
"drmFormatModifierTilingFeatures is a bitmask of VkFormatFeatureFlagBits
that are supported by any image created with format and drmFormatModifier."
"The returned drmFormatModifierTilingFeatures must contain at least one bit."
"Therefore, if the returned drmFormatModifier is DRM_FORMAT_MOD_LINEAR,
then drmFormatModifierPlaneCount must equal the format planecount, and
drmFormatModifierTilingFeatures must be identical to the
VkFormatProperties2::linearTilingFeatures returned in the same pNext chain."
Relevant tests: dEQP-VK.drm_format_modifiers.*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15032>
Mike Blumenkrantz [Fri, 18 Feb 2022 14:44:45 +0000 (09:44 -0500)]
zink: add layer asserts for 3d imageview creation
make sure there's no other mishaps here in the future
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
Mike Blumenkrantz [Tue, 22 Feb 2022 21:10:05 +0000 (16:10 -0500)]
zink: more accurately clamp 3d fb surfaces to corresponding 2d target
if more than 1 layer is being bound, this is an array, otherwise it's just
regular 2d
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
Mike Blumenkrantz [Fri, 18 Feb 2022 14:43:24 +0000 (09:43 -0500)]
zink: clamp 3d/array shader images to lower dimensionality using layer counts
this creates the view type expected by the shader instead of doing weird stuff
like trying to create a 3D imageview with layers > 1
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
Mike Blumenkrantz [Fri, 18 Feb 2022 14:42:25 +0000 (09:42 -0500)]
zink: directly create surfaces for shader images
avoid the implicit clamping of fb surfaces in zink_create_surface()
in order to provide more granularity
no functional changes
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
Mike Blumenkrantz [Tue, 8 Feb 2022 16:03:48 +0000 (11:03 -0500)]
zink: restrict clear flushing on sampler/image bind to compute binds
this is otherwise going to be handled on the next renderpass start
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>
Mike Blumenkrantz [Wed, 23 Feb 2022 15:59:12 +0000 (10:59 -0500)]
zink: use VK_EXT_depth_clip_control when available
this saves a few ALUs in vertex stages
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15174>
Mike Blumenkrantz [Thu, 17 Feb 2022 15:36:05 +0000 (10:36 -0500)]
glx/drisw: handle GL_RESET_NOTIFICATION_STRATEGY
fixes (llvmpipe):
KHR-NoContext.gl45.robustness.lose_context_on_reset
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15061>
Mike Blumenkrantz [Thu, 3 Feb 2022 15:22:34 +0000 (10:22 -0500)]
zink: update psiz handling to fix xfb output
now when gl_PointSize and gl_PointSizeMESA are both present, the former
will be used for xfb with a new location and the latter will be
exported by the shader
fixes (zink):
GTF-GL46.gtf30.GL3Tests.transform_feedback.transform_feedback_builtins
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15184>
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