Roman Lebedev [Wed, 7 Dec 2022 23:27:29 +0000 (02:27 +0300)]
[NFC] Port all LoopUnroll tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:29 +0000 (02:27 +0300)]
[NFC] Port all LoopTransformWarning tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopSimplifyCFG tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopSimplify tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopRotate tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopReroll tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopPredication tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopLoadElim tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopInterchange tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopIdiom tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopFusion tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopFlatten tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopDistribute tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LoopDeletion tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LoopDataPrefetch tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LoopBoundSplit tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LoadStoreVectorizer tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LICM tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:25 +0000 (02:27 +0300)]
[NFC] Port all LCSSA tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:25 +0000 (02:27 +0300)]
[NFC] Port all JumpThreading tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:24 +0000 (02:27 +0300)]
[NFC] Port all InstSimplify tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:24 +0000 (02:27 +0300)]
[NFC] Port all InstMerge tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:24 +0000 (02:27 +0300)]
[NFC] Port all InstCombine tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:23 +0000 (02:27 +0300)]
[NFC] Port all IndVarSimplify tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:22 +0000 (02:27 +0300)]
[NFC] Port all IRCE tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:22 +0000 (02:27 +0300)]
[NFC] Port all GuardWidening tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:21 +0000 (02:27 +0300)]
[NFC] Port all GlobalOpt tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:21 +0000 (02:27 +0300)]
[NFC] Port all GlobalDCE tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:21 +0000 (02:27 +0300)]
[NFC] Port all GVNSink tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:21 +0000 (02:27 +0300)]
[NFC] Port all GVNHoist tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:20 +0000 (02:27 +0300)]
[NFC] Port all GVN tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:20 +0000 (02:27 +0300)]
[NFC] Port all FunctionSpecialization tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:20 +0000 (02:27 +0300)]
[NFC] Port all FunctionAttrs tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:19 +0000 (02:27 +0300)]
[NFC] Port all ForcedFunctionAttrs tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:19 +0000 (02:27 +0300)]
[NFC] Port all Float2Int tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:18 +0000 (02:27 +0300)]
[NFC] Port all DivRemPairs tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:18 +0000 (02:27 +0300)]
[NFC] Port all DeadStoreElimination tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:18 +0000 (02:27 +0300)]
[NFC] Port all DeadArgElim tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:18 +0000 (02:27 +0300)]
[NFC] Port all DFAJumpThreading tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:17 +0000 (02:27 +0300)]
[NFC] Port all CrossDSOCFI tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:17 +0000 (02:27 +0300)]
[NFC] Port all CorrelatedValuePropagation tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:17 +0000 (02:27 +0300)]
[NFC] Port all Coroutines tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:17 +0000 (02:27 +0300)]
[NFC] Port all ConstraintElimination tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:16 +0000 (02:27 +0300)]
[NFC] Port all ConstantHoisting tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:16 +0000 (02:27 +0300)]
[NFC] Port all CodeExtractor tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:16 +0000 (02:27 +0300)]
[NFC] Port all CanonicalizeFreezeInLoops tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:15 +0000 (02:27 +0300)]
[NFC] Port all CallSiteSplitting tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:15 +0000 (02:27 +0300)]
[NFC] Port all BlockExtractor tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:14 +0000 (02:27 +0300)]
[NFC] Port all Attributor tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:14 +0000 (02:27 +0300)]
[NFC] Port all ArgumentPromotion tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:13 +0000 (02:27 +0300)]
[NFC] Port all ADCE tests to `-passes=` syntax
Tue Ly [Wed, 7 Dec 2022 19:24:46 +0000 (14:24 -0500)]
[libc] Fix undefined behavior in UInt<>::shift_right.
Fix undefined behavior of left-shifting uint64_t by 64 in
`UInt<>::shift_right` implementation.
Reviewed By: michaelrj, sivachandra
Differential Revision: https://reviews.llvm.org/D139566
Akira Hatanaka [Wed, 16 Nov 2022 22:20:23 +0000 (14:20 -0800)]
Add support for a backdoor driver option that enables emitting header
usage information in JSON to a file
Each line in the file is a JSON object that has the name of the main
source file followed by the list of system header files included
directly or indirectly from that file.
For example:
{"source":"/tmp/foo.c",
"includes":["/usr/include/stdio.h", "/usr/include/stdlib.h"]}
To reduce the amount of data written to the file, only the system
headers that are directly included from a non-system header file are
recorded.
In order to emit the header information in JSON, it is necessary to set
the following environment variables:
CC_PRINT_HEADERS_FORMAT=json CC_PRINT_HEADERS_FILTERING=only-direct-system
The following combination is equivalent to setting CC_PRINT_HEADERS=1:
CC_PRINT_HEADERS_FORMAT=textual CC_PRINT_HEADERS_FILTERING=none
Differential Revision: https://reviews.llvm.org/D137996
Krzysztof Parzyszek [Wed, 7 Dec 2022 18:04:25 +0000 (10:04 -0800)]
[Bitcode(Reader|Writer)] Convert Optional to std::optional
bixia1 [Wed, 7 Dec 2022 20:54:50 +0000 (12:54 -0800)]
[mlir][sparse] Add dependence on bufferization.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D139571
Mahesh Ravishankar [Wed, 7 Dec 2022 01:00:37 +0000 (01:00 +0000)]
[mlir][Transforms] Simplify region before simplifying operation in CSE.
This covers more options for CSE. It also ensures that two operations
that have same operands but different regions to begin with, but same
regions after `simplifyRegions`, don't get both added to the list of
`knownValues`.
Fixes #59135
Differential Revision: https://reviews.llvm.org/D139490
Leonard Chan [Wed, 7 Dec 2022 23:09:53 +0000 (23:09 +0000)]
[compiler-rt][hwasan] Let CheckAddressSized eventually call HandleTagMismatch on Fuchsia
Any hwasan tag checking done through runtime calls like __hwasan_mem* or
__hwasan_load/store* currently raise a sigtrap on a tag mismatch. Hwasan
dumps as much information it knows on the tag mismatch by placing
important values in specific registers before the brk and encoding the
access information in the optional argument supplied to the brk. If the
platform hwasan runs on uses signal handlers, then users can see the
typical pretty hwasan error report, but Fuchsia doesn't use signal
handlers, so it's left up to the platform exception handler to print all
this encoded information.
This patch attempts to enter the regular error reporting path via
HandleTagMismatch if a new macro CAN_GET_REGISTERS is set. For now this
is only defined for Fuchsia + aarch64, but can be expanded for other
platforms.
Differential Revision: https://reviews.llvm.org/D139377
Johannes Doerfert [Tue, 4 Oct 2022 12:45:21 +0000 (05:45 -0700)]
[AMDGPU] Annotate the intrinsics to be default and nocallback
Differential Revision: https://reviews.llvm.org/D135155
Jakub Kuderski [Wed, 7 Dec 2022 22:21:41 +0000 (17:21 -0500)]
[mlir][arith] Fix comment typo. NFC.
Jakub Kuderski [Wed, 7 Dec 2022 22:15:55 +0000 (17:15 -0500)]
[mlir][arith] Rename addui_carry to addui_extended
The goal is to make the naming of the future `_extended` ops more
consistent. With unsigned addition, the carry value/flag and overflow
bit are the same, but this is not true when it comes to signed addition.
Also rename the second result from `carry` to `overflow`.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D139569
Jon Chesterfield [Wed, 7 Dec 2022 22:02:53 +0000 (22:02 +0000)]
[amdgpu] Reimplement LDS lowering
Renames the current lowering scheme to "module" and introduces two new
ones, "kernel" and "table", plus a "hybrid" that chooses between those three
on a per-variable basis.
Unit tests are set up to pass with the default lowering of "module" or "hybrid"
with this patch defaulting to "module", which will be a less dramatic codegen
change relative to the current. This reflects the sparsity of test coverage for
the table lowering method. Hybrid is better than module in every respect and
will be default in a subsequent patch.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D139433
Alexander Belyaev [Wed, 7 Dec 2022 17:30:36 +0000 (18:30 +0100)]
[mlir] Make patterns for folding tensor.empty optional.
At the moment, they are a part of EmptyOp::getCanonicalizationPatterns. When
extract_slice(tensor.empty) is rewritten as a new tensor.empty, it could
happen that we end up with two tensor.empty ops, since the original
tensor.empty can have two users. After bufferization such cases result in two
allocations.
Differential Revision: https://reviews.llvm.org/D139308
Simon Pilgrim [Wed, 7 Dec 2022 21:52:06 +0000 (21:52 +0000)]
[llvm-exegesis][x86] Add test coverage for Issue #38507
Ensure that the PBLENDVBrr0 destination register is never xmm0
Bran Hagger [Wed, 7 Dec 2022 10:00:15 +0000 (12:00 +0200)]
Enable kmpc_atomic functions for arm64
Define the same kmpc_atomic functions for arm and arm64 that are defined for x86 and x64.
Reviewed By: mstorsjo
Differential Revision: https://reviews.llvm.org/D139139
Chris Bieneman [Mon, 5 Dec 2022 20:21:41 +0000 (14:21 -0600)]
Generate DXIL Shader hash
DXIL shader bitcode is hashed and the hash is placed into the final
output object file in its own data part.
This change modifies the DXContainerGlobals pass to compute the shader
hash (just an MD5 of the bitcode) and put the shader hash data into a
global for the HASH part.
This also sets the hash flag as appropriate for if the hashed shader
contained debug information. There is additional handling required to
get debug information in shaders working correctly with our tooling,
but that will be addressed in subsequent patches.
Reviewed By: python3kgae
Differential Revision: https://reviews.llvm.org/D139357
Alexander Yermolovich [Wed, 7 Dec 2022 21:14:23 +0000 (13:14 -0800)]
Revert "[llvm][dwwarf] Change CU/TU index to 64-bit"
This reverts commit
5ebd28f3e56c00a739fda46c72c9e0f6528add87.
Alexander Yermolovich [Wed, 7 Dec 2022 21:14:11 +0000 (13:14 -0800)]
Revert "[DWARFLibrary] Add support to re-construct cu-index"
This reverts commit
a5bd76a6e3119af9dd9c1d8af89e2b89f5267deb.
Alexander Yermolovich [Wed, 7 Dec 2022 20:22:58 +0000 (12:22 -0800)]
[BOLT][DWARF] Don't create extra .debug_str_offsets contributions
With ThinLTO mutliple CUs can share the same .debug_str_offsets contribution. We
were creating a new one for each CU. This lead to a binary size increase.
Reviewed By: maksfb
Differential Revision: https://reviews.llvm.org/D139214
Alexander Yermolovich [Wed, 7 Dec 2022 00:07:59 +0000 (16:07 -0800)]
[DWARFLibrary] Add support to re-construct cu-index
Summary:
According to DWARF5 specification and gnu specification for DWARF4 the offset
entry in the CU/TU Index is 32 bits. This presents a problem when
.debug_info.dwo in DWP file grows beyond 4GB. The CU Index becomes partially
corrupted.
This diff adds manual parsing of .debug_info.dwo/.debug_abbrev.dwo to
reconstruct CU index in general, and TU index for DWARF5. This is a work around
until DWARF6 spec is finalized.
Next patch will change internal CU/TU struct to 64 bit, and change uses as
necessary. The plan is to land all the patches in one go after all are approved.
This patch originates from the discussion in: https://discourse.llvm.org/t/dwarf-dwp-4gb-limit/63902
Differential Revision: https://reviews.llvm.org/D137882
Alexander Yermolovich [Tue, 6 Dec 2022 00:37:26 +0000 (16:37 -0800)]
[llvm][dwwarf] Change CU/TU index to 64-bit
Summary:
Changed contribution data structure to 64 bit. I added the 32bit and 64bit
accessors to make it explicit where we use 32bit and where we use 64bit. Also to
make sure sure we catch all the cases where this data structure is used.
Craig Topper [Wed, 7 Dec 2022 20:57:04 +0000 (12:57 -0800)]
Revert "[RISCV] Return InstSeq from generateInstSeqImpl instead of using an output parameter. NFC"
This reverts commit
d24915207c631b7cf637081f333b41bc5159c700.
Thinking about this more this probably chewed up 100+ bytes of stack
for each recursive call. So this probably needs more thought. The
code simplification wasn't that much.
Matt Arsenault [Tue, 6 Dec 2022 23:51:16 +0000 (18:51 -0500)]
NVPTX: Cleanup check for denormal mode
Go through the common query and be explicit about the supported flush
type.
Matt Arsenault [Wed, 7 Dec 2022 00:45:17 +0000 (19:45 -0500)]
AMDGPU: Rename test functions and add some cases for consistency
Test all the permutations.
David Tenty [Wed, 7 Dec 2022 20:40:22 +0000 (15:40 -0500)]
Revert "[libunwind] Use .irp directives. NFC"
This reverts commit
8482e95f75d02227fbf51527680c0b5424bacb69, which breaks on AIX
due to unsupported psudeo-ops in the assembly.
Differential Revision: https://reviews.llvm.org/D139368
Nicolai Hähnle [Thu, 1 Dec 2022 11:24:01 +0000 (12:24 +0100)]
GISel/Combiner: maintain created instructions in a SetVector
This is not a correctness fix because the set is only used for debug
output. However, it helps avoid noise when looking at diffs between
compiler runs.
The set is only maintained with debug output enabled, so the added cost
should be acceptable.
Differential Revision: https://reviews.llvm.org/D139465
Koakuma [Wed, 7 Dec 2022 20:31:31 +0000 (15:31 -0500)]
[SPARC] Lower SELECT_CC to MOVr on 64-bit target whenever possible
On 64-bit target, when doing i64 SELECT_CC where one of the comparison operands
is a constant zero, try to fold the compare and MOVcc into a MOVr instruction.
For all integers, EQ and NE comparison are available, additionally for signed
integers, GT, GE, LT, and LE is also available.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D138922
Shilei Tian [Wed, 7 Dec 2022 20:28:20 +0000 (15:28 -0500)]
[NFC][Object] Include header `BitcodeReader.h` instead of using forward declaration for BitcodeModule
`BitcodeModule` is used as element of a vector in `IRSymtabFile`, while in the
header there is only a forward declaration. It will work if the header `BitcodeReader.h`
is included before including `IRObjectFile.h`. However, it is not always the case,
causing compilation error. This patch simply includes the header and remove the
forward declaration.
Reviewed By: tejohnson
Differential Revision: https://reviews.llvm.org/D139556
Brad Smith [Wed, 7 Dec 2022 20:22:28 +0000 (15:22 -0500)]
Revert "[SPARC] Mark the %g0 register as constant & use it to materialize zeros"
2 of the Sparc tests are now failing.
This reverts commit
2c41310fc146a1f609147c65ac5f30e5a57e84a8.
Craig Topper [Wed, 7 Dec 2022 20:25:30 +0000 (12:25 -0800)]
[RISCV] Without Zfh, promote f16 inputs before creating RISCVISD::FCVT_W(U)_RV64 nodes.
This allows us to remove a couple more Zfhmin isel patterns.
Roman Lebedev [Wed, 7 Dec 2022 19:53:08 +0000 (22:53 +0300)]
[NFC] Port all SimpleLoopUnswitch tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 19:42:54 +0000 (22:42 +0300)]
[NFC] Port all (but one) HotColdSplit tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 19:37:54 +0000 (22:37 +0300)]
[NFC] Port all CodeExtractor tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 19:31:04 +0000 (22:31 +0300)]
[NFC] Port all LoopIdiom tests to `-passes=` syntax
Nico Weber [Wed, 7 Dec 2022 20:14:36 +0000 (15:14 -0500)]
[gn build] Reformat all build files
Ran:
git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format
Javier Setoain [Mon, 7 Nov 2022 21:27:36 +0000 (21:27 +0000)]
[mlir] Add hoisting of transfer ops in affine loops
The only way to do this with the current hoisting strategy is by
lowering Affine to Scf first, but that prevents further passes on
Affine.
Differential Revision: https://reviews.llvm.org/D137600
bixia1 [Wed, 7 Dec 2022 16:57:40 +0000 (08:57 -0800)]
[mlir][sparse] Improve concatenate operation conversion for the case with annotated all dense result.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D139345
Nico Weber [Wed, 7 Dec 2022 20:03:16 +0000 (15:03 -0500)]
[clang] Tweak test to tolerate clang being called "clang" instead of "clang-15"
See also
af95441ba7f3ca6.
Craig Topper [Wed, 7 Dec 2022 19:58:30 +0000 (11:58 -0800)]
[RISCV] Promote f16 fp_to_int_sat with Zfhmin during lowering instead of isel.
We already have a custom handler for FP_TO_(S/U)INT_SAT. It's easy
enought to inject an FP_EXTEND in there.
Jacob Lambert [Wed, 7 Dec 2022 19:50:11 +0000 (11:50 -0800)]
[Driver][test] Fix test by creating empty archive instead of empty file
Differential Revision: https://reviews.llvm.org/D137275
James Y Knight [Mon, 21 Nov 2022 01:41:42 +0000 (20:41 -0500)]
[SPARC] Simplify instruction decoder.
After https://reviews.llvm.org/D137653 named sub-operands can be used
in the auto-generated instruction decoders. This allows the
auto-generated decoders to work properly, so all the hand-coded
decoders in the sparc target can be removed.
In some instances, a manually-written decoder had not been implemented
for an instruction, and thus that instruction was not decoded
properly. These have been fixed (and tests added).
Differential Revision: https://reviews.llvm.org/D137727
James Y Knight [Tue, 8 Nov 2022 22:11:04 +0000 (17:11 -0500)]
[TableGen] More named sub-operands work.
Commit
a538d1f13a13 first added support for named sub-operands in
CodeEmitterGen. We now add a few more features to that, enabling
further target cleanups.
1. Adds support for handling an EncoderMethod in a sub-operand in
CodeEmitterGen. Previously, the specified encoder of a sub-operand was
ignored, and only the default used.
2. Adds support for sub-operands in DecoderEmitter, along with support
for tied sub-operands.
The changes to the decoder required a few minor tweaks to a few
targets, where existing brokeness was exposed. In order to keep this
patch small, I left FIXMEs which will be addressed in upcoming
patches. (Except MIPS16, since its object file emission/decoding is
totally broken).
Differential Revision: https://reviews.llvm.org/D137653
Craig Topper [Wed, 7 Dec 2022 19:26:58 +0000 (11:26 -0800)]
[RISCV] Consolidate identical (fcopysign FPR32:, FPR16:) isel patterns. NFC
Rob Suderman [Wed, 7 Dec 2022 19:11:51 +0000 (11:11 -0800)]
[mlir][tosa] Fix tosa.resize for i48 accumulator
Implementation assumed a i32 accumulator. Fixed the implementation to
work with an i32 accumulator.
Reviewed By: NatashaKnk
Differential Revision: https://reviews.llvm.org/D139365
Keith Smiley [Wed, 7 Dec 2022 19:23:42 +0000 (11:23 -0800)]
Fix @llvm.global_ctors docs (NFC)
Roman Lebedev [Wed, 7 Dec 2022 19:10:05 +0000 (22:10 +0300)]
[NFC] Port all IndVarSimplify tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 19:01:38 +0000 (22:01 +0300)]
[NFC] Port all RewriteStatepointsForGC tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 18:59:26 +0000 (21:59 +0300)]
[NFC] Port all MergeFunc tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 18:57:37 +0000 (21:57 +0300)]
[NFC] Port all GVN tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 18:52:06 +0000 (21:52 +0300)]
[NFC] Port all IROutliner tests to `-passes=` syntax
Tim Northover [Thu, 10 Nov 2022 09:22:40 +0000 (09:22 +0000)]
AArch64: emit `fcmp ord %a, zeroinitializer` as a single fcmeq.
Most "ord" checks need two real-world compares to implement, but this is the
canonical form of a "!isnan" check, which is equivalent to comparing the input
for equality against itself.