Med Ismail Bennani [Wed, 19 Aug 2020 20:04:35 +0000 (22:04 +0200)]
[lldb/interpreter] Add REPL-specific init file
This patch adds the infrastructure to have language specific REPL init
files. It's the foundation work to a following patch that will introduce
Swift REPL init file.
When lldb is launched with the `--repl` option, it will look for a REPL
init file in the home directory and source it. This overrides the
default `~/.lldbinit`, which content might make the REPL behave
unexpectedly. If the REPL init file doesn't exists, lldb will fall back
to the default init file.
rdar://
65836048
Differential Revision: https://reviews.llvm.org/D86242
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Dokyung Song [Wed, 19 Aug 2020 20:21:05 +0000 (20:21 +0000)]
[libFuzzer] Fix value-profile-load test.
The behavior of the CrossOver mutator has changed with
bb54bcf84970c04c9748004f3a4cf59b0c1832a7. This seems to affect the
value-profile-load test on Darwin. This patch provides a wider margin for
determining success of the value-profile-load test, by testing the targeted
functionality (i.e., GEP index value profile) more directly and faster. To this
end, LoadTest.cpp now uses a narrower condition (Size != 8) for initial pruning
of inputs, effectively preventing libFuzzer from generating inputs longer than
necessary and spending time on mutating such long inputs in the corpus - a
functionality not meant to be tested by this specific test.
Previously, on x86/Linux, it required 6,597,751 execs with -use_value_profile=1
and 19,605,575 execs with -use_value_profile=0 to hit the crash. With this
patch, the test passes with 174,493 execs, providing a wider margin from the
given trials of 10,000,000. Note that, without the value profile (i.e.,
-use_value_profile=0), the test wouldn't pass as it still requires 19,605,575
execs to hit the crash.
Differential Revision: https://reviews.llvm.org/D86247
Matt Morehouse [Wed, 19 Aug 2020 22:07:17 +0000 (15:07 -0700)]
[DFSan] Handle mmap() calls before interceptors are installed.
InitializeInterceptors() calls dlsym(), which calls calloc(). Depending
on the allocator implementation, calloc() may invoke mmap(), which
results in a segfault since REAL(mmap) is still being resolved.
We fix this by doing a direct syscall if interceptors haven't been fully
resolved yet.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D86168
Siva Chandra Reddy [Wed, 19 Aug 2020 21:44:23 +0000 (14:44 -0700)]
[libc][obvious] Fix x86 long double conversion to integer.
Fixes incorrectly constructed ceill tests.
Francesco Petrogalli [Wed, 19 Aug 2020 19:50:24 +0000 (19:50 +0000)]
[llvm] Add default constructor of `llvm::ElementCount`.
This patch prevents failures like those reported in
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/34173.
We have enabled the default constructor for
`llvm::ElementCount` to make sure the code compiles on Windows.
Reviewed By: ormris
Differential Revision: https://reviews.llvm.org/D86240
Petr Hosek [Wed, 19 Aug 2020 21:33:52 +0000 (14:33 -0700)]
[CMake] Fix an issue where get_system_libname creates an empty regex capture on windows
Fixes https://bugs.chromium.org/p/chromium/issues/detail?id=1119478
Patch By: haampie
Differential Revision: https://reviews.llvm.org/D86245
Kyungwoo Lee [Wed, 19 Aug 2020 21:28:06 +0000 (17:28 -0400)]
Force Remove Attribute
-force-attribute adds an attribute to function via command-line.
However, there was no counter-part to remove an attribute. This patch
adds -force-remove-attribute that removes an attribute from function.
Differential Revision: https://reviews.llvm.org/D85586
Sanjay Patel [Wed, 19 Aug 2020 20:32:24 +0000 (16:32 -0400)]
[ValueTracking] define/use max recursion depth in header
There's a potential motivating case to increase this limit in PR47191:
http://bugs.llvm.org/PR47191
But first we should make it less hacky. The limit in InstCombine is directly tied
to this value because an increase there can cause asserts in the underlying value
tracking calls if not changed together. The usage in VectorUtils is independent,
but the comment suggests that we should use the same value unless there's a known
reason to diverge. There are similar limits in codegen analysis, but I think we
should leave those independent in case we intentionally want the optimization
power/cost to be different there.
Differential Revision: https://reviews.llvm.org/D86113
Mars Saxman [Wed, 19 Aug 2020 20:45:18 +0000 (22:45 +0200)]
Implement FPToUI and UIToFP ops in standard dialect
Add the unsigned complements to the existing FPToSI and SIToFP operations in the
standard dialect, with one-to-one lowerings to the corresponding LLVM operations.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D85557
Hiroshi Yamauchi [Fri, 14 Aug 2020 19:20:08 +0000 (12:20 -0700)]
[X86] Add feature for Fast Short REP MOV (FSRM) for Icelake or newer.
Differential Revision: https://reviews.llvm.org/D85989
Jonas Devlieghere [Wed, 19 Aug 2020 20:25:57 +0000 (13:25 -0700)]
[lldb] Move Xcode SDK helper functions into lldbutil
This allows the logic to be reused by both the builders and the tests.
Craig Topper [Wed, 19 Aug 2020 20:12:46 +0000 (13:12 -0700)]
[X89] Ignore -mtune=generic to fix failures some users are seeing after D85384
Some code bases out there pass -mtune=generic to clang. This would have
been ignored prior to D85384. Now it results in an error
because "generic" isn't recognized by isValidCPUName.
And if we let it go through to the backend as a tune
setting it would get the tune flags closer to i386 rather
than a modern CPU.
I plan to change what tune=generic does in the backend in
a future patch. And allow this in the frontend.
But this should be a quick fix for the error some users
are seeing.
Alexey Bataev [Tue, 18 Aug 2020 18:51:51 +0000 (14:51 -0400)]
[OPENMP]Fix PR47158, case 2: do not report host-only functions in unused function in device mode.
If the function is not marked exlicitly as declare target and it calls
function(s), marked as declare target device_type(host), these host-only
functions should not be dignosed as used in device mode, if the caller
function is not used in device mode too.
Differential Revision: https://reviews.llvm.org/D86164
River Riddle [Wed, 19 Aug 2020 19:57:45 +0000 (12:57 -0700)]
[mlir] Add a new "Pattern Descriptor Language" (PDL) dialect.
PDL presents a high level abstraction for the rewrite pattern infrastructure available in MLIR. This abstraction allows for representing patterns transforming MLIR, as MLIR. This allows for applying all of the benefits that the general MLIR infrastructure provides, to the infrastructure itself. This means that pattern matching can be more easily verified for correctness, targeted by frontends, and optimized.
PDL abstracts over various different aspects of patterns and core MLIR data structures. Patterns are specified via a `pdl.pattern` operation. These operations contain a region body for the "matcher" code, and terminate with a `pdl.rewrite` that either dispatches to an external rewriter or contains a region for the rewrite specified via `pdl`. The types of values in `pdl` are handle types to MLIR C++ types, with `!pdl.attribute`, `!pdl.operation`, and `!pdl.type` directly mapping to `mlir::Attribute`, `mlir::Operation*`, and `mlir::Value` respectively.
An example pattern is shown below:
```mlir
// pdl.pattern contains metadata similarly to a `RewritePattern`.
pdl.pattern : benefit(1) {
// External input operand values are specified via `pdl.input` operations.
// Result types are constrainted via `pdl.type` operations.
%resultType = pdl.type
%inputOperand = pdl.input
%root, %results = pdl.operation "foo.op"(%inputOperand) -> %resultType
pdl.rewrite(%root) {
pdl.replace %root with (%inputOperand)
}
}
```
This is a culmination of the work originally discussed here: https://groups.google.com/a/tensorflow.org/g/mlir/c/j_bn74ByxlQ
Differential Revision: https://reviews.llvm.org/D84578
Sourabh Singh Tomar [Wed, 19 Aug 2020 20:00:31 +0000 (01:30 +0530)]
Re-apply "[DebugInfo] Emit DW_OP_implicit_value for Floating point constants"
This patch was reverted in
7c182663a857fc87 due to some failures
observed on PCC based machines. Failures were due to Endianness issue and
long double representation issues.
Patch is revised to address Endianness issue. Furthermore, support
for emission of `DW_OP_implicit_value` for `long double` has been removed
(since it was unclean at the moment). Planning to handle this in
a clean way soon!
For more context, please refer to following review link.
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D83560
Shilei Tian [Wed, 19 Aug 2020 20:07:58 +0000 (16:07 -0400)]
[OpenMP] Refactored the function `DeviceTy::data_exchange`
This patch contains the following changes:
1. Renamed the function `DeviceTy::data_exchange` to `DeviceTy::dataExchange`;
2. Changed the second argument `DeviceTy DstDev` to `DeviceTy &DstDev`;
3. Renamed the last argument.
Reviewed By: ye-luo
Differential Revision: https://reviews.llvm.org/D86238
Sourabh Singh Tomar [Wed, 19 Aug 2020 19:58:03 +0000 (01:28 +0530)]
Revert "[DebugInfo] Emit DW_OP_implicit_value for Floating point constants"
This reverts commit
15801f16194a3d.
arc's land messed up! It removed the new commit message and took it
from revision.
Raul Tambre [Wed, 19 Aug 2020 19:50:35 +0000 (12:50 -0700)]
[AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass()
TargetRegisterInfo::getMinimalPhysRegClass() returns rtcGPR64RegClassID for X16
and X17, as it's the last matching class. This in turn gets passed to
AArch64RegisterBankInfo::getRegBankFromRegClass(), which hits an unreachable.
It seems sensible to handle this case, so copies from X16 and X17 work.
Copying from X17 is used in inline assembly in libunwind for pointer
authentication.
Differential Revision: https://reviews.llvm.org/D85720
Sourabh Singh Tomar [Thu, 23 Jul 2020 01:51:06 +0000 (07:21 +0530)]
[DebugInfo] Emit DW_OP_implicit_value for Floating point constants
llvm is missing support for DW_OP_implicit_value operation.
DW_OP_implicit_value op is indispensable for cases such as
optimized out long double variables.
For intro refer: DWARFv5 Spec Pg: 40 2.6.1.1.4 Implicit Location Descriptions
Consider the following example:
```
int main() {
long double ld = 3.14;
printf("dummy\n");
ld *= ld;
return 0;
}
```
when compiled with tunk `clang` as
`clang test.c -g -O1` produces following location description
of variable `ld`:
```
DW_AT_location (0x00000000:
[0x0000000000201691, 0x000000000020169b): DW_OP_constu 0xc8f5c28f5c28f800, DW_OP_stack_value, DW_OP_piece 0x8, DW_OP_constu 0x4000, DW_OP_stack_value, DW_OP_bit_piece 0x10 0x40, DW_OP_stack_value)
DW_AT_name ("ld")
```
Here one may notice that this representation is incorrect(DWARF4
stack could only hold integers(and only up to the size of address)).
Here the variable size itself is `128` bit.
GDB and LLDB confirms this:
```
(gdb) p ld
$1 = <invalid float value>
(lldb) frame variable ld
(long double) ld = <extracting data from value failed>
```
GCC represents/uses DW_OP_implicit_value in these sort of situations.
Based on the discussion with Jakub Jelinek regarding GCC's motivation
for using this, I concluded that DW_OP_implicit_value is most appropriate
in this case.
Link: https://gcc.gnu.org/pipermail/gcc/2020-July/233057.html
GDB seems happy after this patch:(LLDB doesn't have support
for DW_OP_implicit_value)
```
(gdb) p ld
p ld
$1 = 3.
14000000000000012434
```
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D83560
Jonas Devlieghere [Wed, 19 Aug 2020 19:40:53 +0000 (12:40 -0700)]
[lldb] Print the load command that wasn't found in TestSimulatorPlatform
Print which load command we were looking for when the sanity check
fails:
AssertionError: 0 != 1 : wrong number of load commands for
LC_VERSION_MIN_MACOSX
Hiroshi Yamauchi [Tue, 11 Aug 2020 21:10:30 +0000 (14:10 -0700)]
[PGO][PGSO][LV] Fix loop not vectorized issue under profile guided size opts.
D81345 appears to accidentally disables vectorization when explicitly
enabled. As PGSO isn't currently accessible from LoopAccessInfo, revert back to
the vectorization with versioning-for-unit-stride for PGSO.
Differential Revision: https://reviews.llvm.org/D85784
Jonas Devlieghere [Wed, 19 Aug 2020 17:19:03 +0000 (10:19 -0700)]
[lldb] Code sign binaries with entitlements
Binaries need to be code signed with entitlements to run on device.
Differential revision: https://reviews.llvm.org/D86237
Petr Hosek [Wed, 19 Aug 2020 18:06:19 +0000 (11:06 -0700)]
[CMake] Always mark terminfo as unavailable on Windows
This addresses the issue introduced by D86134.
Differential Revision: https://reviews.llvm.org/D86234
Matt Arsenault [Fri, 31 Jul 2020 15:41:05 +0000 (11:41 -0400)]
GlobalISel: Add TargetLowering member to LegalizerHelper
Jonas Devlieghere [Wed, 19 Aug 2020 01:48:18 +0000 (18:48 -0700)]
[lldb] Extend Darwin builder to pass the ARCH_CFLAGS spec to Make.
Construct the ARCH_CFLAGS in Python rather than in Make by disassembling
the TRIPLE.
Differential revision: https://reviews.llvm.org/D85539
Florian Hahn [Wed, 19 Aug 2020 18:32:49 +0000 (19:32 +0100)]
[DSE] Remove dead argument from removePartiallyOverlappedStores (NFC).
The argument is unused and can be removed.
Matt Arsenault [Mon, 17 Aug 2020 12:50:11 +0000 (08:50 -0400)]
AMDGPU: Fix wrong type mangling in intrinsic test
The generic address space used to be 4, but the string here seems to
not matter.
Jan Korous [Tue, 14 Jul 2020 02:38:58 +0000 (19:38 -0700)]
[index-while-building] PathIndexer
Differential Revision: https://reviews.llvm.org/D66854
Matt Arsenault [Wed, 19 Aug 2020 18:06:17 +0000 (14:06 -0400)]
GlobalISel: Don't check for verifier enforced constraint
Loads are always required to have a single memory operand.
Matt Arsenault [Wed, 19 Aug 2020 17:59:11 +0000 (13:59 -0400)]
AMDGPU/GlobalISel: Remove hack for combines forming illegal extloads
Previously we weren't adding the LegalizerInfo to the post-legalizer
combiner. Since that's fixed, we don't need to try to filter out the
one case that was breaking.
Peter Collingbourne [Tue, 18 Aug 2020 20:06:41 +0000 (13:06 -0700)]
sanitizer_common: Use void* for madvise first argument on Solaris.
Differential Revision: https://reviews.llvm.org/D86166
Sanjay Patel [Wed, 19 Aug 2020 16:46:53 +0000 (12:46 -0400)]
[InstCombine] add tests for shifted xor; NFC
Matt Arsenault [Wed, 19 Aug 2020 16:10:32 +0000 (12:10 -0400)]
GlobalISel: Use Register
Petr Hosek [Wed, 19 Aug 2020 17:33:03 +0000 (10:33 -0700)]
[CMake] Fix OCaml build failure because of absolute path in system libs
D85820 introduced a full path in the LLVM_SYSTEM_LIBS property of the
LLVMSupport target, which made the OCaml bindings fail to build, since
they use -l [system_lib] flags for every lib in LLVM_SYSTEM_LIBS, which
cannot work with absolute paths.
This patch solves the issue in a similar vain as ZLIB does it: it adds
the full library path to imported_libs, and adds a stripped down version
without directories, lib prefix and lib suffix to system_libs
In the future we should probably make some changes to LLVM_SYSTEM_LIBS,
since both zlib and ncurses do not necessarily have to be system libs
anymore due to the find_package / find_library bits introduced in
D85820 and D79219.
Patch By: haampie
Differential Revision: https://reviews.llvm.org/D86134
Petr Hosek [Wed, 19 Aug 2020 17:30:32 +0000 (10:30 -0700)]
[CMake] Don't look for terminfo libs when LLVM_ENABLE_TERMINFO=OFF
D85820 introduced a bug where LLVM_ENABLE_TERMINFO was set to true when
the library was found, even when the user had set
-DLLVM_ENABLE_TERMINFO=OFF.
Patch By: haampie
Differential Revision: https://reviews.llvm.org/D86173
Jakub Lichman [Wed, 19 Aug 2020 17:28:22 +0000 (17:28 +0000)]
[mlir][VectorToSCF] Fix of broken build - missing link to MLIRLinalgUtils
Mehdi Amini [Wed, 19 Aug 2020 17:26:36 +0000 (17:26 +0000)]
Revert "Revert "[NFC][llvm] Make the contructors of `ElementCount` private.""
Was reverted because MLIR/Flang builds were broken, these APIs have been
fixed in the meantime.
Mehdi Amini [Wed, 19 Aug 2020 17:19:49 +0000 (17:19 +0000)]
Fix flang test after MLIR API changes
Mehdi Amini [Wed, 19 Aug 2020 17:13:28 +0000 (17:13 +0000)]
Revert "[NFC][llvm] Make the contructors of `ElementCount` private."
This reverts commit
264afb9e6aebc98c353644dd0700bec808501cab.
(and dependent
6b742cc48 and
fc53bd610f)
MLIR/Flang are broken.
Jessica Paquette [Thu, 6 Aug 2020 17:40:46 +0000 (10:40 -0700)]
[GlobalISel] Add combine for (x & mask) -> x when (x & mask) == x
If we have a mask, and a value x, where (x & mask) == x, we can drop the AND
and just use x.
This is about a 0.4% geomean code size improvement on CTMark at -O3 for AArch64.
In AArch64, this is most useful post-legalization. Patterns like this often
show up when legalizing s1s, which must be extended to larger types.
e.g.
```
%cmp:_(s32) = G_ICMP ...
%and:_(s32) = G_AND %cmp, 1
```
Since G_ICMP only produces a single bit, there's no reason to mask it with the
G_AND.
Differential Revision: https://reviews.llvm.org/D85463
Jon Chesterfield [Wed, 19 Aug 2020 17:11:34 +0000 (18:11 +0100)]
[Clang] Fix BZ47169, loader_uninitialized on incomplete types
[Clang] Fix BZ47169, loader_uninitialized on incomplete types
Reported by @erichkeane. Fix proposed by @erichkeane works, tests included.
Bug introduced in D74361. Crash was on querying a CXXRecordDecl for
hasTrivialDefaultConstructor on an incomplete type. Fixed by calling
RequireCompleteType in the right place.
Reviewed By: erichkeane
Differential Revision: https://reviews.llvm.org/D85990
Caroline Concatto [Wed, 19 Aug 2020 16:53:29 +0000 (17:53 +0100)]
[clang][driver]Add quotation mark in test/fortran.f95 to avoid false positive
If a folder's name, where the test fortran.f95 is running, has cc1 the test
fails because of CHECK-ASM-NOT: cc1.
The solution used in this patch is to add quotation mark around cc1 and cc1as
because the driver returns these flags with quotation marks ("")
Reviewed By: DavidTruby, echristo
Differential Revision: https://reviews.llvm.org/D86132
Alex Zinenko [Wed, 19 Aug 2020 16:38:56 +0000 (18:38 +0200)]
[mlir] expose standard attributes to C API
Provide C API for MLIR standard attributes. Since standard attributes live
under lib/IR in core MLIR, place the C APIs in the IR library as well (standard
ops will go in a separate library).
Affine map and integer set attributes are only exposed as placeholder types
with IsA support due to the lack of C APIs for the corresponding types.
Integer and floating point attribute APIs expecting APInt and APFloat are not
exposed pending decision on how to support APInt and APFloat.
Reviewed By: stellaraccident
Differential Revision: https://reviews.llvm.org/D86143
Alex Zinenko [Wed, 19 Aug 2020 16:46:53 +0000 (18:46 +0200)]
[mlir] fix build after llvm made ElementCount constructor private
The original patch (
264afb9e6aebc98c353644dd0700bec808501cab) did not
update subprojects.
Jonas Devlieghere [Wed, 19 Aug 2020 16:25:41 +0000 (09:25 -0700)]
[lldb] Add getExtraMakeArgs to Builder (NFC)
Instead of a new method for each variable any subclass might want to
set, have a method getExtraMakeArgs that each subclass can use to return
whatever extra Make arguments it wants.
As per Pavel's suggestion in D85539.
Jonas Devlieghere [Wed, 19 Aug 2020 16:08:40 +0000 (09:08 -0700)]
[lldb] Fix buildDsym signature in Builder base class
The method was missing the optional argument `testname`.
Hamilton Tobon Mosquera [Wed, 19 Aug 2020 16:03:23 +0000 (11:03 -0500)]
[OpenMPOpt][HideMemTransfersLatency] Moving the 'wait' counterpart of __tgt_target_data_begin_mapper
canBeMovedDownwards checks if the "wait" counterpart of __tgt_target_data_begin_mapper can be moved downwards, returning a pointer to the instruction that might require/modify the data transferred, and returning null it the movement is not possible or not worth it. The function splitTargetDataBeginRTC receives that returned instruction and instead of moving the "wait" it creates it at that point.
Differential Revision: https://reviews.llvm.org/D86155
Jonas Devlieghere [Wed, 19 Aug 2020 16:39:44 +0000 (09:39 -0700)]
[clang] Replace call to private ctor with ElementCount::getScalable (2/2)
Update the code for D86120 which made the constructors of `ElementCount`
private. Apparently I missed another instance in the macro just below.
Florian Hahn [Wed, 19 Aug 2020 16:37:20 +0000 (17:37 +0100)]
[docs] Clarify ENABLE_MODULES uses Clang Header Modules.
Suggested post-commit by @dblaikie, thanks!
Jonas Devlieghere [Wed, 19 Aug 2020 16:34:57 +0000 (09:34 -0700)]
[clang] Replace call to private ctor with ElementCount::getScalable
Update the code for D86120 which made the constructors of `ElementCount`
private.
Francesco Petrogalli [Mon, 17 Aug 2020 22:48:15 +0000 (22:48 +0000)]
[NFC][llvm] Make the contructors of `ElementCount` private.
Differential Revision: https://reviews.llvm.org/D86120
Stella Laurenzo [Wed, 19 Aug 2020 00:23:46 +0000 (17:23 -0700)]
Add python bindings for Type and IntegerType.
* The binding for Type is trivial and should be non-controversial.
* The way that I define the IntegerType should serve as a pattern for what I want to do next.
* I propose defining the rest of the standard types in this fashion and then generalizing for dialect types as necessary.
* Essentially, creating/accessing a concrete Type (vs interacting with the string form) is done by "casting" to the concrete type (i.e. IntegerType can be constructed with a Type and will throw if the cast is illegal).
* This deviates from some of our previous discussions about global objects but I think produces a usable API and we should go this way.
Differential Revision: https://reviews.llvm.org/D86179
Sanjay Patel [Wed, 19 Aug 2020 16:07:28 +0000 (12:07 -0400)]
[InstCombine] avoid 'tmp' names in tests; NFC
They may conflict with update_test_checks.py regexes.
Jonas Devlieghere [Wed, 19 Aug 2020 16:05:11 +0000 (09:05 -0700)]
[lldb] Move builders under lldbsuite.test as they import lldbtest (NFC)
Sanjay Patel [Wed, 19 Aug 2020 16:04:53 +0000 (12:04 -0400)]
[InstCombine] reduce code duplication; NFC
Jonas Devlieghere [Wed, 19 Aug 2020 15:27:54 +0000 (08:27 -0700)]
[lldb] Convert builders to use inheritance (NFC)
Rather than have different modules for different platforms, use
inheritance so we can have a Builer base class and optional child
classes that override platform specific methods.
Differential revision: https://reviews.llvm.org/D86174
Jakub Lichman [Wed, 19 Aug 2020 15:13:19 +0000 (15:13 +0000)]
[mlir][VectorToSCF] Bug in TransferRead lowering fixed
If Memref has rank > 1 this pass emits N-1 loops around
TransferRead op and transforms the op itself to 1D read. Since vectors
must have static shape while memrefs don't the pass emits if condition
to prevent out of bounds accesses in case some memref dimension is smaller
than the corresponding dimension of targeted vector. This logic is fine
but authors forgot to apply `permutation_map` on loops upper bounds and
thus if condition compares induction variable to incorrect loop upper bound
(dimension of the memref) in case `permutation_map` is not identity map.
This commit aims to fix that.
Jon Chesterfield [Wed, 19 Aug 2020 14:44:30 +0000 (15:44 +0100)]
[libomptarget][amdgpu] Support building with static rocm libraries
Matt Arsenault [Wed, 19 Aug 2020 14:07:57 +0000 (10:07 -0400)]
AMDGPU/GlobalISel: Add some bitcast tests
madhur13490 [Wed, 19 Aug 2020 11:18:52 +0000 (11:18 +0000)]
[NFC] Fix typo in AMDGPU doc
Reviewed By: t-tye, arsenm
Differential Revision: https://reviews.llvm.org/D86206
Matt Arsenault [Tue, 18 Aug 2020 18:45:05 +0000 (14:45 -0400)]
AMDGPU/GlobalISel: Add selection tests for pointer constants
Benjamin Kramer [Wed, 19 Aug 2020 13:59:39 +0000 (15:59 +0200)]
Make helpers static. NFC.
Roman Lebedev [Wed, 19 Aug 2020 13:52:09 +0000 (16:52 +0300)]
Revert "[InstCombine] Lower infinite combine loop detection thresholds"
And as being reported by Florian Hahn, there's a hit
in MultiSource/Benchmarks/mafft from the test-suite on X86 with -O3 -flto,
so reverting until addressed.
This reverts commit
71e0b82c9f5039cb3987c91075e78733ef044c07.
Simon Pilgrim [Wed, 19 Aug 2020 13:41:40 +0000 (14:41 +0100)]
Fix MSVC implicit truncation narrowing conversion warning.
Simon Pilgrim [Wed, 19 Aug 2020 13:34:12 +0000 (14:34 +0100)]
[X86][AVX] lowerShuffleWithVPMOV - minor refactor to more closely match lowerShuffleAsVTRUNC
Replace isBuildVectorAllZeros check by using the Zeroable bitmask instead.
Simon Pilgrim [Wed, 19 Aug 2020 13:14:44 +0000 (14:14 +0100)]
Fix unused variable warnings. NFCI.
Aaron Puchert [Wed, 19 Aug 2020 13:04:44 +0000 (15:04 +0200)]
[CodeGen] Use existing EmitLambdaVLACapture (NFC)
Xing GUO [Wed, 19 Aug 2020 13:13:46 +0000 (21:13 +0800)]
[obj2yaml] Refactor the .debug_pub* sections dumper.
It's good to reuse the DWARF parser in lib/DebugInfo so that we don't
need to maintain a separate parser in client side (obj2yaml). Besides,
A test case is added whose length field is a very huge value which makes
obj2yaml stuck when parsing the section.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D86192
Pavel Labath [Wed, 19 Aug 2020 12:58:50 +0000 (14:58 +0200)]
[lldb] Clean up DW_AT_declaration-with-children.s test
Address some post-commit feedback on D85968.
Pavel Labath [Tue, 18 Aug 2020 13:46:26 +0000 (15:46 +0200)]
[lldb] Add typedefs to the DeclContext they are created in
TypeSystemClang::CreateTypedef was creating a typedef in the right
DeclContext, but it was not actually adding it as a child of the
context. The resulting inconsistent state meant that we would be unable
to reference the typedef from an expression directly, but we could use
them if they end up being pulled in by some previous subexpression
(because the ASTImporter will set up the correct links in the expression
ast).
This patch adds the typedef to the decl context it is created in.
Differential Revision: https://reviews.llvm.org/D86140
Simon Pilgrim [Wed, 19 Aug 2020 12:28:59 +0000 (13:28 +0100)]
[X86] lowerShuffleWithVPMOV - remove unnecessary shuffle commutation. NFCI.
canonicalizeShuffleMaskWithCommute should have already ensured the lower elements are from V1, we do have test coverage for this already.
Simon Pilgrim [Wed, 19 Aug 2020 12:00:09 +0000 (13:00 +0100)]
[X86][AVX] getAVX512TruncNode - don't truncate from illegal vector widths.
Thanks to @fhahn for the test case.
Sanjay Patel [Wed, 19 Aug 2020 11:40:10 +0000 (07:40 -0400)]
[InstCombine] update stale comments in test files; NFC
I missed updating these with:
rG23bd33c6acc4
Roman Lebedev [Wed, 19 Aug 2020 11:36:47 +0000 (14:36 +0300)]
[InstCombine] Lower infinite combine loop detection thresholds
It's been a month since
2f3862eb9f21e8a0d48505637fefe6e5e295c18c,
and no new bug reports about the threshold were filled,
so let's bump it again and wait again.
Raphael Isemann [Wed, 19 Aug 2020 11:30:31 +0000 (13:30 +0200)]
[lldb] Make error messages in TestQueues more helpfull
David Green [Wed, 19 Aug 2020 10:58:50 +0000 (11:58 +0100)]
[ARM] Change target triple to arm-none-none-eabi. NFC
Muhammad Omair Javaid [Wed, 19 Aug 2020 10:47:46 +0000 (15:47 +0500)]
[LLDB] Minor fix in TestSVERegisters.py for AArch64/Linux buildbot
This adds a minor test case fix to previously submitted AArch64 SVE
ptrace support. This was failing on LLDB/AArch64 Linux buildbot.
Differential Revision: https://reviews.llvm.org/D79699
Simon Pilgrim [Wed, 19 Aug 2020 10:39:12 +0000 (11:39 +0100)]
[X86][AVX] computeKnownBitsForTargetNode - add VTRUNC/VTRUNCS/VTRUNCUS known zero upper elements handling.
Like many of the AVX512 conversion ops, the VTRUNC ops guarantee the upper destination elements are zero.
Paul Walker [Tue, 18 Aug 2020 16:47:10 +0000 (17:47 +0100)]
[SVE] Add tests for fixed length vector integer operations with immediate operands.
Muhammad Omair Javaid [Wed, 19 Aug 2020 07:38:30 +0000 (12:38 +0500)]
[LLDB] Add ptrace register access for AArch64 SVE registers
This patch adds NativeRegisterContext_arm64 ptrace routines to access
AArch64 SVE register set. This patch also adds a test-case to test
AArch64 SVE register access and dynamic size configuration capability.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D79699
Simon Pilgrim [Wed, 19 Aug 2020 09:48:22 +0000 (10:48 +0100)]
[X86][AVX] Fold store(extract_element(vtrunc)) to truncated store
Add handling for storing the extracted lower (truncated bits) element from a X86ISD::VTRUNC node - this can be lowered to a generic truncated store directly.
Differential Revision: https://reviews.llvm.org/D86158
Sander de Smalen [Wed, 19 Aug 2020 09:34:25 +0000 (10:34 +0100)]
[Clang][SVE] NFC: Move info about ACLE types into separate function.
This function returns a struct `BuiltinVectorTypeInfo` that contains
the builtin vector's element type, element count and number of vectors
(used for vector tuples).
Reviewed By: c-rhodes
Differential Revision: https://reviews.llvm.org/D86100
Bjorn Pettersson [Wed, 19 Aug 2020 09:36:03 +0000 (11:36 +0200)]
[GlobalISel] Untabify InstructionSelectorImpl.h. NFC
sstefan1 [Wed, 12 Aug 2020 10:20:53 +0000 (12:20 +0200)]
[OpenMPOpt] ICV tracking for calls
Introduce two new AAs. AAICVTrackerFunctionReturned which checks if a
function can have a unique ICV value after it is finished, and
AAICVCallSiteReturned which checks AAICVTrackerFunctionReturned for a
call site. This enables us to check the value of a call and if it
changes the ICV. This also changes the approach in
`getReplacementValues()` to a worklist-based approach so we can explore
all relevant BBs.
Differential Revision: https://reviews.llvm.org/D85544
sstefan1 [Mon, 17 Aug 2020 17:43:55 +0000 (19:43 +0200)]
[IR] Intrinsics default attributes and opt-out flag
Intrinsic properties can now be set to default and applied to all
intrinsics. If the attributes are not needed, the user can opt-out by
setting the DisableDefaultAttributes flag to true.
Differential Revision: https://reviews.llvm.org/D70365
Meera Nakrani [Wed, 19 Aug 2020 08:36:49 +0000 (08:36 +0000)]
[ARM] Enabled VMLAV and Add instructions to use VMLAVA
Used InstCombine to enable VMLAV and Add instructions to generate VMLAVA instead with tests.
luxufan [Thu, 23 Jul 2020 05:45:14 +0000 (13:45 +0800)]
[RISCV] add the assemble and disassemble support of Zvlsseg instructions
This implements the assemble and disassemble support of RISCV Vector
extension Zvlsseg instructions, base on the 0.9 spec version.
Reviewed by HsiangKai
Differential Revision: https://reviews.llvm.org/D84416
Mauri Mustonen [Wed, 19 Aug 2020 07:54:52 +0000 (08:54 +0100)]
[utils] Fix regexp in llvm/utils/extract_vplan.py to extract VPlans.
Regarding this bug in Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=46451
I went ahead and fixed the regexp pattern and now Python script is able
to extract vplan graphs from the log files. Additionally some test for
this would be nice to have but I'm not sure are Python scripts tested
in LLVM and if so where they live.
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D86068
madhur13490 [Thu, 2 Jul 2020 09:08:06 +0000 (09:08 +0000)]
[GlobalISel] Don't skip adding predicate matcher
This patch fixes a bug which skipped
adding predicate matcher for a pattern in many cases.
For example, if predicate is Load and
its memoryVT is non-null then the loop
continues and never reaches to the end which
adds the predicate matcher. This patch moves the
matcher addition to the top of the loop
so that it gets added regardless of contextual checks
later in the loop.
Other way to fix this issue is to remove all "continue" statements
in checks and let the loop continue till end.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D83034
Florian Hahn [Wed, 19 Aug 2020 07:47:03 +0000 (08:47 +0100)]
[DSE,MemorySSA] Use NumRedundantStores instead of NumNoopStores.
Legacy DSE uses NumRedundantStores, while MemorySSA DSE uses
NumNoopStores. We should just use the same counter.
Ronak Chauhan [Wed, 19 Aug 2020 07:37:40 +0000 (13:07 +0530)]
Revert "[AMDGPU] Support disassembly for AMDGPU kernel descriptors"
This reverts commit
cacfb02d28a3cabd4e45d2535cb0686cef48a2c9.
Reverting due to buildbot failures.
Martin Storsjö [Wed, 19 Aug 2020 07:40:27 +0000 (10:40 +0300)]
[clang] Remove stray semicolons, fixing GCC warnings. NFC.
Muhammad Omair Javaid [Wed, 19 Aug 2020 07:29:16 +0000 (12:29 +0500)]
[LLDB] NativeThreadLinux invalidate register cache on stop
In our discussion D79699 SVE ptrace register access support we decide to
invalidate register context cached data on every stop instead of doing
at before Step/Resume.
InvalidateAllRegisters was added to facilitate flushing of SVE register
context configuration and cached register values. It now makes more
sense to move invalidation after every stop where we initiate SVE
configuration update if needed by calling ConfigureRegisterContext.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D84501
Muhammad Omair Javaid [Wed, 19 Aug 2020 07:27:02 +0000 (12:27 +0500)]
Convert SVE macros into c++ constants and inlines
This patch updates LLDB's in house version of SVE ptrace/sig macros by
converting them into constants and inlines. They are housed under sve
namespace and are used by process elf-core for reading SVE register data.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D85641
Haojian Wu [Wed, 19 Aug 2020 07:04:31 +0000 (09:04 +0200)]
[AST] Fix a crash on mangling a binding decl from a DeclRefExpr.
Differential Revision: https://reviews.llvm.org/D86130
David Sherwood [Wed, 12 Aug 2020 13:16:22 +0000 (14:16 +0100)]
[SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorLoads
In DAGTypeLegalizer::GenWidenVectorLoads the algorithm assumes it only
ever deals with fixed width types, hence the offsets for each individual
store never take 'vscale' into account. I've changed the code in that
function to use TypeSize instead of unsigned for tracking the remaining
load amount. In addition, I've changed the load loop to use the new
IncrementPointer helper function for updating the addresses in each
iteration, since this handles scalable vector types.
Also, I've added report_fatal_errors in GenWidenVectorExtLoads,
TargetLowering::scalarizeVectorLoad and TargetLowering::scalarizeVectorStores,
since these functions currently use a sequence of element-by-element
scalar loads/stores. In a similar vein, I've also added a fatal error
report in FindMemType for the case when we decide to return the element
type for a scalable vector type.
I've added new tests in
CodeGen/AArch64/sve-split-load.ll
CodeGen/AArch64/sve-ld-addressing-mode-reg-imm.ll
for the changes in GenWidenVectorLoads.
Differential Revision: https://reviews.llvm.org/D85909
Craig Topper [Wed, 19 Aug 2020 06:43:15 +0000 (23:43 -0700)]
[X86][Driver] Remove code that forced a core2 mtune from MachO::TranslateArgs.
mtune was previously ignored by the compiler so I'm not sure this
did anything. But after D85384 we're starting to support mtune
and this code is now causing a couple test failures on MacOS.
Shinji Okumura [Wed, 19 Aug 2020 06:01:14 +0000 (15:01 +0900)]
[Attributor][NFC] Add tests to range.ll
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D86128
Yaxun (Sam) Liu [Wed, 19 Aug 2020 04:21:54 +0000 (00:21 -0400)]
Fix test hip-target-id.hip
Some build bot has lld in the directory name, which caused pattern match
issue in the list test.
LLVM GN Syncbot [Wed, 19 Aug 2020 03:44:19 +0000 (03:44 +0000)]
[gn build] Port
7546b29e761