Michael Liao [Sun, 24 Feb 2019 03:07:32 +0000 (03:07 +0000)]
[NFC] Minor coding style (indent) fix.
llvm-svn: 354741
Philip Reames [Sun, 24 Feb 2019 00:45:09 +0000 (00:45 +0000)]
[Hexagon, SystemZ] Be super conservative about atomics
As requested during review of D57601, be equally conservative for atomic MMOs as for volatile MMOs in all in tree backends. At the moment, all atomic MMOs are also volatile, but I'm about to change that.
Reviewed as part of https://reviews.llvm.org/D58490, with other backends still pending review.
llvm-svn: 354740
Duncan P. N. Exon Smith [Sat, 23 Feb 2019 23:48:47 +0000 (23:48 +0000)]
VFS: Avoid some unnecessary std::string copies
Thread Twine a little deeper through the VFS to avoid unnecessarily
constructing the same std::string twice in a parameter sequence:
Twine -> std::string -> StringRef -> std::string
Changing a few parameters from StringRef to Twine avoids the early call
to `Twine::str()`.
llvm-svn: 354739
Craig Topper [Sat, 23 Feb 2019 21:41:44 +0000 (21:41 +0000)]
[TwoAddressInstructionPass] After commuting an instruction and before trying to look for more commutable operands, resample the number of operands.
The new instruciton might have less operands than the original instruction. If we don't resample, the next loop iteration might read an operand that doesn't exist.
X86 can commute blends to movss/movsd which reduces from 4 operands to 3. This happened in the test case that caused r354363 & company to be reverted. A reduced version of that has been committed here.
Really this whole checking for more commutable operands is a little fragile. It assumes that the new instructions operands are the same order and positions as the original except for the pair that was swapped. I don't know of anything that breaks this assumption today, but I've left a fixme. Fixing this will likely require an interface change.
llvm-svn: 354738
Craig Topper [Sat, 23 Feb 2019 21:41:42 +0000 (21:41 +0000)]
Recommit r354363 "[X86][SSE] Generalize X86ISD::BLENDI support to more value types"
And its follow ups r354511, r354640.
A follow patch will fix the issue that caused it to be reverted.
llvm-svn: 354737
Richard Smith [Sat, 23 Feb 2019 21:06:26 +0000 (21:06 +0000)]
Enable coroutines under -std=c++2a.
llvm-svn: 354736
Richard Smith [Sat, 23 Feb 2019 21:06:25 +0000 (21:06 +0000)]
[cxx_status] Update to match Kona motions.
llvm-svn: 354735
Craig Topper [Sat, 23 Feb 2019 19:51:32 +0000 (19:51 +0000)]
Recommit r354647 and r354648 "[LegalizeTypes] When promoting the result of EXTRACT_SUBVECTOR, also check if the input needs to be promoted. Use that to determine the element type to extract"
r354648 was a follow up to fix a regression "[X86] Add a DAG combine for (aext_vector_inreg (aext_vector_inreg X)) -> (aext_vector_inreg X) to fix a regression from my previous commit."
These were reverted in r354713 as their context depended on other patches that were reverted for a bug.
llvm-svn: 354734
Nikita Popov [Sat, 23 Feb 2019 18:59:01 +0000 (18:59 +0000)]
[WebAssembly] Fix select of and (PR40805)
Fixes https://bugs.llvm.org/show_bug.cgi?id=40805 introduced by
patterns added in D53676.
I'm removing the patterns entirely here, as they are not correct
in the general case. If necessary something more specific can be
added in the future.
Differential Revision: https://reviews.llvm.org/D58575
llvm-svn: 354733
Simon Pilgrim [Sat, 23 Feb 2019 18:53:03 +0000 (18:53 +0000)]
[X86][AVX] combineInsertSubvector - remove concat_vectors(load(x),load(x)) --> sub_vbroadcast(x)
D58053/rL354340 added this to EltsFromConsecutiveLoads directly
llvm-svn: 354732
Simon Pilgrim [Sat, 23 Feb 2019 18:49:02 +0000 (18:49 +0000)]
Fix MSVC constant truncation warnings. NFCI.
llvm-svn: 354731
Simon Pilgrim [Sat, 23 Feb 2019 18:34:05 +0000 (18:34 +0000)]
[X86][AVX] concat_vectors(scalar_to_vector(x),scalar_to_vector(x)) --> broadcast(x)
For AVX1, limit this to i32/f32/i64/f64 loading cases only.
llvm-svn: 354730
Simon Pilgrim [Sat, 23 Feb 2019 17:10:47 +0000 (17:10 +0000)]
[X86][AVX] Shuffle->Permute+Blend if we have one v4f64/v4i64 shuffle input in place
Even on AVX1 we can pretty cheaply (VPERM2F128+VSHUFPD) permute a single v4f64/v4i64 input (on AVX2 its just a single VPERMPD), followed by a BLENDPD.
llvm-svn: 354729
Bruno Ricci [Sat, 23 Feb 2019 16:40:30 +0000 (16:40 +0000)]
[NFC] Fix Wdocumentation warning in OMPToClause
llvm-svn: 354728
Bruno Ricci [Sat, 23 Feb 2019 16:25:00 +0000 (16:25 +0000)]
[Sema][NFC] SequenceChecker: More tests in preparation for D57660
llvm-svn: 354727
Simon Dardis [Sat, 23 Feb 2019 15:56:32 +0000 (15:56 +0000)]
[MIPS] Fix a incorrect test. (NFC)
This test is incorrect as it should be using the microMIPSR6 instruction to
return, not the microMIPS version.
llvm-svn: 354726
Louis Dionne [Sat, 23 Feb 2019 11:24:03 +0000 (11:24 +0000)]
[libcxx] Make sure all experimental tests are disabled when enable_experimental=False
Summary:
Previously, we'd run some experimental tests even when enable_experimental=False
was used with lit.
Reviewers: EricWF
Subscribers: christof, jkorous, dexonsmith, libcxx-commits, mclow.lists
Differential Revision: https://reviews.llvm.org/D55834
llvm-svn: 354725
Craig Topper [Sat, 23 Feb 2019 08:34:10 +0000 (08:34 +0000)]
[X86] Sign extend the 8-bit immediate when commuting blend instructions to match isel.
Conversion from ConstantSDNode to MachineInstr sign extends immediates from their APInt representation to int64_t.
This commit makes sure we do the same for commuting. The tests changes show how this improves CSE. This issue was made worse by the MachineCSE using commuteInstruction to undo a commute. So we virtually guarantee the sign extend from isel would be lost.
The improved CSE also occurred with r354363, but that was reverted. I'm working to undo the revert, but wanted to get this fix in while it was easy to see the results.
llvm-svn: 354724
Brad Smith [Sat, 23 Feb 2019 07:21:19 +0000 (07:21 +0000)]
Remove OpenBSD case for old system libstdc++ header path as OpenBSD
has switched to libc++.
llvm-svn: 354723
Michael Trent [Sat, 23 Feb 2019 06:19:56 +0000 (06:19 +0000)]
objdump fails to parse Mach-O binaries with n_desc bearing stabs
Summary:
The objdump Mach-O parser uses MachOObjectFile::checkSymbolTable() to
verify the symbol table is in a legal state before dereferencing the
offsets in the table. This routine missed a test for N_STAB symbols
when validating the two-level name space library ordinal for undefined
symbols. If the binary in question contained a value in the n_desc high
byte that is larger than the list of loaded dylibs, checkSymbolTable()
will flag the library ordinal as being out of range. Most of the time
the n_desc field is set to 0 or to small values, but old final linked
binaries exist with N_STAB symbols bearing non-trivial n_desc fields.
The change here is simply to verify a symbol is not an N_STAB symbol
before consulting the values of n_other or n_desc.
rdar://
44977336
Reviewers: lhames, pete, ab
Reviewed By: pete
Subscribers: llvm-commits, rupprecht
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58568
llvm-svn: 354722
Brad Smith [Sat, 23 Feb 2019 06:19:28 +0000 (06:19 +0000)]
Remove sanitizer context workaround no longer necessary
The base linker is now lld.
llvm-svn: 354721
Richard Trieu [Sat, 23 Feb 2019 05:48:50 +0000 (05:48 +0000)]
Remove overly broad assert from r354717.
llvm-svn: 354720
Daniel Sanders [Sat, 23 Feb 2019 03:25:37 +0000 (03:25 +0000)]
Try again to fix memory leak in r354692
The previous one didn't fix everything.
llvm-svn: 354719
Julian Lettner [Sat, 23 Feb 2019 03:24:10 +0000 (03:24 +0000)]
[NFC][Sanitizer] Comment out argument checks
These break clang-ppc64 bots.
llvm-svn: 354718
Julian Lettner [Sat, 23 Feb 2019 02:36:23 +0000 (02:36 +0000)]
[NFC][Sanitizer] Add argument checks to BufferedStackTrace::Unwind* functions
Reviewers: vitalybuka
Differential Revision: https://reviews.llvm.org/D58555
llvm-svn: 354717
Alexandre Ganea [Sat, 23 Feb 2019 01:46:18 +0000 (01:46 +0000)]
[LLD][COFF] Add support for /FUNCTIONPADMIN command-line option
Initial patch by Stefan Reinalter.
Fixes PR36775
Differential Revision: https://reviews.llvm.org/D49366
llvm-svn: 354716
Jordan Rupprecht [Sat, 23 Feb 2019 01:28:32 +0000 (01:28 +0000)]
[NFC] Fix typos: preceeding -> preceding
llvm-svn: 354715
Reid Kleckner [Sat, 23 Feb 2019 01:19:42 +0000 (01:19 +0000)]
Revert r354363 & co "[X86][SSE] Generalize X86ISD::BLENDI support to more value types"
r354363 caused https://crbug.com/934963#c1, which has a plain C reduced
test case.
I also had to revert some dependent changes:
- r354648
- r354647
- r354640
- r354511
llvm-svn: 354713
Daniel Sanders [Sat, 23 Feb 2019 01:13:35 +0000 (01:13 +0000)]
Fix memory leak in r354692
llvm-svn: 354712
Jim Ingham [Sat, 23 Feb 2019 01:08:17 +0000 (01:08 +0000)]
Revert r354706 - lit touched my thigh
llvm-svn: 354711
Craig Topper [Sat, 23 Feb 2019 00:38:19 +0000 (00:38 +0000)]
[LegalizeTypes] Use PromoteTargetBoolean in PromoteIntOp_ADDSUBCARRY instead of reimplementing it. NFCI
llvm-svn: 354710
Craig Topper [Sat, 23 Feb 2019 00:35:02 +0000 (00:35 +0000)]
[X86] Enable custom splitting of v8i64/v16i32 sext/zext for avx/avx2 when input type will be promoted by the type legalize to 128-bits.
If the the input type will be promoted to 128 bits its better to put a sign_extend_inreg/and in the 128 bit register before the split occurs. Otherwise we end up doing it on each half in the wider register.
Some of the overflow arithmetic tests are regressions, but I think we can make some improvement using getSetccResultType in DAG combine and/or type legalization.
llvm-svn: 354709
Craig Topper [Sat, 23 Feb 2019 00:34:58 +0000 (00:34 +0000)]
[X86] Add a few test cases for a v8i64 sext/zext from an illegal type that needs to be promoted to 128 bits.
If v8i64 isn't a legal type but v4i64 is, these will be split and then each half will get their input promoted and become an any_extend_vector_inreg/punpckhwd + any_extend + and/sign_extend_inreg.
If we instead recognize the input will be promoted we can emit the and/sign_extend_inreg first in a 128 bit register. Then we can sign_extend/zero_extend one half and pshufd+sign_extend/zero_extend the other half.
llvm-svn: 354708
Rui Ueyama [Sat, 23 Feb 2019 00:24:18 +0000 (00:24 +0000)]
Split a long line to avoid annoying horizontal scrolling on a browser.
llvm-svn: 354707
Jim Ingham [Sat, 23 Feb 2019 00:13:25 +0000 (00:13 +0000)]
Make sure that stop-hooks run asynchronously.
They aren't designed to nest recursively, so this will prevent that.
Also add a --auto-continue flag, putting "continue" in the stop hook makes
the stop hooks fight one another in multi-threaded programs.
Also allow more than one -o options so you can make more complex stop hooks w/o
having to go into the editor.
<rdar://problem/
48115661>
Differential Revision: https://reviews.llvm.org/D58394
llvm-svn: 354706
Sam Clegg [Sat, 23 Feb 2019 00:07:39 +0000 (00:07 +0000)]
[WebAssembly] Update CodeGen test expectations after rL354697. NFC
llvm-svn: 354705
Rui Ueyama [Fri, 22 Feb 2019 23:59:51 +0000 (23:59 +0000)]
s/method/function/g since function is the correct name in C++.
llvm-svn: 354704
Rui Ueyama [Fri, 22 Feb 2019 23:59:43 +0000 (23:59 +0000)]
Remove a function from header and move the implementation to a .cpp file. NFC.
llvm-svn: 354703
Jim Ingham [Fri, 22 Feb 2019 23:54:11 +0000 (23:54 +0000)]
When deserializing breakpoints some options may not be present.
The deserializer was not handling this case. For now we just
accept the absent option, and set it to the breakpoint default.
This will be more important if/when I figure out how to serialize
the options set on breakpont locations.
<rdar://problem/
48322664>
llvm-svn: 354702
Julian Lettner [Fri, 22 Feb 2019 23:37:46 +0000 (23:37 +0000)]
[NFC][Sanitizer] Re-enable test on Darwin
This unexpectedly passes on our CI, although it still fails on my
machine.
llvm-svn: 354701
Konstantin Zhuravlyov [Fri, 22 Feb 2019 23:21:06 +0000 (23:21 +0000)]
Revert "AMDGPU/NFC: Cleanup subtarget predicates"
It breaks one of our downstream merges, so revert it
temporarily while investigating failures downstream
llvm-svn: 354700
Sanjay Patel [Fri, 22 Feb 2019 23:19:34 +0000 (23:19 +0000)]
[CGP] add tests for uaddo increment/decrement; NFC
llvm-svn: 354699
Michael Kruse [Fri, 22 Feb 2019 22:29:42 +0000 (22:29 +0000)]
[OpenMP 5.0] Parsing/sema support for to clause with mapper modifier.
This patch implements the parsing and sema support for OpenMP to clause
with potential user-defined mappers attached. User defined mapper is a
new feature in OpenMP 5.0. A to/from clause can have an explicit or
implicit associated mapper, which instructs the compiler to generate and
use customized mapping functions. An example is shown below:
struct S { int len; int *d; };
#pragma omp declare mapper(id: struct S s) map(s, s.d[0:s.len])
struct S ss;
#pragma omp target update to(mapper(id): ss) // use the mapper with name 'id' to map ss to device
Contributed-by: <lildmh@gmail.com>
Differential Revision: https://reviews.llvm.org/D58523
llvm-svn: 354698
Sam Clegg [Fri, 22 Feb 2019 22:29:34 +0000 (22:29 +0000)]
[WebAssembly] Remove unneeded MCSymbolRefExpr variants
We record the type of the symbol (event/function/data/global) in the
MCWasmSymbol and so it should always be clear how to handle a relocation
based on the symbol itself.
The exception is a function which still needs the special @TYPEINDEX
then the relocation contains the signature rather than the address
of the functions.
Differential Revision: https://reviews.llvm.org/D58472
llvm-svn: 354697
Julian Lettner [Fri, 22 Feb 2019 22:03:09 +0000 (22:03 +0000)]
[NFC][Sanitizer] Rename BufferedStackTrace::FastUnwindStack
FastUnwindStack -> UnwindFast
SlowUnwindStack -> UnwindSlow
Stack is redundant, verb should come first.
SlowUnwindStackWithContext(uptr pc, void *context, u32 max_depth) ->
SlowUnwindStack
WithContext is redundant, since it is a required parameter.
Reviewers: vitalybuka
Differential Revision: https://reviews.llvm.org/D58551
llvm-svn: 354696
Julian Lettner [Fri, 22 Feb 2019 22:00:13 +0000 (22:00 +0000)]
[Sanitizer] Fix uses of stack->Unwind(..., fast)
Apply StackTrace::WillUseFastUnwind(fast) in a few more places missed by
my previous patch (https://reviews.llvm.org/D58156).
Reviewers: vitalybuka
Differential Revision: https://reviews.llvm.org/D58550
llvm-svn: 354695
Sam Clegg [Fri, 22 Feb 2019 21:41:42 +0000 (21:41 +0000)]
[WebAssembly] MC: Handle aliases of aliases
Differential Revision: https://reviews.llvm.org/D58417
llvm-svn: 354694
David Greene [Fri, 22 Feb 2019 21:19:48 +0000 (21:19 +0000)]
[CMake] Honor LLVM_EXTERNAL_<proj>_SOURCE_DIR
When LLVM_ENABLE_PROJECTS is set, CMake assumes the project
directories are all side-by-side. This is not always the case and
there's no reason to expect it if LLVM_EXTERNAL_<proj>_SOURCE_DIR is
set. Honor that setting if it exists and allow the build configuration
to continue.
Differential Revision: https://reviews.llvm.org/D49672
llvm-svn: 354693
Daniel Sanders [Fri, 22 Feb 2019 20:59:07 +0000 (20:59 +0000)]
Restore ability for C++ API users to Enable IPRA.
Summary:
Prior to r310876 one of our out-of-tree targets was enabling IPRA by modifying
the TargetOptions::EnableIPRA. This no longer works on current trunk since the
useIPRA() hook overrides any values that are set in advance. This patch adjusts
the behaviour of the hook so that API users and useIPRA() can both enable it
but useIPRA() cannot disable it if the API user already enabled it.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: wdng, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D38043
llvm-svn: 354692
Louis Dionne [Fri, 22 Feb 2019 20:48:54 +0000 (20:48 +0000)]
[clang] Only provide C11 features in <float.h> starting with C++17
Summary:
In r353970, I enabled those features in C++11 and above. To be strictly
conforming, those features should only be enabled in C++17 and above.
Reviewers: jfb, eli.friedman
Subscribers: jkorous, dexonsmith, libcxx-commits
Differential Revision: https://reviews.llvm.org/D58289
llvm-svn: 354691
Alexey Bataev [Fri, 22 Feb 2019 20:36:10 +0000 (20:36 +0000)]
[OPENMP] Delayed diagnostics for VLA support.
Generalized processing of the deferred diagnostics for OpenMP/CUDA code.
llvm-svn: 354690
Sanjay Patel [Fri, 22 Feb 2019 20:20:24 +0000 (20:20 +0000)]
[CGP] move overflow intrinsic insertion to common location; NFCI
We need to enhance the uaddo matching to handle special-cases
as seen in PR40486 and PR31754. That means we won't necessarily
have a def-use pattern, so we'll need to check dominance to
determine where to place the intrinsic (as we already do for
usubo). This preliminary patch is just rearranging the code,
so the planned follow-up to improve uaddo will be more clear.
llvm-svn: 354689
Matt Arsenault [Fri, 22 Feb 2019 19:30:38 +0000 (19:30 +0000)]
MIR: Preserve incoming frame index numbers
Don't skip incrementing the frame index number
if the object is dead. Instructions can still be
referencing the old frame index number, and this
doesn't attempt to remap those. The resulting
MIR then fails to load because the use instructions
use a higher frame index number than recorded
list of stack objects.
I'm not sure it's possible to craft a testcase
with the existing set of passes. It requires
selectively marking some stack objects
dead in an essentially random order.
StackSlotColoring condenses towards
the low indexes. This avoids a regression in a
future AMDGPU commit when some frame indexes
are lowered separately from PEI.
llvm-svn: 354688
Matt Arsenault [Fri, 22 Feb 2019 19:16:52 +0000 (19:16 +0000)]
CodeGen: Make RegAllocRegistry a template class
Will allow re-using the machinery for independent
sets of register allocators.
This will allow AMDGPU to use separate command line
options for the allocator to use for SGPRs separate
from VGPRs.
llvm-svn: 354687
Matt Arsenault [Fri, 22 Feb 2019 19:03:36 +0000 (19:03 +0000)]
AMDGPU: Use removeAllRegUnitsForPhysReg
llvm-svn: 354686
Matt Arsenault [Fri, 22 Feb 2019 19:03:31 +0000 (19:03 +0000)]
LiveIntervals: Add removeAllRegUnitsForPhysReg
Convenience wrapper for removing the reg units of
a physical register.
llvm-svn: 354685
Sam Clegg [Fri, 22 Feb 2019 19:00:03 +0000 (19:00 +0000)]
[WebAssembly] Remove debug statement submitted in rL354657
Subscribers: dschuff, jgravelle-google, hiraditya, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58549
llvm-svn: 354684
Mitch Phillips [Fri, 22 Feb 2019 18:45:41 +0000 (18:45 +0000)]
[GN] Updated build file to allow GN builds to succeed at ToT.
llvm-svn: 354683
Guozhi Wei [Fri, 22 Feb 2019 18:04:37 +0000 (18:04 +0000)]
[MBP] Factor out function hasViableTopFallthrough and enhancement
This patch factor out the function hasViableTopFallthrough from rotateLoop. It is also enhanced. Original code checks only if there is a block can be placed before current loop top. This patch also checks if the loop top is the most possible successor of its predecessor. The attached test case shows its effect.
Differential Revision: https://reviews.llvm.org/D58393
llvm-svn: 354682
Simon Pilgrim [Fri, 22 Feb 2019 17:37:59 +0000 (17:37 +0000)]
Fix "not all control paths return" warning. NFCI.
llvm-svn: 354681
Alexey Bataev [Fri, 22 Feb 2019 17:16:50 +0000 (17:16 +0000)]
Revert "[OPENMP] Delayed diagnostics for VLA support."
This reverts commit r354679 to fix the problem with the Windows
buildbots
llvm-svn: 354680
Alexey Bataev [Fri, 22 Feb 2019 16:49:13 +0000 (16:49 +0000)]
[OPENMP] Delayed diagnostics for VLA support.
Generalized processing of the deferred diagnostics for OpenMP/CUDA code.
llvm-svn: 354679
Saleem Abdulrasool [Fri, 22 Feb 2019 16:29:50 +0000 (16:29 +0000)]
CodeGen: use COMDAT for block copy/destroy helpers
SVN r339438 added support to deduplicate the helpers by using a consistent
naming scheme and using LinkOnceODR semantics. This works on ELF by means of
weak linking semantics, and entirely does not work on PE/COFF where you end up
with multiply defined strong symbols, which is a strong error on PE/COFF.
Assign the functions a COMDAT group so that they can be uniqued by the linker.
This fixes the use of blocks in CoreFoundation on Windows.
llvm-svn: 354678
Nirav Dave [Fri, 22 Feb 2019 16:20:34 +0000 (16:20 +0000)]
Disable big-endian constant store merges from rL354676.
llvm-svn: 354677
Nirav Dave [Fri, 22 Feb 2019 16:00:19 +0000 (16:00 +0000)]
[DAGCombine] Fold overlapping constant stores
Fold a smaller constant store into larger constant stores immediately
preceeding it.
Reviewers: rnk, courbet
Subscribers: javed.absar, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58468
llvm-svn: 354676
Sanjay Patel [Fri, 22 Feb 2019 15:47:45 +0000 (15:47 +0000)]
[x86] allow narrowing of vector UINT_TO_FP
As discussed in:
D56864
D58197
Always use the narrow (128-bit) instruction when possible.
We already had the signed int version of this transform.
llvm-svn: 354675
Sanjay Patel [Fri, 22 Feb 2019 15:28:22 +0000 (15:28 +0000)]
[x86] simplify code in combineExtractSubvector; NFC
Only the 1st fold is attempted pre-legalization, but it requires
legal (simple) types too, so we don't need an EVT in any of the code.
llvm-svn: 354674
Matt Arsenault [Fri, 22 Feb 2019 15:01:41 +0000 (15:01 +0000)]
BreakCriticalEdges: Update PostDominatorTree
llvm-svn: 354673
Petar Jovanovic [Fri, 22 Feb 2019 14:53:58 +0000 (14:53 +0000)]
[mips][micromips] fix filling delay slots for PseudoIndirectBranch_MM
Filling a delay slot in 32bit jump instructions with a 16bit instruction
can cause issues. According to the documentation such an operation is
unpredictable.
This patch adds opcode Mips::PseudoIndirectBranch_MM alongside
Mips::PseudoIndirectBranch and other instructions that are expanded to jr
instruction and do not allow a 16bit instruction in their delay slots.
Patch by Mirko Brkusanin.
Differential Revision: https://reviews.llvm.org/D58507
llvm-svn: 354672
Alexey Bataev [Fri, 22 Feb 2019 14:42:48 +0000 (14:42 +0000)]
[CUDA]Delayed diagnostics for the asm instructions.
Adapted targetDiag for the CUDA and used for the delayed diagnostics in
asm constructs. Works for both host and device compilation sides.
Differential Revision: https://reviews.llvm.org/D58463
llvm-svn: 354671
Roman Tereshin [Fri, 22 Feb 2019 14:33:46 +0000 (14:33 +0000)]
[LowerSwitch][AMDGPU] Do not handle impossible values
This patch adds LazyValueInfo to LowerSwitch to compute the range of the
value being switched over and reduce the size of the tree LowerSwitch
builds to lower a switch.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D58096
llvm-svn: 354670
Chijun Sima [Fri, 22 Feb 2019 13:48:38 +0000 (13:48 +0000)]
[DTU] Refine the interface and logic of applyUpdates
Summary:
This patch separates two semantics of `applyUpdates`:
1. User provides an accurate CFG diff and the dominator tree is updated according to the difference of `the number of edge insertions` and `the number of edge deletions` to infer the status of an edge before and after the update.
2. User provides a sequence of hints. Updates mentioned in this sequence might never happened and even duplicated.
Logic changes:
Previously, removing invalid updates is considered a side-effect of deduplication and is not guaranteed to be reliable. To handle the second semantic, `applyUpdates` does validity checking before deduplication, which can cause updates that have already been applied to be submitted again. Then, different calls to `applyUpdates` might cause unintended consequences, for example,
```
DTU(Lazy) and Edge A->B exists.
1. DTU.applyUpdates({{Delete, A, B}, {Insert, A, B}}) // User expects these 2 updates result in a no-op, but {Insert, A, B} is queued
2. Remove A->B
3. DTU.applyUpdates({{Delete, A, B}}) // DTU cancels this update with {Insert, A, B} mentioned above together (Unintended)
```
But by restricting the precondition that updates of an edge need to be strictly ordered as how CFG changes were made, we can infer the initial status of this edge to resolve this issue.
Interface changes:
The second semantic of `applyUpdates` is separated to `applyUpdatesPermissive`.
These changes enable DTU(Lazy) to use the first semantic if needed, which is quite useful in `transforms/utils`.
Reviewers: kuhar, brzycki, dmgreen, grosser
Reviewed By: brzycki
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58170
llvm-svn: 354669
Pavel Labath [Fri, 22 Feb 2019 13:36:01 +0000 (13:36 +0000)]
Avoid two-stage initialization of MinidumpParser
remove the Initialize function, move the things that can fail into the
static factory function. The factory function now returns
Expected<Parser> instead of Optional<Parser> so that it can give a
reason why creation failed.
llvm-svn: 354668
David Green [Fri, 22 Feb 2019 12:23:31 +0000 (12:23 +0000)]
[ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs
This adds a number of missing Thumb1 opcodes so that the peephole optimiser can
remove redundant CMP instructions.
Reapplying this after the first attempt broke non-thumb1 code as the t2ADDri
instruction can be used with frame indices. In thumb1 we use tADDframe.
Differential Revision: https://reviews.llvm.org/D57833
llvm-svn: 354667
James Henderson [Fri, 22 Feb 2019 11:22:39 +0000 (11:22 +0000)]
[ELF][test]Remove unnecessary empty symbol references in yaml/add missing symbols for relocs
yaml2obj used to require the Symbol field in relocations, but it hasn't
done so for a couple of years. Another change to yaml2obj will soon land
that will look up the symbol by name or index, if present, and emit an
error if not found. This will mean that an explicit symbol reference
(even to an empty-named symbol) that does not reference a symbol
declared in the yaml will result in an error.
This patch updates tests that would otherwise start emitting errors.
Reviewed by: ruiu, grimar
Differential Revision: https://reviews.llvm.org/D58508
llvm-svn: 354666
Diana Picus [Fri, 22 Feb 2019 09:54:54 +0000 (09:54 +0000)]
[ARM GlobalISel] Support floating point for Thumb2
This is exactly the same as arm mode, so for the instruction selector
tests we just extract them to a new file and run with the same checks
for both arm and thumb mode.
For the legalizer we need to update the tests for soft float a bit, but
only because BL and tBL are slightly different. We could be pedantic and
check that we get a well-formed BL for arm mode and a tBL for thumb, but
for the purposes of the legalizer test it's sufficient to just skip over
the predicate operands in the checks. Also note that we have the
pedantic checks in the divmod test, so we're covered.
llvm-svn: 354665
Haojian Wu [Fri, 22 Feb 2019 09:43:56 +0000 (09:43 +0000)]
[clangd] Don't attach FixIt to the source code in macro.
Summary:
We are less certain it is the correct fix. Also, clang doesn't apply FixIt to
the source code in macro.
Reviewers: ilya-biryukov
Reviewed By: ilya-biryukov
Subscribers: ioeric, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D58525
llvm-svn: 354664
George Rimar [Fri, 22 Feb 2019 08:58:23 +0000 (08:58 +0000)]
Fix BB after r354661
Update 2 test cases after obj2yaml fix in r354661.
llvm-svn: 354663
Pavel Labath [Fri, 22 Feb 2019 08:51:08 +0000 (08:51 +0000)]
Split up minidump register context tests
The tests were doing two somewhat independent things:
- checking that the registers can be retrieved from the minidump file
- checking that they can be converted into a form suitable for
consumption by lldb
The first thing requires a minidump file (but it's independent of other
lldb structures), while the second one does not require a minidump file
(but it needs lldb register info structures).
Splitting this into two tests gives an opportunity to write more
detailed tests, and allows the two pieces of functionality to be moved
into different packages, if that proves to be necessary.
llvm-svn: 354662
George Rimar [Fri, 22 Feb 2019 08:45:21 +0000 (08:45 +0000)]
[obj2yaml] - Do not miss section index for special symbols.
This fixes https://bugs.llvm.org/show_bug.cgi?id=40786
("obj2yaml symbol output missing section index for SHN_ABS and SHN_COMMON symbols")
Since SHN_ABS and SHN_COMMON symbols are special, we should preserve
the st_shndx for them. The patch does this for them and the other special symbols.
The test case is based on the test provided by James Henderson at the bug page!
Differential revision: https://reviews.llvm.org/D58498
llvm-svn: 354661
Alina Sbirlea [Fri, 22 Feb 2019 07:34:54 +0000 (07:34 +0000)]
[MemorySSA] Update test with minimized one. NFCI
llvm-svn: 354658
Heejin Ahn [Fri, 22 Feb 2019 07:19:30 +0000 (07:19 +0000)]
[WebAssembly] Remove getBottom function from CFGStackify (NFC)
Summary:
This removes `getBottom` function and the bookeeping map of <begin
marker instruction, bottom BB>.
Reviewers: dschuff
Subscribers: sunfish, sbc100, jgravelle-google, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58319
llvm-svn: 354657
Alina Sbirlea [Fri, 22 Feb 2019 07:18:37 +0000 (07:18 +0000)]
[MemorySSA & LoopPassManager] Resolve PR40038.
The correct edge being deleted is not to the unswitched exit block, but to the
original block before it was split. That's the key in the map, not the
value.
The insert is correct. The new edge is to the .split block.
The splitting turns OriginalBB into:
OriginalBB -> OriginalBB.split.
Assuming the orignal CFG edge: ParentBB->OriginalBB, we must now delete
ParentBB->OriginalBB, not ParentBB->OriginalBB.split.
llvm-svn: 354656
Craig Topper [Fri, 22 Feb 2019 07:03:25 +0000 (07:03 +0000)]
[LegalizeVectorOps] Improve the placement of ANDs in the ExpandLoad path for non-byte-sized loads.
When we need to merge two adjacent loads the AND mask for the low piece was still sized for the full src element size. But we didn't have that many bits. The upper bits are already zero due to the SRL. So we can skip the AND if we're going to combine with the high bits.
We do need an AND to clear out any bits from the high part. We were anding the high part before combining with the low part, but it looks like ANDing after the OR gets better results.
So we can just emit the final AND after the optional concatentation is done. That will handling skipping before the OR and get rid of extra high bits after the OR.
llvm-svn: 354655
Craig Topper [Fri, 22 Feb 2019 06:18:33 +0000 (06:18 +0000)]
[LegalizeVectorOps] Simplify the non-byte sized load handling VectorLegalizer::ExpandLoad. NFCI
Remove an if that should always be true. Merge the body of another into the only block that could make the if true.
llvm-svn: 354654
Craig Topper [Fri, 22 Feb 2019 06:18:32 +0000 (06:18 +0000)]
[X86] Add test cases to cover the path in VectorLegalizer::ExpandLoad for non-byte sized loads where bits from two loads need to be concatenated.
If the scalar type doesn't divide evenly into the WideVT then the code will need to take some bits from adjacent scalar loads and combine them.
But most of our testing is for i1 element type which always divides evenly.
llvm-svn: 354653
Chijun Sima [Fri, 22 Feb 2019 05:41:43 +0000 (05:41 +0000)]
[DTU] Deprecate insertEdge*/deleteEdge*
Summary: This patch converts all existing `insertEdge*/deleteEdge*` to `applyUpdates` and marks `insertEdge*/deleteEdge*` as deprecated.
Reviewers: kuhar, brzycki
Reviewed By: kuhar, brzycki
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58443
llvm-svn: 354652
Yaxun Liu [Fri, 22 Feb 2019 04:20:12 +0000 (04:20 +0000)]
revert r354615: [HIP] change kernel stub name
It caused regressions.
Differential Revision: https://reviews.llvm.org/D58518
llvm-svn: 354651
Lang Hames [Fri, 22 Feb 2019 03:56:50 +0000 (03:56 +0000)]
Fix a think-o in the disable-kaleidoscope-tests-on-windows predicate of r354646.
llvm-svn: 354650
Matt Arsenault [Fri, 22 Feb 2019 03:38:47 +0000 (03:38 +0000)]
DAG: Add helper for creating shifts with correct type
llvm-svn: 354649
Craig Topper [Fri, 22 Feb 2019 01:49:53 +0000 (01:49 +0000)]
[X86] Add a DAG combine for (aext_vector_inreg (aext_vector_inreg X)) -> (aext_vector_inreg X) to fix a regression from my previous commit.
Type legalization is causing two nodes to be created here, but we can use a single node to extend from v8i16 to v2i64.
llvm-svn: 354648
Craig Topper [Fri, 22 Feb 2019 01:49:50 +0000 (01:49 +0000)]
[LegalizeTypes] When promoting the result of EXTRACT_SUBVECTOR, also check if the input needs to be promoted. Use that to determine the element type to extract.
Otherwise we end up creating extract_vector_elts that then each need to have their input promoted. This can lead to truncates needing to be emitted for each of those.
But we already emitted any_extends when we legalized the extract_subvector. So now we have pairs of any_extend+trunc that partially cancel. But depending on how DAGCombiner visits them we can get weird results.
By promoting the input at the same time we can create only a single any_extend or truncate.
There's one regression in the vector-narrow-binop.ll case, but that looks easy to fix with a follow up patch.
llvm-svn: 354647
Lang Hames [Fri, 22 Feb 2019 01:44:23 +0000 (01:44 +0000)]
Add 'Windows' to the disabled platforms list for the Kaleidoscope tests.
Expands on the check from r354645.
llvm-svn: 354646
Lang Hames [Fri, 22 Feb 2019 01:19:53 +0000 (01:19 +0000)]
Disable Kaleidoscope tests on Win32 -- looks like they're still failing there.
The Kaleidoscope tests were re-enabled in r354630, but are still failing on
Windows. This patch disables them on that platform until the failure can be
investigated.
llvm-svn: 354645
Artem Dergachev [Fri, 22 Feb 2019 00:18:46 +0000 (00:18 +0000)]
[analyzer] MIGChecker: Enable by default as `osx.MIG'.
With r354643, the checker is feature-rich and polished enough.
rdar://problem/
35380337
Differential Revision: https://reviews.llvm.org/D58397
llvm-svn: 354644
Artem Dergachev [Fri, 22 Feb 2019 00:15:14 +0000 (00:15 +0000)]
[analyzer] MIGChecker: Add support for more APIs.
Add more "consuming" functions. For now only vm_deallocate() was supported.
Add a non-zero value that isn't an error; this value is -305 ("MIG_NO_REPLY")
and it's fine to deallocate data when you are returning this error.
Make sure that the mig_server_routine annotation is inherited.
rdar://problem/
35380337
Differential Revision: https://reviews.llvm.org/D58397
llvm-svn: 354643
Artem Dergachev [Fri, 22 Feb 2019 00:09:56 +0000 (00:09 +0000)]
[analyzer] MIGChecker: Fix an FN when the object is released in a destructor.
When a MIG server routine argument is released in an automatic destructor,
the Static Analyzer thinks that this happens after the return statement, and so
the violation of the MIG convention doesn't happen.
Of course, it doesn't quite work that way, so this is a false negative.
Add a hack that makes the checker double-check at the end of function
that no argument was released when the routine fails with an error.
rdar://problem/
35380337
Differential Revision: https://reviews.llvm.org/D58392
llvm-svn: 354642
Artem Dergachev [Fri, 22 Feb 2019 00:06:30 +0000 (00:06 +0000)]
[analyzer] MIGChecker: Improve intermediate diagnostic notes.
Add a BugReporterVisitor for highlighting the events of deallocating a
parameter. All such events are relevant to the emitted report (as long as the
report is indeed emitted), so all of them will get highlighted.
Add a trackExpressionValue visitor for highlighting where does the error return
code come from.
Do not add a trackExpressionValue visitor for highlighting how the deallocated
argument(s) was(were) copied around. This still remains to be implemented.
rdar://problem/
35380337
Differential Revision: https://reviews.llvm.org/D58368
llvm-svn: 354641
Craig Topper [Fri, 22 Feb 2019 00:04:35 +0000 (00:04 +0000)]
[X86] Fix some copy/paste mistakes that caused a VR128 to be used as the address of a load in an isel pattern
This was introduced in r354511.
Fixes PR40811.
llvm-svn: 354640
Jonas Devlieghere [Fri, 22 Feb 2019 00:03:59 +0000 (00:03 +0000)]
Revert "[xcodeproj] Add SBReproducer to LLDB.framework"
This was bogus.
llvm-svn: 354639