Alyssa Rosenzweig [Thu, 14 Apr 2022 01:05:02 +0000 (21:05 -0400)]
agx: Split up RA from post-RA lowering
This allows us to validate results in the middle.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:11:23 +0000 (23:11 -0400)]
agx: Lower phi nodes to parallel copies
Now we have an SSA RA :-)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 01:40:35 +0000 (21:40 -0400)]
agx: Don't lower phis in NIR
We're ready for them now! Just scalarize.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Mon, 18 Apr 2022 22:55:38 +0000 (18:55 -0400)]
agx: Copy prop into phi nodes
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 01:40:23 +0000 (21:40 -0400)]
agx: Translate phi nodes
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 22:34:50 +0000 (18:34 -0400)]
agx: Make DCE dumber
The current DCE pass hits issue around phi nodes. These need to be
solved properly eventually, but for now workaround them by doing
something obviously correct (but suboptimal compile time).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Thu, 14 Apr 2022 01:04:36 +0000 (21:04 -0400)]
agx: Adapt liveness analysis for SSA
Lifted from nir_liveness.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Sun, 1 May 2022 19:53:35 +0000 (15:53 -0400)]
agx: Introduce worklist infrastructure
Using the common NIR stuff.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:33:09 +0000 (23:33 -0400)]
agx: Add agx_after_block_logical helper
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:32:18 +0000 (23:32 -0400)]
agx: Mark the logical ends of blocks
We need to insert parallel copies at the logical end of blocks, before branches.
Add a pseudo instruction signaling that. Cribbed from ACO.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:10:47 +0000 (23:10 -0400)]
agx: Add predecessor index helper
To order phi sources.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 02:06:06 +0000 (22:06 -0400)]
agx: Use a dynarray for predecessors
This imposes a fixed ordering, allowing phi sources to be implicitly ordered.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:18:03 +0000 (23:18 -0400)]
agx: Remove else optimization
It will conflict with SSA-based RA and needs to be rewritten to happen
late.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Sun, 1 May 2022 20:24:18 +0000 (16:24 -0400)]
agx: Use extract helper for tex internally
Allows better optimization.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 23:46:13 +0000 (19:46 -0400)]
agx: Emit splits for intrinsics
This allows optimizing the extracts.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 00:58:49 +0000 (20:58 -0400)]
agx: Optimize p_split(kill) specially
Let's make sure these are allocated optimally.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 00:43:32 +0000 (20:43 -0400)]
agx: Lower p_split after RA
Using existing regalloc infrastructure.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Sun, 17 Apr 2022 20:47:37 +0000 (16:47 -0400)]
agx: Use a transfer graph for parallel copies
Lifted from ir3. Algorithm is the same; the data structures and interface are
lightly modified to decouple from ir3's IR.
Sequentializing parallel copies after RA is tricky. ir3's implementation works
well enough, so I use that one.
Original implementation by Connor Abbott.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 23:45:34 +0000 (19:45 -0400)]
agx: Add helper to emit splits
This should be used for vector destinations, to facilitate the extraction
optimization.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 00:44:20 +0000 (20:44 -0400)]
agx: Add helper to emit combines
...in such a way that subsequent extracts will be optimized.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 23:43:46 +0000 (19:43 -0400)]
agx: Add a hash table for vector extracts
This will allow us to introduce splits gradually, giving a graceful fallback.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 01:41:34 +0000 (21:41 -0400)]
agx: Add phi pseudo instruction
For SSA.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 00:43:56 +0000 (20:43 -0400)]
agx: Add p_split pseudoinstruction
Easier on RA for extracts.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 01:29:18 +0000 (21:29 -0400)]
agx: Dynamically allocate agx_instr->src
Required for phi nodes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 23:27:00 +0000 (19:27 -0400)]
agx: Implement simple copyprop
Cleans up some of the mess.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:16 +0000 (18:06 -0400)]
agx: Use pseudo ops for mov/not/and/xor/or
Rather than using builder magic (implicitly lowered on emit), add actual pseudo
operations (explicitly lowered before encoding). In theory this is slower, I
doubt it matters. This makes the instruction aliases first-class for IR prining
and machine inspection, which will make optimization passes easier to write.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:13 +0000 (18:06 -0400)]
agx: Add unit test infrastructure
Lifted from Bifrost. Add some basic optimizer tests (they pass!) to show the
compiler is ready to be unit tested. Given we can't have hardware CI for Asahi
yet -- and dEQP is still pretty janky -- unit testing should prove quite useful.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:12 +0000 (18:06 -0400)]
agx: Wrap compiler header in extern "C"
So we can use it from GTest.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:10 +0000 (18:06 -0400)]
agx: Use correct types for some IR enums
Otherwise there are implicit int->enum casts which prevent us from building as
C++ (with -fpermissive).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:08 +0000 (18:06 -0400)]
agx: Match order for designated initializers
Required to compile our headers with C++, to allow us to use GTest unit tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:03 +0000 (18:06 -0400)]
agx: Track write registers more accurately
We may not write a full 32-bit vec4, don't be so pessimistic.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:01 +0000 (18:06 -0400)]
agx: Note that RA proceeds in dominance-order
This is an important invariant for SSA-based RA to work.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:05:59 +0000 (18:05 -0400)]
agx: Implement some shader-db stats
Instructions, bytes, and registers -- this should hold us over until we
can reverse the underlying uarch and get proper cycle estimations.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Mon, 18 Apr 2022 00:25:23 +0000 (20:25 -0400)]
asahi: Workaround broken GLSL compiler
https://gitlab.freedesktop.org/mesa/mesa/-/issues/6075 still hasn't been
fixed (despite the bug being known for a year now..)
Workaround the brokenness.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Rob Clark [Sat, 30 Apr 2022 17:24:08 +0000 (10:24 -0700)]
freedreno/drm: Fix bos_on_stack calculation
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16263>
Konstantin Seurer [Sat, 30 Apr 2022 21:53:43 +0000 (23:53 +0200)]
radv: Use the entire morton code as sort key
Fixes: be57b08 <"radv: Build accaleration structures using LBVH">
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16264>
Konstantin Seurer [Sat, 30 Apr 2022 09:25:37 +0000 (11:25 +0200)]
radv/radix_sort: Make variable names consistent
We usually use pdevice for "physical device" and not "device pointer".
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16259>
Konstantin Seurer [Sat, 30 Apr 2022 09:19:49 +0000 (11:19 +0200)]
radv/radix_sort: Add missing entry points
Fixes: 5d9ef0e ("radv: Add the fuchsia radix sort")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16259>
Yiwei Zhang [Sat, 9 Apr 2022 02:48:42 +0000 (02:48 +0000)]
venus: enable ANB shared presentable image prop
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15868>
Yiwei Zhang [Sat, 9 Apr 2022 02:46:00 +0000 (02:46 +0000)]
venus: update vn_GetSwapchainGrallocUsage2ANDROID for shared present
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15868>
Yiwei Zhang [Sat, 9 Apr 2022 00:21:53 +0000 (00:21 +0000)]
venus: cache front_rendering_usage bit at gralloc init
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15868>
Yiwei Zhang [Fri, 8 Apr 2022 23:13:35 +0000 (23:13 +0000)]
venus: refactor android gralloc pieces
There's no functional change.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15868>
Francisco Jerez [Wed, 27 Oct 2021 00:18:58 +0000 (17:18 -0700)]
intel/dev: Compute pixel pipe information based on geometry topology DRM query.
This changes the intel_device_info calculation to call an additional
DRM query requesting the geometry topology from the kernel, which may
differ from the result of the current topology query on XeHP+
platforms with compute-only and 3D-only DSSes. This seems more
reliable than the current guesswork done in intel_device_info.c trying
to figure out which DSSes are available for the render CS.
Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143>
Emma Anholt [Thu, 14 Apr 2022 03:25:59 +0000 (20:25 -0700)]
nouveau: Enable the NIR backend by default.
The glsl-to-tgsi code generation and GLSL IR linker is is going away
(!8044), so we need to make the call on whether to use nir-to-tgsi (See
!15932 and !15541), or switch over to the NIR code generator. The NIR
backend should reduce the compile time regression while providing more
direct control over the IR we receive than going through NTT, while still
providing the optimization that NIR-to-TGSI was bringing us.
nv92 shader-db:
total local in shared programs: 2048 -> 1988 (-2.93%)
local in affected programs: 2048 -> 1988 (-2.93%)
total gpr in shared programs: 688468 -> 724705 (5.26%)
gpr in affected programs: 437159 -> 473396 (8.29%)
total instructions in shared programs: 6115978 -> 5874401 (-3.95%)
instructions in affected programs: 5038041 -> 4796464 (-4.80%)
total loops in shared programs: 1361 -> 835 (-38.65%)
loops in affected programs: 538 -> 12 (-97.77%)
total bytes in shared programs:
42389752 ->
40480416 (-4.50%)
bytes in affected programs:
36311616 ->
34402280 (-5.26%)
LOST: 0
GAINED: 1 (pixmark-piano)
nv120 shader-db:
total local in shared programs: 4416 -> 1988 (-54.98%)
local in affected programs: 4416 -> 1988 (-54.98%)
total gpr in shared programs: 870534 -> 893490 (2.64%)
gpr in affected programs: 564210 -> 587166 (4.07%)
total instructions in shared programs: 6379402 -> 6243210 (-2.13%)
instructions in affected programs: 5430790 -> 5294598 (-2.51%)
total bytes in shared programs:
68184224 ->
66729672 (-2.13%)
bytes in affected programs:
58013544 ->
56558992 (-2.51%)
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Emma Anholt [Mon, 25 Apr 2022 23:32:39 +0000 (16:32 -0700)]
nouveau/nir: Put the UBO offset indirect into the address reg.
Fixes indirect UBO addressing pre-nvc0.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Karol Herbst [Mon, 25 Apr 2022 20:21:16 +0000 (22:21 +0200)]
nv50/nir: align tlsspace to 0x10
nvc0 aligns to 0x10 in setting up its rogram header, but nv50 TLS
allocation expects the incoming value to be aligned already (like TGSI
always did). Avoids regression in
KHR-GL33.shaders.arrays.declaration.dynamic_expression_array_access_* with
the nir backend.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Emma Anholt [Sun, 24 Apr 2022 19:44:23 +0000 (12:44 -0700)]
nouveau/nir: Add support for pre-GF100 images and ssbos.
We have to allocate them slots in the global file.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Emma Anholt [Sun, 24 Apr 2022 17:19:34 +0000 (10:19 -0700)]
ci/nouveau: Add MESA_GLES_VERSION_OVERRIDE=3.1 baseline state.
imirkin requested that I test the GLES31 codepaths on nv50, and this is
the best I can do with the hardware I have.
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Emma Anholt [Wed, 20 Apr 2022 23:30:37 +0000 (16:30 -0700)]
nouveau/nir: Move FS output stores to the end of the last block.
The nir_move/sink caused instructions to sink interleaved into the output
stores at the end of the shader. nouveau's RA doesn't track liveness of
FS outputs in registers after the export instruction, so they could end up
overwritten. To work around it, after normal NIR move/sink, move the
output stores back to the end of the shader.
Fixes:
b1fa2068b8e8 ("nouveau/nir: Enable nir_opt_move/sink.")
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Chia-I Wu [Tue, 26 Apr 2022 04:45:50 +0000 (21:45 -0700)]
turnip: fix drm modifier support with planar formats
We need to advertise the results of tu6_plane_count and handle
VK_IMAGE_ASPECT_MEMORY_PLANE_*_BIT.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6374
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16169>
Erik Faye-Lund [Thu, 28 Apr 2022 09:47:37 +0000 (11:47 +0200)]
mesa: add missing error-path
The ARB_shader_objects spec says the following:
> The error INVALID_VALUE is generated by any command that takes one or
> more handles as input, and one or more of these handles are not an
> object handle generated by OpenGL.
And a long, long time ago, we used do to just that for
glDeleteObjectARB... Until
9ac9605de15, all the way back in February 2006,
where the error condition was removed without explanation.
Let's restore it, because it should really be there.
This was noticed by running the tests that are in the mesa-demos
repository, that actually tested this condition.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16211>
Erik Faye-Lund [Fri, 29 Apr 2022 07:20:33 +0000 (09:20 +0200)]
gallium/xlib: fix stale comment
We haven't been doing what the comment says for about a decade, it's
about time to update the comment!
Fixes:
5f60a00743f ("st/glx: remove STENCIL_BITS, DEFAULT_SOFTWARE_DEPTH_BITS")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16213>
Erik Faye-Lund [Fri, 29 Apr 2022 07:15:58 +0000 (09:15 +0200)]
meson: deprecate specifying osmesa-bits
This option has no meaningful effect any more other than pointlessly
renaming the the library. Let's introduce a new default value called
"unspecified", and complain if it's set to anything else.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16213>
Erik Faye-Lund [Thu, 28 Apr 2022 12:05:14 +0000 (14:05 +0200)]
meson: remove unused defines
These defines are no longer used since we removed libmesa_classic.
Fixes:
e030d5ba8ac ("mesa: Delete libmesa_classic")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16213>
Jordan Justen [Fri, 29 Apr 2022 09:37:25 +0000 (02:37 -0700)]
iris: Fix assertion meant to only target the clear-color stride
Fixes:
2bc8c61fd00 ("iris: Return a 64B stride for clear color plane")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6398
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16241>
Jesse Natalie [Thu, 28 Apr 2022 20:52:11 +0000 (13:52 -0700)]
microsoft/compiler: Unload DXIL validator library *after* calling Release()
Otherwise, the code to actually run Release() might not be loaded or
callable anymore.
Fixes:
193cf76c ("microsoft/compiler: add common dxil-validator API")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16225>
Daniel Schürmann [Fri, 25 Mar 2022 11:03:27 +0000 (12:03 +0100)]
aco/optimizer: prevent any overflow between SGPR and const offset on MUBUF
Apparently, if the SGPR offset + const offset overflows,
it doesn't work.
Totals from 145 (0.11% of 134913) affected shaders: (GFX10.3)
SpillSGPRs: 134 -> 104 (-22.39%)
CodeSize: 1632676 -> 1645916 (+0.81%); split: -0.03%, +0.84%
Instrs: 316920 -> 320252 (+1.05%); split: -0.01%, +1.07%
Latency: 1456285 -> 1459686 (+0.23%); split: -0.02%, +0.25%
InvThroughput: 165785 -> 166086 (+0.18%); split: -0.02%, +0.20%
VClause: 6815 -> 6875 (+0.88%); split: -0.03%, +0.91%
SClause: 19089 -> 19079 (-0.05%); split: -0.06%, +0.01%
PreSGPRs: 7302 -> 7304 (+0.03%); split: -0.01%, +0.04%
Fixes: KHR-GL45.shader_storage_buffer_object.basic-operations-case1-cs
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15866>
Daniel Schürmann [Tue, 19 Apr 2022 09:33:22 +0000 (11:33 +0200)]
aco: adjust num_waves for LDS before scheduling
Totals from 67 (0.05% of 134913) affected shaders: (GFX10.3)
VGPRs: 2024 -> 2136 (+5.53%); split: -0.40%, +5.93%
CodeSize: 162364 -> 162348 (-0.01%); split: -0.08%, +0.07%
MaxWaves: 1882 -> 1816 (-3.51%); split: +0.11%, -3.61%
Instrs: 29176 -> 29162 (-0.05%); split: -0.09%, +0.04%
Latency: 329984 -> 327272 (-0.82%); split: -0.88%, +0.06%
InvThroughput: 54653 -> 54672 (+0.03%); split: -0.01%, +0.04%
VClause: 782 -> 761 (-2.69%); split: -2.81%, +0.13%
SClause: 833 -> 824 (-1.08%); split: -2.28%, +1.20%
Copies: 1872 -> 1873 (+0.05%); split: -0.37%, +0.43%
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16039>
Daniel Schürmann [Tue, 19 Apr 2022 09:32:56 +0000 (11:32 +0200)]
aco: split num_waves adjustment into separate function
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16039>
Daniel Schürmann [Tue, 19 Apr 2022 14:58:26 +0000 (16:58 +0200)]
aco: remove 'max_waves' and use 'num_waves' to adjust for LDS and workgroup size
Totals from 21 (0.02% of 134913) affected shaders: (GFX10.3)
VGPRs: 1024 -> 1176 (+14.84%)
CodeSize: 127824 -> 127664 (-0.13%); split: -0.17%, +0.04%
MaxWaves: 416 -> 378 (-9.13%)
Instrs: 22521 -> 22502 (-0.08%); split: -0.17%, +0.09%
Latency: 146386 -> 143154 (-2.21%); split: -2.21%, +0.00%
InvThroughput: 28379 -> 28944 (+1.99%); split: -0.23%, +2.22%
VClause: 575 -> 579 (+0.70%); split: -0.87%, +1.57%
SClause: 692 -> 645 (-6.79%)
Copies: 780 -> 747 (-4.23%); split: -4.74%, +0.51%
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16039>
Danylo Piliaiev [Fri, 29 Apr 2022 14:39:25 +0000 (17:39 +0300)]
turnip: Fix tu_debug_flags values clashing
Was not caught during rebase...
Fixes:
725ae34458ff3cbb9d87e08c8a73780672221a9e
("turnip: Add debug option to print gmem load/store skip stats")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16246>
Juan A. Suarez Romero [Thu, 28 Apr 2022 16:05:55 +0000 (18:05 +0200)]
mesa: unref syncobj after wait_sync
Before returning the wait_sync() function, the sync object must be
unreferenced.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6377
Fixes:
0af7c1e385b ("mesa/st: merge the syncobj code from st into mesa")
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16242>
Samuel Pitoiset [Fri, 29 Apr 2022 07:38:00 +0000 (09:38 +0200)]
radv/ci: stop skipping dEQP-VK.synchronization.* on Bonaire
I can't reproduce GPU hangs after 5 CTS runs and Timur also confirmed
that his Bonaire GPU didn't hang after one CTS run.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16244>
Samuel Pitoiset [Tue, 12 Apr 2022 14:36:45 +0000 (16:36 +0200)]
radv: fix the number of generated primitive queries with NGG GS vs legacy
With NGG GS, the hardware can't know the number of generated primitives
and we have to increment it manually from the shader using a plain GDS
atomic operation.
Though this had a serious problem (see this old TODO) if the bound
pipeline was using legacy GS because the query implementation was
relying on NGG GS. Another situation is if we had one draw with NGG GS,
followed by one draw with legacy (or the opposite) the query result
would have been broken.
The solution is to allocate two 64-bit values for storing the begin/end
values if the query pool is supposed to need GDS and accumulate the
result with the number of generated primitives generated by the hw.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15892>
Danylo Piliaiev [Fri, 15 Apr 2022 14:26:48 +0000 (17:26 +0300)]
turnip: Add debug option to print gmem load/store skip stats
TU_DEBUG=log_skip_gmem_ops would print stats about skipped
gmem/load every second.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15974>
Danylo Piliaiev [Thu, 14 Apr 2022 14:19:21 +0000 (17:19 +0300)]
turnip: Skip load/stores for tiles with no geometry
When HW binning is used tile loads/stores could be skipped
if there is no geometry in the tile.
Loads could be skipped when:
- The attachment won't be resolved, otherwise if load is skipped
there would be holes in the resolved attachment;
- There is no vkCmdClearAttachments afterwards since it is likely
a partial clear done via 2d blit (2d blit doesn't produce geometry).
Stores could be skipped when:
- The attachment was not cleared, which may happen by load_op or
vkCmdClearAttachments;
- When store is not a resolve.
I chose to predicate each load/store separately to allow them to be
skipped when only some attachments are cleared or resolved.
Gmem loads are moved into separate cs because whether to emit
CP_COND_REG_EXEC depends on HW binning being enabled and usage of
vkCmdClearAttachments.
CP_COND_REG_EXEC predicate could be changed during draw_cs only
by perf query, in such case the predicate should be re-emitted.
(At the moment it is always re-emitted before stores)
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15974>
Danylo Piliaiev [Thu, 14 Apr 2022 14:15:49 +0000 (17:15 +0300)]
freedreno/a6xx: Add UNK fields to CP_REG_TEST and CP_COND_REG_EXEC
Their meaning is unknown, however they DO change the behavior.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15974>
Gert Wollny [Sun, 17 Apr 2022 15:25:18 +0000 (17:25 +0200)]
virgl: don't move input gl_SampleMaskIn to a temp
The input is an array so moving it to a single temporary value doesn't
seem to make much sense. I also don't see any piglit regressions when
not moving the value to a temporary.
Fixes:
bc912bace1cf8cd03793c5ae34bd5a2afd015019
virgl: Add workarounds for virglrenderer input/sv signedness bugs.
v2: remove unused enum for SAMPLEMASK (Emma)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15997>
Samuel Pitoiset [Fri, 29 Apr 2022 07:42:03 +0000 (09:42 +0200)]
radv/ci: remove empty flakes lists for GFX9
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16239>
Pierre-Eric Pelloux-Prayer [Mon, 25 Apr 2022 12:19:24 +0000 (14:19 +0200)]
radeonsi: enable PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16139>
Pierre-Eric Pelloux-Prayer [Mon, 25 Apr 2022 12:19:02 +0000 (14:19 +0200)]
gallium: add PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER
This way we can make allow_draw_out_of_order true by default for all
apps, iff the driver allows it.
And allow_draw_out_of_order=false can still be used in drirc, for
apps that need this optim to be turned off.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16139>
Pierre-Eric Pelloux-Prayer [Mon, 25 Apr 2022 11:41:49 +0000 (13:41 +0200)]
drirc: remove i965 entry
The driver has been deleted in !10153.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16139>
Pierre-Eric Pelloux-Prayer [Wed, 16 Mar 2022 09:40:00 +0000 (10:40 +0100)]
radeonsi: drop assume_no_z_fights option
And garbage collect the code that was only used by this option.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16139>
Pierre-Eric Pelloux-Prayer [Wed, 16 Mar 2022 09:36:38 +0000 (10:36 +0100)]
radeonsi: remove commutative_blend_add option
This is unused.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16139>
Samuel Pitoiset [Fri, 29 Apr 2022 07:13:21 +0000 (09:13 +0200)]
radv/ci: update list of expected failures for Bonaire (GFX7)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16237>
Erik Faye-Lund [Thu, 21 Apr 2022 11:08:09 +0000 (13:08 +0200)]
microsoft/compiler: fixup indentation
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16079>
Erik Faye-Lund [Thu, 21 Apr 2022 11:07:08 +0000 (13:07 +0200)]
microsoft/clc: fixup indentation
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16079>
M Henning [Sat, 2 Apr 2022 04:16:55 +0000 (00:16 -0400)]
ttn: Make ttn_optimize_nir match gl_nir_opts
ttn_optimize_nir was copied from gl code in
9a834447d6, so update it
to include all of the lowering steps that gl does. nouveau needs
some of these passes to be applied.
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16158>
Dave Airlie [Sun, 13 Mar 2022 19:54:20 +0000 (05:54 +1000)]
vulkan/wsi: keep allocate queue families in image, just don't fill them
This changes the code so that it only looks at the passed in families
when concurrent, otherwise it always allocates one.
Fixes:
48b3ef625e19 ("vulkan/wsi: handle queue families properly for non-concurrent sharing mode.")
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15331>
Renato Pereyra [Thu, 28 Apr 2022 21:36:42 +0000 (14:36 -0700)]
venus: add support for vk_xwayland_wait_ready
Signed-off-by: Renato Pereyra <renatopereyra@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16229>
Mike Blumenkrantz [Thu, 28 Apr 2022 20:50:56 +0000 (16:50 -0400)]
zink: remove drm_fd
no longer used
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16226>
Mike Blumenkrantz [Thu, 28 Apr 2022 20:31:16 +0000 (16:31 -0400)]
zink: ignore KMS handle types
who could've guessed that such a thing was possible
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16226>
Mike Blumenkrantz [Thu, 28 Apr 2022 20:30:43 +0000 (16:30 -0400)]
zink: export fd info for all 2d images
there's no way to add this later, so here we go
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16226>
Mike Blumenkrantz [Thu, 28 Apr 2022 19:50:40 +0000 (15:50 -0400)]
zink: fix dmabuf plane returns
use the actual drm format plane count, not the resource format
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16226>
Karol Herbst [Thu, 14 Apr 2022 17:14:10 +0000 (19:14 +0200)]
vtn: clamp SpvOpImageQuerySize dest to 32 bit
CL image arrays slice is 64 bit for whatever reason...
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16205>
Jason Ekstrand [Wed, 30 Mar 2022 15:57:19 +0000 (10:57 -0500)]
nir/deref: Add an alu-of-cast optimization
Casts shouldn't change the bit pattern of the deref and you have to cast
again after you're done with the ALU anyway so we can ignore casts on
ALU sources. This means we can actually start constant folding NULL
checks even if there are annoying casts in the way.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15673>
Dave Airlie [Wed, 23 Mar 2022 03:12:38 +0000 (13:12 +1000)]
gallium/vl: respect the video codecs configure in meson
Acked-by: Christian König <christian.koenig@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15258>
Dave Airlie [Mon, 7 Mar 2022 02:37:29 +0000 (12:37 +1000)]
meson: add a video codec support option
This allows to turn on/off all hw implementations for a specific video
codec across the tree. Patent encumbered codecs can cause problems for
distributions due to the nature of at least MPEG-LA licensing.
https://jina-liu.medium.com/settle-your-questions-about-h-264-license-cost-once-and-for-all-hopefully-
a058c2149256
is probably the best explaination I can find.
From a distro pov, codecs are a jigsaw puzzle, you only seem to become a problem well you fit all the pieces.
This patch will allow disabling the mesa piece of the puzzle.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15258>
Dave Airlie [Wed, 23 Mar 2022 03:11:42 +0000 (13:11 +1000)]
gallium/omx: add video codec supported hook for decode paths.
These never asked the driver for what was supported.
Acked-by: Christian König <christian.koenig@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15258>
Dave Airlie [Wed, 23 Mar 2022 03:05:58 +0000 (13:05 +1000)]
gallium/vl: wrap codec support checks in a common function.
This just is an initial wrapping of all calls into the driver
to check for codec support.
The idea is to add more to this function to support the meson
level disables.
Acked-by: Christian König <christian.koenig@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15258>
Jordan Justen [Tue, 11 Jan 2022 22:14:01 +0000 (14:14 -0800)]
intel_dev_info: Add --hwconfig command line parameter
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14511>
Jordan Justen [Sat, 30 Oct 2021 20:41:38 +0000 (13:41 -0700)]
intel/dev: Read hwconfig from i915
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14511>
Emma Anholt [Tue, 26 Apr 2022 00:02:20 +0000 (17:02 -0700)]
nir_to_tgsi: Drop the txl(lod=0)->tex nir_lower_tex() fixup.
I've fixed nir_lower_tex() to not do that for us any more.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16156>
Emma Anholt [Mon, 25 Apr 2022 23:55:45 +0000 (16:55 -0700)]
nir/lower_tex: Make the adding a 0 LOD to nir_op_tex in the VS optional.
This controls the whole lowering of "make tex ops with implicit
derivatives on non-implicit-derivative stages be tex ops with an explicit
lod of 0 instead", but it's really hard to describe that in a git commit
summary.
All existing callers get it added except:
- nir_to_tgsi which didn't want it.
- nouveau, which didn't want it (fixes regressions in shadowcube and
shadow2darray with NIR, since the shading languages don't expose txl of
those sampler types and thus it's not supported in HW)
- optional lowering passes in mesa/st (lower_rect, YUV lowering, etc)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16156>
Yiwei Zhang [Thu, 28 Apr 2022 17:57:38 +0000 (17:57 +0000)]
venus: disable VK_EXT_extended_dynamic_state2
extended_dynamic_state.*_raster tests timeout because the new
VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE is not handled in venus.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16222>
Nanley Chery [Thu, 29 Apr 2021 19:04:04 +0000 (12:04 -0700)]
isl,iris: Add DG2 CCS modifier support for XeHP
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
Nanley Chery [Wed, 29 Sep 2021 22:59:21 +0000 (15:59 -0700)]
intel/isl: Add a score for I915_FORMAT_MOD_4_TILED
Enables the modifier in anv.
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
Anuj Phogat [Mon, 13 Jan 2020 20:51:55 +0000 (12:51 -0800)]
isl,iris: Add I915_FORMAT_MOD_4_TILED support for XeHP
This patch adds Tile 4 modifier support to Mesa and allows Mesa to
use Tile 4 on gen12-hp with GBM.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
Anuj Phogat [Thu, 11 Mar 2021 23:32:53 +0000 (15:32 -0800)]
include/uapi: Update drm_fourcc.h from kernel
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
v2. Pull in the header from drm-next at commit
9035039e1ed691cd893777a42e048003a2f349d6
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
Nanley Chery [Thu, 28 Apr 2022 15:01:19 +0000 (08:01 -0700)]
iris: Return a 64B stride for clear color plane
Although modifiers which use a clear color plane specify that the
plane's pitch should be ignored, some kernels have been found to require
64-byte alignment.
Cc: mesa-stable
Fixes:
db475c81b7c ("iris: Return non-zero stride for clear color plane")
Reported-by: Dongwon Kim <dongwon.kim@intel.com>
Suggested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>