Samuel Pitoiset [Wed, 2 Dec 2015 21:05:17 +0000 (22:05 +0100)]
nv50/ir/gk110: add memory barriers support for GK110
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 29 Nov 2015 14:50:09 +0000 (15:50 +0100)]
nv50/ir: do not call textureMask() for surface ops
That texture mask thing doesn't seem to be needed for surface ops, so
just as nve4+, let do that only for texture ops.
This fixes a segfault with 'test_surface_st' from
gallium/tests/trivial/compute.c on Fermi because this test uses sustp.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jose Fonseca [Thu, 26 Nov 2015 10:39:41 +0000 (10:39 +0000)]
appveyor: Initial integration.
AppVeyor doesn't require an appveyor.yml in the repos (in fact it has
some limitations as noted in comments below), but doing so has two great
advantages over the web UI:
- appveyor.yml can be revisioned together with the code, so instructions
should always be in synch with the code
- appveyor.yml can be reused for people's private repositories (be on
fdo or GitHub, etc.)
Acked-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Wed, 2 Dec 2015 17:48:29 +0000 (17:48 +0000)]
util/blitter: Fix "SO C90 forbids mixed declarations and code".
Trivial.
Brian Paul [Tue, 1 Dec 2015 21:35:14 +0000 (14:35 -0700)]
mesa: print enum string in compressed_subtexture_error_check() error msg
Trivial.
Edward O'Callaghan [Thu, 26 Nov 2015 05:55:01 +0000 (16:55 +1100)]
gallium/util: Fix util_blitter_clear_depth_stencil() for num_layers>1
Previously util_blitter_clear_depth_stencil() could not clear more
than the first layer. We need to generalise this as we did for
util_blitter_clear_render_target().
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Thu, 26 Nov 2015 05:55:00 +0000 (16:55 +1100)]
gallium/util: Fix util_blitter_clear_render_target() for num_layers>1
Previously util_blitter_clear_render_target() could not clear more
than the first layer. We need to generalise this so that
ARB_clear_texture can pass the 3d piglit test.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Roland Scheidegger [Tue, 1 Dec 2015 19:06:59 +0000 (20:06 +0100)]
mesa: fix VIEWPORT_INDEX_PROVOKING_VERTEX and LAYER_PROVOKING_VERTEX queries
These are implementation-dependent queries, but so far we just returned the
value of whatever the current provoking vertex convention was set to, which
was clearly wrong.
Just make this a variable in the context constants like for other things
which are implementation dependent (I assume all drivers will want to set
this to the same value for both queries), and set it to GL_UNDEFINED_VERTEX
which is correct for everybody (and drivers can override it).
Reviewed-by: Brian Paul <brianp@vmware.com>
CC: <mesa-stable@lists.freedesktop.org>
Jose Fonseca [Tue, 1 Dec 2015 23:07:08 +0000 (23:07 +0000)]
Remove Sun CC specific code.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Jose Fonseca [Tue, 1 Dec 2015 22:43:46 +0000 (22:43 +0000)]
configure.ac: Refuse to build with Sun C compiler.
https://bugs.freedesktop.org/show_bug.cgi?id=93189
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Eric Anholt [Tue, 1 Dec 2015 19:57:49 +0000 (11:57 -0800)]
travis: Add a test build with scons.
Since I just broke the scons build, I figured I'd make Travis test that I
don't break it again in the future. The script runs the builds in
parallel across VMs, so it still takes just 5 minutes to turn around
results.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Kenneth Graunke [Mon, 30 Nov 2015 09:54:42 +0000 (01:54 -0800)]
i965: Increase BRW_MAX_UBO to 14.
The NVIDIA binary driver and Intel's closed source driver both expose
14 here, rather than the GL minimum of 12. Let's follow suit.
Without this, Shadow of Mordor fails to render correctly and triggers
OpenGL errors:
Mesa: User error: GL_INVALID_VALUE in glBindBufferBase(index=68)
Mesa: User error: GL_INVALID_VALUE in glUniformBlockBinding(block binding 68 >= 60)
There are 5 stages (VS, TCS, TES, GS, FS), and 12 * 5 = 60 is too small.
14 * 5 = 70 will work just fine.
Tapani believes this will also help Alien Isolation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Mon, 30 Nov 2015 17:25:19 +0000 (09:25 -0800)]
i965: Do dead-code elimination in a single pass.
The first pass marked dead instructions as opcode = NOP, and a second
pass deleted those instructions so that the live ranges used in the
first pass wouldn't change.
But since we're walking the instructions in reverse order, we can just
do everything in one pass. The only thing we have to do is walk the
blocks in reverse as well.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Mon, 30 Nov 2015 17:24:23 +0000 (09:24 -0800)]
glsl: Rename safe_reverse -> reverse_safe.
To match existing foreach_in_list_reverse_safe.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Thu, 26 Nov 2015 00:19:06 +0000 (16:19 -0800)]
i965: Don't mark dead instructions' sources live.
Removes dead code from glsl-mat-from-int-ctor-03.shader_test.
Reported-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Dave Airlie [Tue, 24 Feb 2015 06:07:23 +0000 (16:07 +1000)]
r600: set mega fetch count to 16 for gs copy shader
Seems like MFC should be set for this shader.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 24 Feb 2015 05:58:33 +0000 (15:58 +1000)]
r600: increment ring index after emit vertex not before.
The docs say we should send the emit after the ring writes,
so lets do that and not have an ALU in between.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 24 Feb 2015 05:57:49 +0000 (15:57 +1000)]
r600: add alu + cf nop to copy shader on r600
SB suggests we do this for r600, so lets do it,
for the copy shader.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 24 Feb 2015 04:10:20 +0000 (14:10 +1000)]
r600: SMX returns CONTEXT_DONE early workaround
streamout, gs rings bug on certain r600s, requires a wait idle
before each surface sync.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 23 Feb 2015 20:14:31 +0000 (20:14 +0000)]
r600: do SQ flush ES ring rolling workaround
Need to insert a SQ_NON_EVENT when ever geometry
shaders are enabled.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Samuel Pitoiset [Tue, 1 Dec 2015 21:40:45 +0000 (22:40 +0100)]
nv50,nvc0: allow to create resources other than buffers
For the compute support, we might stick buffers as surfaces. This fixes
an assertion when executing src/gallium/tests/trivial/compute.
To avoid using these "restricted" surfaces as render targets, these
assertions have been moved. Note that it's already handled for the
framebuffer thing on nvc0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Brian Paul [Tue, 1 Dec 2015 20:02:05 +0000 (13:02 -0700)]
glapi: work-around MSVC 65K string length limitation for enums.c
String literals cannot exceed 65535 characters for MSVC. Instead of
emiting a string, emit an array of characters.
v2: fix indentation and add comment in the gl_enums.py file about this
ugliness.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Tue, 1 Dec 2015 20:01:53 +0000 (12:01 -0800)]
mapi: Fix enums.c build with other build systems.
Tested with scons (by both myself and Mark Janes), Android is just copy
and paste.
Eric Anholt [Tue, 24 Nov 2015 00:25:29 +0000 (16:25 -0800)]
travis: Initial import of travis instructions.
This just builds/installs our dependencies, and runs "make check". I'm
interested in integrating more tests into it, but this seems like a pretty
easy first start.
If your personal branches of Mesa are on github, you can enable it on your
account and the repository (see
https://docs.travis-ci.com/user/for-beginners), then any pushes you do
will get their HEAD commit tested, and any pull requests to your tree will
get their merge commits tested.
Eric Anholt [Sat, 19 Sep 2015 16:35:15 +0000 (12:35 -0400)]
mesa: Drop the blacklisting of new GL enums.
Now when people need new extensions, they can skip the entire
enum-definition process, and we can stop reviewing new extension XML for
its enum content.
This also brings in a new enum that I wanted to use in enum_strings.cpp
for testing the code generator.
v2: Drop comment about disabled GL_1PASS_EXT test.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Sat, 19 Sep 2015 16:57:22 +0000 (12:57 -0400)]
mesa: Use a 32-bit offset for the enums.c string offset table.
With GLES 3.1, GL 4.5, and many new vendor extensions about to get their
enums added, we jump up to 85k of table.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Thu, 26 Nov 2015 01:04:21 +0000 (17:04 -0800)]
mesa: Prefer newer names to older ones among names present in core.
Sometimes GL likes to rename an old enum when it grows a more general
purpose, and we should prefer the new name. Changes from this:
GL_POINT/LINE_SIZE_* (1.1) -> GL_SMOOTH_POINT/LINE_SIZE_* (1.2)
GL_FOG_COORDINATE_* (1.4) -> GL_FOG_COORD_* (1.5)
GL_SOURCE[012]_RGB/ALPHA (1.3) -> GL_SRC0_RGB (1.5)
GL_COPY_READ/WRITE_BUFFER (3.1) -> GL_COPY_READ_BUFFER_BINDING (4.2)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Thu, 26 Nov 2015 01:00:00 +0000 (17:00 -0800)]
mesa: Drop bitfield "enums" from the enum-to-string table.
Asking the table for bitfield names doesn't make any sense. For 0x10, do
you want GL_GLYPH_HORIZONTAL_BEARING_ADVANCE_BIT_NV or
GL_COLOR_BUFFER_BIT4_QCOM or GL_POLYGON_STIPPLE_BIT or
GL_SHADER_GLOBAL_ACCESS_BARRIER_BIT_NV? Giving a useful answer would
depend on a whole lot of context.
This also fixes a bad enum table entry, where we chose GL_HINT_BIT instead
of GL_ABGR_EXT for 0x8000, so we can now fix its entry in the enum_strings
test.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Thu, 17 Sep 2015 23:10:28 +0000 (19:10 -0400)]
mesa: Switch to using the Khronos registry for generating enums.
I've used a bunch of python code to cut out new enums so that the two
generated files can be diffed. I'll remove all that hardcoding in the
following commits. All remaining differences between the generated code:
- GL_TEXTURE_BUFFER_FORMAT didn't appear in GL3 when TBOs got merged to
core, so it now gets an _ARB suffix instead.
- Blacklisting can't keep EXT_sso's GL_ACTIVE_PROGRAM_EXT from becoming
GL_ACTIVE_PROGRAM -- in our hash table, GL_ACTIVE_PROGRAM_EXT points at
the GLES2 enum's value (aka GL_CURRENT_PROGRAM). By not blacklisting
the core name, we get both enums translated.
- GL_DRAW_FRAMEBUFFER_BINDING and GL_FRAMEBUFFER_BINDING both appeared in
GL3 as synonyms, and the new code happens to choose
GL_FRAMEBUFFER_BINDING instead.
- GL_TEXTURE_COMPONENTS and GL_TEXTURE_INTERNAL_FORMAT both appear in 1.1,
and the new code chooses GL_TEXTURE_INTERNAL_FORMAT instead (which seems
better, to me)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Wed, 25 Nov 2015 23:38:55 +0000 (15:38 -0800)]
mesa: Remove the python mode bits from gl_enums.py.
emacs whines at me every time I open the file about these unsafe
variables, and the file was reformatted from 8 space to 4 space long ago.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Thu, 26 Nov 2015 00:29:10 +0000 (16:29 -0800)]
mesa: Drop apparently typoed GL_ALL_CLIENT_ATTRIB_BITS.
GL_ALL_ATTRIB_BITS is a thing, and GL_CLIENT_ALL_ATTRIB_BITS, but I don't
see GL_ALL_CLIENT_ATTRIB_BITS in my grepping of khronos XML, GL extension
specs, GL 1.1, GL 2.2, and GL 4.4.
Reviewed-by: Brian Paul <brianp@vmware.com>
Eric Anholt [Sat, 19 Sep 2015 15:28:46 +0000 (11:28 -0400)]
mesa: Drop enums that had been removed in later revs of specs.
Mesa hasn't been using these enums and the finalized specs don't reference
them, so losing them from our generated enum-to-string code should be
fine. Reduces diffs to generating from Khronos XML, which has these enums
noted defined but commented out from any consumers.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Fri, 18 Sep 2015 19:02:07 +0000 (15:02 -0400)]
mesa: Fix a typo in AMD_performance_monitor enum.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Fri, 18 Sep 2015 18:55:41 +0000 (14:55 -0400)]
mesa: Fix enum definition of CULL_VERTEX_EYE/OBJECT_POSITION
In converting to using the Khronos XML, I found that our XML had these two
swapped, and the text spec agreed.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Thu, 17 Sep 2015 21:39:52 +0000 (17:39 -0400)]
mesa: Add a copy of the Khronos gl.xml (SVN #31705).
The intention here is to keep a pristine copy of the upstream gl.xml that
can be updated at any time with a new version, and use that to generate
Mesa code from instead of our private XML.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Wed, 25 Nov 2015 06:11:41 +0000 (22:11 -0800)]
mesa: Cut enum_strings.cpp test down to a few hand-chosen enums.
The previous contents appeared to be the output of some form of code
generation for all enums, with a few entries hand-edited to deal with
oddness. The downside to this was that when an enum gets promoted from
vendor to _EXT or _EXT to _ARB or _ARB to core, make check starts failing
even when the commiter has done nothing wrong. Instead of black-box
testing the code generation, pick a few enums that intentionally poke the
interesting cases of code generation.
People editing the code generator should be diffing the generated code
anyway. This should catch when they fail to do so, without throwing false
negatives when people update the GL XML.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tom Stellard [Sat, 28 Nov 2015 02:40:24 +0000 (02:40 +0000)]
clover: Handle NULL devices returned by pipe_loader_probe() v2
When probing for devices, clover will call pipe_loader_probe() twice.
The first time to retrieve the number of devices, and then second time
to retrieve the device structures.
We currently assume that the return value of both calls will be the
same, but this will not be the case if a device happens to disappear
between the two calls.
When a device disappears, the pipe_loader_probe() will add a NULL
device to the device list, so we need to handle this.
v2:
- Keep range for loop
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Jonathan Gray [Mon, 23 Nov 2015 03:22:24 +0000 (14:22 +1100)]
automake: fix some occurrences of hardcoded -ldl and -lpthread
Correct some occurrences of -ldl and -lpthread to use
$(DLOPEN_LIBS) and $(PTHREAD_LIBS) respectively.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Iago Toral Quiroga [Mon, 23 Nov 2015 12:53:09 +0000 (13:53 +0100)]
glsl/lower_ubo_reference: split struct copies into element copies
Improves register pressure, since otherwise we end up emitting
loads for all the elements in the RHS and them emitting
stores for all elements in the LHS.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Mon, 23 Nov 2015 12:53:08 +0000 (13:53 +0100)]
glsl/lower_ubo_reference: split array copies into element copies
Improves register pressure, since otherwise we end up emitting
loads for all the elements in the RHS and them emitting
stores for all elements in the LHS.
v2:
- Mark progress properly. This also fixes some instances where the added
nodes with individual element copies where not being lowered, which is
expected behavior as explained in the documentation for
visit_list_elements.
- Only need to do this if the RHS is a buffer-backed variable.
- We can also have arrays inside structs. A later patch will make it so
we also split struct copies and end up with multiple
ir_dereference_record assignments, so make sure that if any of these
is an array copy, we also split it.
Fixes the following piglit tests:
tests/spec/arb_shader_storage_buffer_object/execution/large-field-copy.shader_test
tests/spec/arb_shader_storage_buffer_object/linker/copy-large-array.shader_test
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Julien Isorce [Thu, 26 Nov 2015 08:30:30 +0000 (08:30 +0000)]
st/va: also retrieve reference frames info for h264
Other hardwares than AMD require to parse:
VAPictureParameterBufferH264.ReferenceFrames[16]
Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Julien Isorce [Thu, 26 Nov 2015 08:29:54 +0000 (08:29 +0000)]
st/va: delay decoder creation until max_references is known
In general max_references cannot be based on num_render_targets.
This patch allows to allocate buffers with an accurate size.
I.e. no more than necessary. For other codecs it is a fixed
value 2.
This is similar behaviour as vaapi/vdpau-driver.
For now HEVC case defaults to num_render_targets as before.
But it could also benefits this change by setting a more
accurate max_references number in handlePictureParameterBuffer.
Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Iago Toral Quiroga [Fri, 27 Nov 2015 11:46:20 +0000 (12:46 +0100)]
glsl/dead_builin_varyings: Fix gl_FragData array lowering
The current implementation looks for array dereferences on gl_FragData and
immediately proceeds to lower them, however this is not enough because we
can have array access on vector variables too, like in this code:
out vec4 color;
void main()
{
int i;
for (i = 0; i < 4; i++)
color[i] = 1.0;
}
Fix it by making sure that the actual variable being dereferenced is an array.
Fixes a crash in:
spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-ldexp-dvec4.shader_test
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Dave Airlie [Tue, 24 Feb 2015 04:09:40 +0000 (14:09 +1000)]
r600: workaround empty geom shader.
We need to emit at least one cut/emit in every
geometry shader, the easiest workaround it to
stick a single CUT at the top of each geom shader.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 24 Feb 2015 06:30:05 +0000 (16:30 +1000)]
r600: rv670 use at least 16es/gs threads
This is specified in the docs for rv670 to work properly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 18 Feb 2015 23:51:19 +0000 (23:51 +0000)]
r600: geometry shader gsvs itemsize workaround
On some chips the GSVS itemsize needs to be aligned to a cacheline size.
This only applies to some of the r600 family chips.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Gregory Hainaut [Sun, 25 Oct 2015 14:01:37 +0000 (15:01 +0100)]
glsl: don't sort varying in separate shader mode
This fixes an issue where the addition of the FLAT qualifier in
varying_matches::record() can break the expected varying order.
It also avoids a future issue with the relaxing of interpolation
qualifier matching constraints in GLSL 4.50.
V2: (by Timothy Arceri)
* reworked comment slightly
Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Gregory Hainaut [Sun, 25 Oct 2015 14:01:35 +0000 (15:01 +0100)]
glsl: don't dead code remove SSO varyings marked as active
GL_ARB_separate_shader_objects allow matching by name variable or block
interface. Input varyings can't be removed because it is will impact the
location assignment.
This fixes the bug 79783 and likely any application that uses
GL_ARB_separate_shader_objects extension.
V2 (by Timothy Arceri):
* simplify now that builtins are not set as always active
Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
https://bugs.freedesktop.org/show_bug.cgi?id=79783
Gregory Hainaut [Sun, 25 Oct 2015 14:01:34 +0000 (15:01 +0100)]
glsl: add always_active_io attribute to ir_variable
The value will be set in separate-shader program when an input/output
must remains active. e.g. when deadcode removal isn't allowed because
it will create interface location/name-matching mismatch.
v3:
* Rename the attribute
* Use ir_variable directly instead of ir_variable_refcount_visitor
* Move the foreach IR code in the linker file
v4:
* Fix variable name in assert
v5 (by Timothy Arceri):
* Rename functions and reword comments
* Don't set always active on builtins
Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Timothy Arceri [Sat, 21 Nov 2015 00:08:36 +0000 (11:08 +1100)]
glsl: copy how_declared when lowering interface blocks
Cc: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Timothy Arceri [Sat, 21 Nov 2015 01:47:25 +0000 (12:47 +1100)]
glsl: optimise inputs/outputs with explicit locations
This change allows used defined inputs/outputs with explicit locations
to be removed if they are detected to not be used between shaders
at link time.
To enable this we change the is_unmatched_generic_inout field to be
flagged when we have a user defined varying. Previously
explicit_location was assumed to be set only in builtins however SSO
allows the user to set an explicit location.
We then add a function to match explicit locations between shaders.
V2: call match_explicit_outputs_to_inputs() after
is_unmatched_generic_inout has been initialised.
Cc: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Dave Airlie [Mon, 30 Nov 2015 04:23:00 +0000 (14:23 +1000)]
r600/shader: split address get out to a function.
This will be used in the tess shaders.
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Marta Lofstedt [Fri, 27 Nov 2015 14:31:10 +0000 (15:31 +0100)]
doc: Set GL_OES_geometry_shader as started
Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Marta Lofstedt [Fri, 27 Nov 2015 14:31:05 +0000 (15:31 +0100)]
gles2: Update gl2ext.h to revision: 32120
This is needed to be able to implement the accepted OES
extensions.
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Julien Isorce [Fri, 27 Nov 2015 08:55:55 +0000 (08:55 +0000)]
vl/buffers: fixes vl_video_buffer_formats for RGBX
Fixes:
42a5e143a8d "vl/buffers: add RGBX and BGRX to the supported formats"
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Samuel Iglesias Gonsálvez [Mon, 30 Nov 2015 08:28:42 +0000 (09:28 +0100)]
i965/fs: remove unused fs_reg offset
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Kenneth Graunke [Fri, 20 Nov 2015 00:00:18 +0000 (16:00 -0800)]
i965: Add src/dst interference for certain instructions with hazards.
When working on tessellation shaders, I created some vec4 virtual
opcodes for creating message headers through a sequence like:
mov(8) g7<1>UD 0x00000000UD { align1 WE_all 1Q compacted };
mov(1) g7.5<1>UD 0x00000100UD { align1 WE_all };
mov(1) g7<1>UD g0<0,1,0>UD { align1 WE_all compacted };
mov(1) g7.3<1>UD g8<0,1,0>UD { align1 WE_all };
This is done in the generator since the vec4 backend can't handle align1
regioning. From the visitor's point of view, this is a single opcode:
hs_set_output_urb_offsets vgrf7.0:UD, 1U, vgrf8.xxxx:UD
Normally, there's no hazard between sources and destinations - an
instruction (naturally) reads its sources, then writes the result to the
destination. However, when the virtual instruction generates multiple
hardware instructions, we can get into trouble.
In the above example, if the register allocator assigned vgrf7 and vgrf8
to the same hardware register, then we'd clobber the source with 0 in
the first instruction, and read back the wrong value in the last one.
It occured to me that this is exactly the same problem we have with
SIMD16 instructions that use W/UW or B/UB types with 0 stride. The
hardware implicitly decodes them as two SIMD8 instructions, and with
the overlapping regions, the first would clobber the second.
Previously, we handled that by incrementing the live range end IP by 1,
which works, but is excessive: the next instruction doesn't actually
care about that. It might also be the end of control flow. This might
keep values alive too long. What we really want is to say "my source
and destinations interfere".
This patch creates new infrastructure for doing just that, and teaches
the register allocator to add interference when there's a hazard. For
my vec4 case, we can determine this by switching on opcodes. For the
SIMD16 case, we just move the existing code there.
I audited our existing virtual opcodes that generate multiple
instructions; I believe FS_OPCODE_PACK_HALF_2x16_SPLIT needs this
treatment as well, but no others.
v2: Rebased by mattst88.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 18 Nov 2015 02:24:11 +0000 (18:24 -0800)]
i965: Fix JIP to properly skip over unrelated control flow.
We've apparently always been botching JIP for sequences such as:
do
cmp.f0.0 ...
(+f0.0) break
...
if
...
else
...
endif
...
while
Normally, UIP is supposed to point to the final destination of the jump,
while in nested control flow, JIP is supposed to point to the end of the
current nesting level. It essentially bounces out of the current nested
control flow, to an instruction that has a JIP which bounces out another
level, and so on.
In the above example, when setting JIP for the BREAK, we call
brw_find_next_block_end(), which begins a search after the BREAK for the
next ENDIF, ELSE, WHILE, or HALT. It ignores the IF and finds the ELSE,
setting JIP there.
This makes no sense at all. The break is supposed to skip over the
whole if/else/endif block entirely. They have a sibling relationship,
not a nesting relationship.
This patch fixes brw_find_next_block_end() to track depth as it does
its search, and ignore anything not at depth 0. So when it sees the
IF, it ignores everything until after the ENDIF. That way, it finds
the end of the right block.
I noticed this while reading some assembly code. We believe jumping
earlier is harmless, but makes the EU walk through a bunch of disabled
instructions for no reason. I noticed that GLBenchmark Manhattan had
a shader that contained a BREAK with a bogus JIP, but didn't measure
any performance improvement (it's likely miniscule, if there is any).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Dave Airlie [Mon, 30 Nov 2015 00:37:21 +0000 (10:37 +1000)]
r600: move per-type settings into a switch statement
This will allow adding tess stuff much cleaner later.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:17:34 +0000 (10:17 +1000)]
r600: split out common alu_writes pattern.
This just splits out a common pattern into an inline function
to make things cleaner to read.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:05:42 +0000 (11:05 +1000)]
r600/llvm: fix r600/llvm build
Reported on irc by gryffus
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 29 Nov 2015 23:35:37 +0000 (09:35 +1000)]
r600: fixes for register definitions.
Forgot to add these.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 23 Nov 2015 22:44:13 +0000 (08:44 +1000)]
r600: add missing register to initial state
We really should initialise HS/LS_2 and SQ_LDS_ALLOC exists
on all evergreen not just cayman, so we should initialise
it as well.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 23 Nov 2015 22:39:25 +0000 (08:39 +1000)]
r600: define registers required for tessellation
This adds the defines for a bunch of registers and shader
values that are required to implement tessellation.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 23 Nov 2015 20:48:20 +0000 (06:48 +1000)]
r600: consolidate clip state updates
Move some common code into one place, tess will also need
to use this function.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Samuel Pitoiset [Sun, 29 Nov 2015 15:04:11 +0000 (16:04 +0100)]
nv50/ir: always display the opcode number for unknown instructions
This helps in debugging unknown instructions.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Emil Velikov [Fri, 27 Nov 2015 13:12:59 +0000 (13:12 +0000)]
mesa: remove len argument from _mesa_shader_debug()
There was only a single user which was using strlen(buf).
As this function is not user facing (i.e. we don't need to feed back
original length via a callback), we can simplify things.
Suggested-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Emil Velikov [Wed, 25 Nov 2015 21:31:57 +0000 (21:31 +0000)]
drivers/x11: scons: partially revert
b9b40ef9b76
As glsl_types.{cpp,h} were moved out of the sconscript (commit
b23a4859f4d "scons: Build nir/glsl_types.cpp once.") remove the dangling
includes.
Cc: Jose Fonseca <jfonseca@vmware.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Emil Velikov [Wed, 25 Nov 2015 21:31:56 +0000 (21:31 +0000)]
nir: remove recursive inclusion in builtin_type_macros.h
The header is already included by glsl_types.{cpp,h}.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Wed, 25 Nov 2015 21:31:55 +0000 (21:31 +0000)]
nir: remove unneeded include
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Emil Velikov [Wed, 25 Nov 2015 20:17:06 +0000 (20:17 +0000)]
mesa/program: remove dead function declarations
Dead since
5e9aa9926b9 (2011) - _mesa_ir_compile_shader
69e07bdeb42 (2009) - _mesa_get_program_register
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Mon, 23 Nov 2015 20:26:59 +0000 (20:26 +0000)]
auxiliary/vl/dri: fd management cleanups
Analogous to previous commit, minus the extra dup. We are the one
opening the device thus we can directly use the fd.
Spotted by Coverity (CID 1339867, 1339877)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Mon, 23 Nov 2015 20:26:58 +0000 (20:26 +0000)]
auxiliary/vl/drm: fd management cleanups
Analogous to previous commit.
Spotted by Coverity (CID 1339868)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Mon, 23 Nov 2015 20:26:57 +0000 (20:26 +0000)]
st/xa: fd management cleanups
Analogous to previous commit.
Spotted by Coverity (CID 1339866)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Mon, 23 Nov 2015 20:26:56 +0000 (20:26 +0000)]
st/dri: fd management cleanups
Add some checks if the original/dup'd fd is valid and ensure that we
don't leak it on error. The former is implicitly handled within the
pipe_loader, although let's make things explicit and check beforehand.
Spotted by Coverity (CID 1339865)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Mon, 23 Nov 2015 20:26:55 +0000 (20:26 +0000)]
pipe-loader: check if winsys.name is non-null prior to strcmp
In theory this wouldn't be an issue, as we'll find the correct name and
break out of the loop before we hit the sentinel.
Let's fix this and avoid issues in the future.
Spotted by Coverity (CID 1339869, 1339870, 1339871)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Sun, 29 Nov 2015 11:48:26 +0000 (11:48 +0000)]
st/va: add missing break statement
Earlier commit factored out the mpeg4 IQ matrix handling into separate
function, although it forgot to add a break in its case statement.
Thus the data ended up partially overwritten as the mpeg4 and h265
structs are members of the desc union.
Spotted by Coverity (CID 1341052)
Fixes:
64761a841db "st/va: move MPEG4 functions into separate file"
Cc: Julien Isorce <j.isorce@samsung.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Ilia Mirkin [Thu, 26 Nov 2015 15:32:57 +0000 (10:32 -0500)]
mesa: support GL_RED/GL_RG in ES2 contexts when driver support exists
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93126
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Nicolai Hähnle [Fri, 27 Nov 2015 23:02:26 +0000 (00:02 +0100)]
radeon: only suspend queries on flush if they haven't been suspended yet
Non-timer queries are suspended during blits. When the blits end, the queries
are resumed, but this resume operation itself might run out of CS space and
trigger a flush. When this happens, we must prevent a duplicate suspend during
preflush suspend, and we must also prevent a duplicate resume when the CS flush
returns back to the original resume operation.
This fixes a regression that was introduced by:
commit
8a125afa6e88a3eeddba8c7fdc1a75c9b99d5489
Author: Nicolai Hähnle <nhaehnle@gmail.com>
Date: Wed Nov 18 18:40:22 2015 +0100
radeon: ensure that timing/profiling queries are suspended on flush
The queries_suspended_for_flush flag is redundant because suspended queries
are not removed from their respective linked list.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reported-by: Axel Davy <axel.davy@ens.fr>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Tested-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jose Fonseca [Thu, 26 Nov 2015 15:06:35 +0000 (15:06 +0000)]
scons: Use LD version script for libgl-xlib.
Trivial.
Jose Fonseca [Wed, 25 Nov 2015 13:34:18 +0000 (13:34 +0000)]
svga: Don't return value from void function.
Addresses MSVC warning C4098: 'svga_destroy_query' : 'void' function
returning a value.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Wed, 25 Nov 2015 13:33:08 +0000 (13:33 +0000)]
gallium: Make pipe_query_result::batch array length non-zero.
Zero length arrays are non standard:
warning C4200: nonstandard extension used : zero-sized array in struct/union
Cannot generate copy-ctor or copy-assignment operator when UDT contains a zero-sized array
And all code does `N * sizeof query_result->batch[0]`, so it should work
exactly the same.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Neil Roberts [Thu, 26 Nov 2015 16:53:42 +0000 (17:53 +0100)]
util: Tiny optimisation for the linear→srgb conversion
When converting 0.0 it would be nice if it didn't do any arithmetic.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Thu, 26 Nov 2015 20:57:40 +0000 (21:57 +0100)]
docs: Update GL3.txt to add ARB_internalformat_query2
Added to OpenGL 4.3 section, tagged as 'in progress (elima)'. See
https://bugs.freedesktop.org/show_bug.cgi?id=92687.
Thanks to Thomas H.P. Andersen for remainding me about this.
v1: - Update the already existing entry in section 4.3
instead (Ilia Mirkin).
- Added my BZ nickname as contact person (Felix Schwarz).
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Timothy Arceri [Thu, 26 Nov 2015 10:32:48 +0000 (21:32 +1100)]
glsl: don't generate extra errors in ValidateProgramPipeline
From Section 11.1.3.11 (Validation) of the GLES 3.1 spec:
"An INVALID_OPERATION error is generated by any command that trans-
fers vertices to the GL or launches compute work if the current set
of active program objects cannot be executed, for reasons including:"
It then goes on to list the rules we validate in the
_mesa_validate_program_pipeline() function.
For ValidateProgramPipeline the only mention of generating an error is:
"An INVALID_OPERATION error is generated if pipeline is not a name re-
turned from a previous call to GenProgramPipelines or if such a name has
since been deleted by DeleteProgramPipelines,"
Which we handle separately.
This fixes:
ES31-CTS.sepshaderobjs.PipelineApi
No regressions on the eEQP 3.1 tests.
Cc: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Rob Clark [Thu, 26 Nov 2015 17:26:53 +0000 (12:26 -0500)]
freedreno/ir3: assign varying locations later
Rather than assigning inloc up front, when we don't yet know if it will
be unused, assign it last thing before the legalize pass.
Also, realize when inputs are unused (since for frag shader's we can't
rely on them being removed from ir->inputs[]). This doesn't make sense
if we don't also dynamically assign the inloc's, since we could end up
telling the hw the wrong # of varyings (since we currently assume that
the # of varyings and max-inloc are related..)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 26 Nov 2015 17:25:18 +0000 (12:25 -0500)]
freedreno/ir3: use instr flag to mark unused instructions
Rather than magic depth value, which won't be available in later stages.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 26 Nov 2015 17:21:21 +0000 (12:21 -0500)]
freedreno/a4xx: rework vinterp/vpsrepl
Same as previous commit, for a4xx.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 26 Nov 2015 17:18:14 +0000 (12:18 -0500)]
freedreno/a3xx: rework vinterp/vpsrepl
Make the interpolation / point-sprite replacement mode setup deal with
varying packing.
In a later commit, we switch to packing just the varying components that
are actually used by the frag shader, so we won't be able to assume
everything is vec4's aligned to vec4. Which would highly confuse the
previous vinterp/vpsrepl logic.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Serge Martin [Mon, 26 Oct 2015 15:53:00 +0000 (16:53 +0100)]
clover: fix tgsi compiler crash with invalid src
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Francisco Jerez [Mon, 23 Nov 2015 17:18:26 +0000 (19:18 +0200)]
i965/gen9+: Switch thread scratch space to non-coherent stateless access.
The thread scratch space is thread-local so using the full IA-coherent
stateless surface index (255 since Gen8) is unnecessary and
potentially expensive. On Gen8 and early steppings of Gen9 this is
not a functional change because the kernel already sets bit 4 of
HDC_CHICKEN0 which overrides all HDC memory access to be non-coherent
in order to workaround a hardware bug.
This happens to fix a full system hang when running any spilling code
on a pre-production SKL GT4e machine I have on my desk (forcing all
HDC access to non-coherent from the kernel up to stepping F0 might be
a good idea though regardless of this patch), and improves performance
of the OglPSBump2 SynMark benchmark run with INTEL_DEBUG=spill_fs by
33% (11 runs, 5% significance) on a production SKL GT2 (on which HDC
IA-coherency is apparently functional so it wouldn't make sense to
disable globally).
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Francisco Jerez [Wed, 25 Nov 2015 19:02:15 +0000 (21:02 +0200)]
i965/fs: Don't use Gen7-style scratch block reads on Gen9+.
Unfortunately Gen7 scratch block reads and writes seem to be hardwired
to BTI 255 even on Gen9+ where that index causes the dataport to do an
IA-coherent read or write. This change is required for the next patch
to be correct, since otherwise we would be writing to the scratch
space using non-coherent access and then reading it back using
IA-coherent reads, which wouldn't be guaranteed to return the value
previously written to the same location without introducing an
additional HDC flush in between.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Francisco Jerez [Mon, 23 Nov 2015 17:15:26 +0000 (19:15 +0200)]
i965: Add symbolic defines for some magic dataport surface indices.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Nicolai Hähnle [Thu, 19 Nov 2015 11:14:03 +0000 (12:14 +0100)]
radeon: use PIPE_DRIVER_QUERY_FLAG_DONT_LIST for perfcounters
Since the query names are not very enlightening, and there are thousands
of them, GALLIUM_HUD=help should only show the first and last query name
for each hardware block.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 19 Nov 2015 11:13:43 +0000 (12:13 +0100)]
gallium: add PIPE_DRIVER_QUERY_FLAG_DONT_LIST
This allows the driver to give a hint to the HUD so that GALLIUM_HUD=help is
less spammy.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 25 Nov 2015 11:32:23 +0000 (12:32 +0100)]
radeon: delay the generation of driver query names until first use
This shaves a bit more time off the startup of programs that don't
actually use performance counters.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Julien Isorce [Thu, 26 Nov 2015 08:21:45 +0000 (08:21 +0000)]
st/va: add missing profiles in PipeToProfile's switch.
Otherwise assert is raised from vlVaQueryConfigProfiles's for loop.
Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Marta Lofstedt [Wed, 25 Nov 2015 11:16:02 +0000 (12:16 +0100)]
mesa: remove ARB_geometry_shader4
No drivers currently implement ARB_geometry_shader4, nor are there
any plans to implement it. We only support the version of geometry
shaders that was incorporated into OpenGL 3.2 / GLSL 1.50.
Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tapani Pälli [Fri, 13 Nov 2015 09:13:05 +0000 (11:13 +0200)]
mesa: error out in indirect draw when vertex bindings mismatch
Patch adds additional mask for tracking which vertex arrays have
associated vertex buffer binding set. This array can be directly
compared to which vertex arrays are enabled and should match when
drawing.
Fixes following CTS tests:
ES31-CTS.draw_indirect.negative-noVBO-arrays
ES31-CTS.draw_indirect.negative-noVBO-elements
v2: update mask in vertex_array_attrib_binding
v3: rename mask and make it track _BoundArrays which matches what
was actually originally wanted (Fredrik Höglund)
v4: code cleanup, check for GLES 3.1 (Fredrik Höglund)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
Michel Dänzer [Thu, 26 Nov 2015 03:14:28 +0000 (12:14 +0900)]
targets/xvmc: use the non-inline sw helpers
This was missed in commit
59cfb21d ("targets: use the non-inline sw
helpers").
Fixes build failure:
CXXLD libXvMCgallium.la
../../../../src/gallium/auxiliary/pipe-loader/.libs/libpipe_loader_static.a(libpipe_loader_static_la-pipe_loader_sw.o):(.data.rel.ro+0x0): undefined reference to `sw_screen_create'
collect2: error: ld returned 1 exit status
Makefile:756: recipe for target 'libXvMCgallium.la' failed
make[3]: *** [libXvMCgallium.la] Error 1
Trivial.