Petar Avramovic [Fri, 12 Feb 2021 16:08:15 +0000 (17:08 +0100)]
AMDGPU/GlobalISel: Precommit globalisel tests for isKnownNeverNaN
Nicolas Vasilache [Fri, 12 Feb 2021 15:46:55 +0000 (15:46 +0000)]
[mlir][Linalg] NFC - Add an OpFoldResult-based builder for InitTensorOp
Yaxun (Sam) Liu [Fri, 12 Feb 2021 15:21:27 +0000 (10:21 -0500)]
Relands "[HIP] Change default --gpu-max-threads-per-block value to 1024"
This reverts commit
e384e94fbe7c1d5c89fcdde33ffda04e9802c2ce.
David Goldman [Fri, 4 Dec 2020 20:04:25 +0000 (15:04 -0500)]
Improve hover scopes for Objective-C code
- Instead of `AppDelegate::application:didFinishLaunchingWithOptions:` you
will now see `-[AppDelegate application:didFinishLaunchingWithOptions:]`
- Also include categories in the name when printing the scopes, e.g. `Class(Category)` and `-[Class(Category) method]`
Differential Revision: https://reviews.llvm.org/D68590
Kirstóf Umann [Tue, 21 Jul 2020 12:42:05 +0000 (14:42 +0200)]
[analyzer][Liveness][NFC] Remove an unneeded pass to collect variables that appear in an assignment
Suppose you stumble across a DeclRefExpr in the AST, that references a VarDecl.
How would you know that that variable is written in the containing statement, or
not? One trick would be to ascend the AST through Stmt::getParent, and see
whether the variable appears on the left hand side of the assignment.
Liveness does something similar, but instead of ascending the AST, it descends
into it with a StmtVisitor, and after finding an assignment, it notes that the
LHS appears in the context of an assignemnt. However, as [1] demonstrates, the
analysis isn't ran on the AST of an entire function, but rather on CFG, where
the order of the statements, visited in order, would make it impossible to know
this information by descending.
void f() {
int i;
i = 5;
}
`-FunctionDecl 0x55a6e1b070b8 <test.cpp:1:1, line:5:1> line:1:6 f 'void ()'
`-CompoundStmt 0x55a6e1b07298 <col:10, line:5:1>
|-DeclStmt 0x55a6e1b07220 <line:2:3, col:8>
| `-VarDecl 0x55a6e1b071b8 <col:3, col:7> col:7 used i 'int'
`-BinaryOperator 0x55a6e1b07278 <line:4:3, col:7> 'int' lvalue '='
|-DeclRefExpr 0x55a6e1b07238 <col:3> 'int' lvalue Var 0x55a6e1b071b8 'i' 'int'
`-IntegerLiteral 0x55a6e1b07258 <col:7> 'int' 5
void f()
[B2 (ENTRY)]
Succs (1): B1
[B1]
1: int i;
2: 5
3: i
4: [B1.3] = [B1.2]
Preds (1): B2
Succs (1): B0
[B0 (EXIT)]
Preds (1): B1
You can see that the arguments (rightfully so, they need to be evaluated first)
precede the assignment operator. For this reason, Liveness implemented a pass to
scan the CFG and note which variables appear in an assignment.
BUT.
This problem only exists if we traverse a CFGBlock in order. And Liveness in
fact does it reverse order. So a distinct pass is indeed unnecessary, we can
note the appearance of the assignment by the time we reach the variable.
[1] http://lists.llvm.org/pipermail/cfe-dev/2020-July/066330.html
Differential Revision: https://reviews.llvm.org/D87518
Jay Foad [Thu, 27 Aug 2020 15:15:33 +0000 (16:15 +0100)]
[TableGen][GlobalISel] Allow duplicate RendererFns
Allow different GICustomOperandRenderers to use the same RendererFn.
This avoids the need for targets to define a bunch of identical C++
renderer functions with different names.
Without this fix TableGen would have emitted code that tried to define
the GICR enumeration with duplicate enumerators.
Differential Revision: https://reviews.llvm.org/D96587
Sam McCall [Thu, 11 Feb 2021 15:32:09 +0000 (16:32 +0100)]
[clangd] Move command handlers into a map in ClangdLSPServer. NFC
Differential Revision: https://reviews.llvm.org/D96507
Nicolas Vasilache [Fri, 12 Feb 2021 13:50:10 +0000 (13:50 +0000)]
[mlir][Linalg] Improve region support in Linalg ops.
This revision takes advantage of the newly extended `ref` directive in assembly format
to allow better region handling for LinalgOps. Specifically, FillOp and CopyOp now build their regions explicitly which allows retiring older behavior that relied on specific op knowledge in both lowering to loops and vectorization.
Differential Revision: https://reviews.llvm.org/D96598
Haojian Wu [Thu, 11 Feb 2021 14:57:54 +0000 (15:57 +0100)]
[clangd] Remove the cross-file-rename option.
and simplify the code.
Differential Revision: https://reviews.llvm.org/D96578
David Green [Fri, 12 Feb 2021 14:28:57 +0000 (14:28 +0000)]
[ARM] Single source VMOVNT
Our current lowering of VMOVNT goes via a shuffle vector of the form
<0, N, 2, N+2, 4, N+4, ..>. That can of course also be a single input
shuffle of the form <0, 0, 2, 2, 4, 4, ..>, where we use a VMOVNT to
insert a vector into the top lanes of itself. This adds lowering of that
case, re-using the existing isVMOVNMask.
Differential Revision: https://reviews.llvm.org/D96065
Benjamin Kramer [Fri, 12 Feb 2021 14:04:12 +0000 (15:04 +0100)]
[mlir][spirv] Lower sexti -> SConvert
Kerry McLaughlin [Fri, 12 Feb 2021 10:57:31 +0000 (10:57 +0000)]
[SVE][LoopVectorize] Support for vectorization of loops with function calls
Changes `getScalarizationOverhead` to return an invalid cost for scalable VFs
and adds some simple tests for loops containing a function for which
there is a vectorized variant available.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D96356
Sanjay Patel [Fri, 12 Feb 2021 13:07:29 +0000 (08:07 -0500)]
[Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics
The vector reduction intrinsics started life as experimental ops, so backend support
was lacking. As part of promoting them to 1st-class intrinsics, however, codegen
support was added/improved:
D58015
D90247
So I think it is safe to now remove this complication from IR.
Note that we still have an IR-level codegen expansion pass for these as discussed
in D95690. Removing that is another step in simplifying the logic. Also note that
x86 was already unconditionally forming reductions in IR, so there should be no
difference for x86.
I spot checked a couple of the tests here by running them through opt+llc and did
not see any asm diffs.
If we do find functional differences for other targets, it should be possible
to (at least temporarily) restore the shuffle IR with the ExpandReductions IR
pass.
Differential Revision: https://reviews.llvm.org/D96552
Alex Zinenko [Fri, 12 Feb 2021 11:53:12 +0000 (12:53 +0100)]
[mlir] Use target-specific GPU kernel attributes in lowering pipelines
Until now, the GPU translation to NVVM or ROCDL intrinsics relied on the
presence of the generic `gpu.kernel` attribute to attach additional LLVM IR
metadata to the relevant functions. This would be problematic if each dialect
were to handle the conversion of its own options, which is the intended
direction for the translation infrastructure. Introduce `nvvm.kernel` and
`rocdl.kernel` in addition to `gpu.kernel` and base translation on these new
attributes instead.
Reviewed By: herhut
Differential Revision: https://reviews.llvm.org/D96591
Florian Hahn [Mon, 9 Nov 2020 15:23:04 +0000 (15:23 +0000)]
[VPlan] Make VPRecipeBase inherit from VPUser directly (NFC).
The individual recipes have been updated to manage their operands using
VPUser a while back. Now that the transition is done, we can instead
make VPRecipeBase a VPUser and get rid of the toVPUser helper.
Abhina Sreeskantharajan [Fri, 12 Feb 2021 12:12:12 +0000 (07:12 -0500)]
Mark output as text if it is really text
This is a continuation of https://reviews.llvm.org/D67696. The following places need to set the OF_Text flag correctly.
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D96363
luxufan [Fri, 12 Feb 2021 07:16:59 +0000 (15:16 +0800)]
[RISCV] Change parseVTypeI function
Change parseVTypeI function to Make the added vset instruction test cases report more concrete error message.
Differential Revision: https://reviews.llvm.org/D96218
David Sherwood [Tue, 2 Feb 2021 16:52:19 +0000 (16:52 +0000)]
[NFC][Analysis] Change struct VecDesc to use ElementCount
This patch changes the VecDesc struct to use ElementCount
instead of an unsigned VF value, in preparation for
future work that adds support for vectorized versions of
math functions using scalable vectors. Since all I'm doing
in this patch is switching the type I believe it's a
non-functional change. I changed getWidestVF to now return
both the widest fixed-width and scalable VF values, but
currently the widest scalable value will be zero.
Differential Revision: https://reviews.llvm.org/D96011
Vitaly Buka [Fri, 12 Feb 2021 06:02:45 +0000 (22:02 -0800)]
[ASAN][NFC] Improve language
Vitaly Buka [Fri, 12 Feb 2021 05:46:35 +0000 (21:46 -0800)]
[NFC][ProfileData] Improve language
Max Kazantsev [Fri, 12 Feb 2021 10:38:07 +0000 (17:38 +0700)]
[Test] Add test with uadd intrinsic with missing opt opportunity
Simon Pilgrim [Fri, 12 Feb 2021 10:01:53 +0000 (10:01 +0000)]
[DAG] DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT - break if-else chain. NFCI.
Style fixup - the if() block always returns so we can pull out the contents of the else() block.
Stephan Herhut [Fri, 12 Feb 2021 10:23:53 +0000 (11:23 +0100)]
[mlir][math] Fix cmake files after dialect splitting.
This fixes some missing dependencies that broke the shared library
build.
Sjoerd Meijer [Thu, 11 Feb 2021 16:44:10 +0000 (16:44 +0000)]
[MIRLangRef] Document MachineOperand comments
Late follow-up of D74306 to document MachineOperand comments in
MIRLangRef.
Differential Revision: https://reviews.llvm.org/D96518
Florian Hahn [Fri, 12 Feb 2021 09:29:02 +0000 (09:29 +0000)]
[AArch64] Add tests with sign cmps patterns that can be improved.
Some of the sign patterns can be optimized to or & asr, which requires
fewer instructions.
Sven van Haastregt [Fri, 12 Feb 2021 09:58:18 +0000 (09:58 +0000)]
[OpenCL][Docs] Clean up trailing characters
Clean up trailing whitespace and a stray backtick.
Sven van Haastregt [Fri, 12 Feb 2021 09:56:32 +0000 (09:56 +0000)]
[OpenCL][Docs] Describe internals of TableGen builtins
Add a high level explanation of the `-fdeclare-opencl-builtins` option.
Differential Revision: https://reviews.llvm.org/D96150
Stephan Herhut [Fri, 12 Feb 2021 09:34:42 +0000 (10:34 +0100)]
[mlir][math] Split off the math dialect.
This does not split transformations, yet. Those will be done as future clean ups.
Differential Revision: https://reviews.llvm.org/D96272
Jon Chesterfield [Fri, 12 Feb 2021 09:51:21 +0000 (09:51 +0000)]
[libomptarget][amdgcn] Build amdgcn devicertl as openmp
[libomptarget][amdgcn] Build amdgcn devicertl as openmp
Change cmake to build as openmp and fix up some minor errors in the code.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D96533
Maxim Kuvyrkov [Fri, 12 Feb 2021 09:47:37 +0000 (09:47 +0000)]
Fix exegesis build on aarch64-windows-msvc host
Include x86 intrinsics only when compiling for x86_64
or i386. _MSC_VER no longer implies x86.
Reviewed By: gchatelet
Differential Revision: https://reviews.llvm.org/D96498
David Sherwood [Mon, 8 Feb 2021 17:16:03 +0000 (17:16 +0000)]
[Analysis] Change VFABI::mangleTLIVectorName to use ElementCount
Adds support for mangling TLI vector names for scalable vectors.
Differential Revision: https://reviews.llvm.org/D96338
Alexander Belyaev [Fri, 12 Feb 2021 09:22:09 +0000 (10:22 +0100)]
[mlir] Initialize `isSmallAlloc` in `initialize` method.
Fraser Cormack [Thu, 11 Feb 2021 12:45:38 +0000 (12:45 +0000)]
[RISCV] Add support for integer fixed min/max
This patch extends the initial fixed-length vector support to include
smin, smax, umin, and umax.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D96491
Kristof Beyls [Thu, 11 Feb 2021 10:48:08 +0000 (11:48 +0100)]
[DeveloperPolicy] Specify LLVM's license more clearly.
Before, the first mention of LLVM's license on the developer policy page stated
that LLVM's license is Apache 2. This patch makes that more accurate by
mentioning the LLVM exception this first time the LLVM license is discussed on
that page, i.e. Apache-2.0 with LLVM-exception.
Technically, the correct SPDX identifier for LLVM's license is 'Apache-2.0 WITH
LLVM-exception', but I thought that writing the 'WITH' in lower case made the
paragraph easier to read without reducing clarity.
Differential Revision: https://reviews.llvm.org/D96482
wlei [Wed, 3 Feb 2021 22:13:06 +0000 (14:13 -0800)]
[CSSPGO][llvm-profgen] Add brackets for context id to support extended binary format
To align with https://reviews.llvm.org/D95547, we need to add brackets for context id before initializing the `SampleContext`.
Also added test cases for extended binary format from llvm-profgen side.
Differential Revision: https://reviews.llvm.org/D95929
Alexander Belyaev [Fri, 12 Feb 2021 09:04:41 +0000 (10:04 +0100)]
[mlir] Allow users of `PromoteBuffersToStackPass` to customize `small buffer` func.
Differential Revision: https://reviews.llvm.org/D96579
Raphael Isemann [Fri, 12 Feb 2021 07:51:43 +0000 (08:51 +0100)]
[lldb] Let TestPExpectTest test the right test class
This test supposed to check the test base we are using for pexpect tests, but instead it used the normal TestBase
class we use for all other tests. TestBase already had the substrs type check since D88792 so this
test was passing because of that.
This just changes the test base of the test to the pexpect one so that the `expect` calls find their intended
target function. Also moves the check to the very start so that we can check the argument without
actually having to start a terminal and all that jazz.
(I found this by accident as D88792 got somehow reverted in a downstream branch so this test started
failing).
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D96556
Sander de Smalen [Fri, 12 Feb 2021 08:00:28 +0000 (08:00 +0000)]
[BasicTTIImpl] Fix getCastInstrCost for scalable vectors by querying for ElementCount.
This fixes an overly restrictive assumption that the vector is a FixedVectorType,
in code that tries to calculate the cost of a cast operation when splitting
a too-wide vector. The algorithm works the same for scalable vectors, so this
patch removes the cast<FixedVectorType>.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D96253
Michael Kruse [Fri, 12 Feb 2021 08:18:34 +0000 (02:18 -0600)]
[Polly] Remove unused declaration. NFC.
Sander de Smalen [Fri, 12 Feb 2021 07:40:52 +0000 (07:40 +0000)]
[CostModel] An extending load to illegal type is not free.
COST(zext (<4 x i32> load(...) to <4 x i64>)) != 0 when
<4 x i64> is an illegal result type that requires splitting
of the operation.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D96250
Kazu Hirata [Fri, 12 Feb 2021 07:31:30 +0000 (23:31 -0800)]
[CodeGen] Use range-based for loops (NFC)
Kazu Hirata [Fri, 12 Feb 2021 07:31:29 +0000 (23:31 -0800)]
[PGO] Drop unnecessary const from return types (NFC)
Kazu Hirata [Fri, 12 Feb 2021 07:31:27 +0000 (23:31 -0800)]
[TableGen] Use ListSeparator (NFC)
Fangrui Song [Fri, 12 Feb 2021 06:53:56 +0000 (22:53 -0800)]
DebugInfo/Symbolize: Use stable_sort
This fixes coff-dwarf.test on some build bots.
The test relies on the sort order and prefers main (StorageClass: External) to .text (StorageClass: Static).
Max Kazantsev [Fri, 12 Feb 2021 06:48:40 +0000 (13:48 +0700)]
[Test] Add a potentially hanging test to prevent merging patches that hang it
Heejin Ahn [Thu, 11 Feb 2021 17:56:06 +0000 (09:56 -0800)]
[WebAssembly] Fix delegate's argument computation
I previously assumed `delegate`'s immediate argument computation
followed a different rule than that of branches, but we agreed to make
it the same
(https://github.com/WebAssembly/exception-handling/issues/146). This
removes the need for a separate `DelegateStack` in both CFGStackify and
InstPrinter.
When computing the immediate argument, we use a different function for
`delegate` computation because in MIR `DELEGATE`'s instruction's
destination is the destination catch BB or delegate BB, and when it is a
catch BB, we need an additional step of getting its corresponding `end`
marker.
Reviewed By: tlively, dschuff
Differential Revision: https://reviews.llvm.org/D96525
Peter Collingbourne [Thu, 4 Feb 2021 20:28:31 +0000 (12:28 -0800)]
gn build: Support cross-compiling libunwind for Android.
- Usual cross-compilation fix: s/target_/current_/g
- Define _LIBUNWIND_IS_NATIVE_ONLY to enable unwinding past
functions with return pointer authentication.
- Android needs two libunwind static libraries: one with symbols exported and
one without. These both need to be in the same build tree so
the libunwind_hermetic_static_library configuration option doesn't
help here. Replace it with build rules that build both libraries.
- Install the libraries in the location that Android expects them to be.
Differential Revision: https://reviews.llvm.org/D96563
Pushpinder Singh [Mon, 8 Feb 2021 06:47:30 +0000 (12:17 +0530)]
[OpenMP][AMDGPU] Add support for linking libomptarget bitcode
This patch uses the existing logic of CUDA for searching libomptarget
and extracts it to a common method.
Reviewed By: JonChesterfield, tianshilei1992
Differential Revision: https://reviews.llvm.org/D96248
Craig Topper [Fri, 12 Feb 2021 05:02:50 +0000 (21:02 -0800)]
[TableGen] Make the map in InfoByHwMode protected. NFCI
Switch some for loops to just use the begin()/end() implementations
in the InfoByHwMode struct.
Add a method to insert into the map for the one case that was
modifying the map directly.
Michael Kruse [Fri, 12 Feb 2021 03:56:50 +0000 (21:56 -0600)]
[Polly] Sanitize optimization levels.
The description of the -polly switch stated that it was only enabled
with -O3. This was a lie, the optimization level was ignored. Only at
-O0 Polly was not added to the pass pipeline because the pass builder,
but only because the extension points were not triggered.
In the NewPM, the VectorizerStart extensions point is actually trigger
even with -O0 which leads to the following crash:
Assertion `Level != OptimizationLevel::O0 && "Must request optimizations!"' failed.
We sanitize the optimization levels using the following rules for both
pass mangers:
1. Only enable Polly if optimizing at all (-O1, -O2 or -O3).
2. Do not enable Polly when optimizing for size.
3. Ignore the optimization level for diagnostic passes (printer, viewer
or JScop-exporter).
4. If only diagnostic passes enabled, skip the code-generation.
5. Fix the description of the -polly command line option.
Jianzhou Zhao [Fri, 12 Feb 2021 05:00:50 +0000 (05:00 +0000)]
[dfsan] Fix building OriginAddr at non-linux OS
Fix the broken build by D96545
Jonas Devlieghere [Fri, 12 Feb 2021 04:40:00 +0000 (20:40 -0800)]
[lldb] s/TARGET_OS_EMBEDDED/TARGET_OS_IPHONE/
TARGET_OS_EMBEDDED is deprecated, use TARGET_OS_IPHONE and/or
TARGET_OS_SIMULATOR instead.
Jonas Devlieghere [Fri, 12 Feb 2021 04:20:04 +0000 (20:20 -0800)]
[lldb] Fix 'r' and 'run' aliases on Apple Silicon
The 'r' and 'run' aliases were different based on the target
architecture. I suspect the intention was to disable shell expansion on
embedded devices. This fixes TestCustomShell.test on AS.
James Y Knight [Fri, 12 Feb 2021 03:26:12 +0000 (22:26 -0500)]
Fix bitcode decoder error in "Encode alignment attribute for `atomicrmw`"
The wrong record field number was being used in bitcode decoding,
which broke a self-hosted LTO build. (Yet, somehow, this _doesn't_
seem to have broken simple bitcode encode/decode roundtrip tests, and
I'm not sure why...)
Fixes commit
d06ab79816785fa362e7d96d7a398bea8064cba7
Amara Emerson [Fri, 12 Feb 2021 03:14:41 +0000 (19:14 -0800)]
[GlobalISel] Fix sext_inreg(load) combine to not move the originating load.
The builder was using the extend user as the insertion point, which meant that
we were incorrectly "moving" the load from its original position, and therefore
could violate memory operation ordering.
Fangrui Song [Fri, 12 Feb 2021 03:22:44 +0000 (19:22 -0800)]
DebugInfo/Symbolize: Don't differentiate function/data symbolization
Before
d08bd13ac8a560c4645e17e192ca07e1bdcd2895, only `SymbolRef::ST_Function`
symbols were used for .symtab symbolization. That commit added a `"DATA"` mode
to llvm-symbolizer which used `SymbolRef::ST_Data` symbols for symbolization.
Since function and data symbols have different addresses, we don't need to
differentiate the two modes. This patches unifies the two modes to simplify
code.
`"DATA"` is used by `compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_libcdep.cpp`.
`check-hwasan` and `check-tsan` have runtime tests.
Differential Revision: https://reviews.llvm.org/D96322
Tom Stellard [Thu, 11 Feb 2021 22:28:19 +0000 (22:28 +0000)]
Partially Revert "scan-view: Remove Reporter.py and associated AppleScript files"
This reverts some of commit
dbb01536f6f49fa428f170e34466072ef439b3e9.
The Reporter module was still being used by the ScanView.py module and deleting
it caused scan-view to fail. This commit adds back Reporter.py but removes the
code the references the AppleScript files which were removed in
dbb01536f6f49fa428f170e34466072ef439b3e9.
Reviewed By: NoQ
Differential Revision: https://reviews.llvm.org/D96367
Michael Kruse [Thu, 11 Feb 2021 19:38:06 +0000 (13:38 -0600)]
[Polly] Hide IslScheduleOptimizer implementation from header. NFC.
These are implementation details of the IslScheduleOptimizer pass
implementation and not use anywhere else. Hence, we can move them to the
cpp file and into an anonymous namespace.
Only getPartialTilePrefixes is, aside from the pass itself, used
externally (by the ScheduleOptimizerTest) and moved into the polly
namespace.
Aart Bik [Thu, 11 Feb 2021 20:11:34 +0000 (12:11 -0800)]
[mlir] detect integer overflow in debug mode
Rationale:
This computation failed ASAN for the following input
(integer overflow during
4032000000000000000 * 100):
tensor<100x200x300x400x500x600x700x800xf32>
This change adds a simple overflow detection during
debug mode (which we run more regularly than ASAN).
Arguably this is an unrealistic tensor input, but
in the context of sparse tensors, we may start to
see cases like this.
Bug:
https://bugs.llvm.org/show_bug.cgi?id=49136
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D96530
Philip Reames [Fri, 12 Feb 2021 01:55:29 +0000 (17:55 -0800)]
[knownbits] Preserve known bits for small shift recurrences
The motivation for this is that I'm looking at an example that uses shifts as induction variables. There's lots of other omissions, but one of the first I noticed is that we can't compute tight known bits. (This indirectly causes SCEV's range analysis to produce very poor results as well.)
Differential Revision: https://reviews.llvm.org/D96440
Sam Clegg [Wed, 3 Feb 2021 03:03:16 +0000 (19:03 -0800)]
[lld][WebAssembly] Fix for weak undefined functions in -pie mode
This fixes two somewhat related issues. Firstly we were never
generating imports for weak functions (even with the `import-functions`
policy for undefined symbols). Adding a direct call to foo in the
`weak-undefined-pic.s` exposed a crash in the linker which this
change fixes.
Secondly we were failing to call `handleWeakUndefines` for the `-pie`
case which is PIC but doesn't set the undefined symbol policy to
`import-functions`. With this change `-pie` binaries will by default
call `handleWeakUndefines` which generates the undefined stub handlers
for any weakly undefined symbols.
Fixes: https://github.com/emscripten-core/emscripten/issues/13337
Differential Revision: https://reviews.llvm.org/D95914
Philip Reames [Fri, 12 Feb 2021 01:06:49 +0000 (17:06 -0800)]
[tests] Autogen update test to remove whitespace diffs
Philip Reames [Fri, 12 Feb 2021 01:02:59 +0000 (17:02 -0800)]
[tests] precommit a tests for D96534 (and other range quality items)
Philip Reames [Fri, 12 Feb 2021 00:51:12 +0000 (16:51 -0800)]
[tests] Autogen a few tests for ease of update
Vitaly Buka [Fri, 12 Feb 2021 00:36:16 +0000 (16:36 -0800)]
[NFC,memprof] Update test after D96319
Vitaly Buka [Wed, 10 Feb 2021 11:38:19 +0000 (03:38 -0800)]
[Msan, NewPM] Reduce size of msan binaries
EarlyCSEPass called after msan redices code size by about 10%.
Similar optimization exists for legacy pass manager in
addGeneralOptsForMemorySanitizer.
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D96406
Craig Topper [Thu, 11 Feb 2021 23:34:09 +0000 (15:34 -0800)]
[RISCV] Add a pattern for a scalable vector mask vnot.
We can use a vnand.mm with the same register for both inputs.
This avoids materializing an alls ones constant with vmset.mm.
Vitaly Buka [Wed, 10 Feb 2021 22:28:48 +0000 (14:28 -0800)]
[NFC] Extract function which registers sanitizer passes
Reviewed By: aeubanks
Differential Revision: https://reviews.llvm.org/D96481
Julian Lettner [Tue, 9 Feb 2021 18:01:54 +0000 (10:01 -0800)]
[Sanitizer] Fix sanitizer tests without reducing optimization levels
As discussed, these tests are compiled with optimization to mimic real
sanitizer usage [1].
Let's mark relevant functions with `noinline` so we can continue to
check against the stack traces in the report.
[1] https://reviews.llvm.org/D96198
This reverts commit
04af72c5423eb5ff7c0deba2d08cb46d583bb9d4.
Differential Revision: https://reviews.llvm.org/D96357
Valentin Clement [Thu, 11 Feb 2021 23:09:39 +0000 (18:09 -0500)]
[flang][fir][NFC] Move BoxType to TableGen type definition
This patch is a follow up of D96422 and move BoxType to TableGen.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D96476
Peter Collingbourne [Thu, 17 Dec 2020 01:53:20 +0000 (17:53 -0800)]
ObjectFileELF: Test whether reloc_header is non-null instead of asserting.
It is possible for the GetSectionHeaderByIndex lookup to fail because
the previous FindSectionContainingFileAddress lookup found a segment
instead of a section. This is possible if the binary does not have
a PLT (which means that lld will in some circumstances set DT_JMPREL
to 0, which is typically an address that is part of the ELF headers
and not in a section) and may also be possible if the section headers
have been stripped. To handle this possibility, replace the assert
with an if.
Differential Revision: https://reviews.llvm.org/D93438
Dave Lee [Thu, 11 Feb 2021 20:02:17 +0000 (12:02 -0800)]
[lldb] Add step target to ThreadPlanStepInRange constructor
`QueueThreadPlanForStepInRange` accepts a `step_into_target`, but the constructor for
`ThreadPlanStepInRange` does not. Instead, a caller would optionally call
`SetStepInTarget()` in a separate statement.
This change adds `step_into_target` as a constructor argument. This simplifies
construction of `ThreadPlanSP`, by avoiding a subsequent downcast and conditional
assignment. This constructor is already used in downstream repos.
Differential Revision: https://reviews.llvm.org/D96539
Hongtao Yu [Thu, 11 Feb 2021 22:51:47 +0000 (14:51 -0800)]
Remove test code that cause MSAN failure.
Summary:
The negative test (with the feature being added disabled) caused MSAN failure and that's the added feature is supposed to fix. Therefore the negative test code is being removed.
Dan Gohman [Mon, 12 Oct 2020 21:53:40 +0000 (14:53 -0700)]
[WebAssembly] Use the new crt1-command.o if present.
If crt1-command.o exists in the sysroot, the libc has new-style command
support, so use it.
Differential Revision: https://reviews.llvm.org/D89274
Nicolas Vasilache [Thu, 11 Feb 2021 22:26:49 +0000 (22:26 +0000)]
s[mlir] Tighten computation of inferred SubView result type.
The AffineMap in the MemRef inferred by SubViewOp may have uncompressed symbols which result in type mismatch on otherwise unused symbols. Make the computation of the AffineMap compress those unused symbols which results in better canonical types.
Additionally, improve the error message to report which inferred type was expected.
Differential Revision: https://reviews.llvm.org/D96551
ShihPo Hung [Thu, 11 Feb 2021 22:19:30 +0000 (14:19 -0800)]
[RISCV] Initial support for insert/extract subvector
This patch handles cast-like insert_subvector & extract_subvector
in which case:
1. index starts from 0.
2. inserting a fixed-width vector into a scalable vector,
or extracting a fixed-width vector from a scalable vector.
Reviewed By: craig.topper, frasercrmck
Differential Revision: https://reviews.llvm.org/D96352
James Y Knight [Thu, 11 Feb 2021 22:33:43 +0000 (17:33 -0500)]
NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg.
The ability to specify alignment was recently added, and it's an
important property which we should ensure is set as expected by
Clang. (Especially before making further changes to Clang's code in
this area.) But, because it's on the end of the lines, the existing
tests all ignore it.
Therefore, update all the tests to also verify the expected alignment
for atomicrmw and cmpxchg. While I was in there, I also updated uses
of 'load atomic' and 'store atomic', and added the memory ordering,
where that was missing.
Jianzhou Zhao [Thu, 11 Feb 2021 21:50:17 +0000 (21:50 +0000)]
[dfsan] Introduce memory mapping for origin tracking
Reviewed-by: morehouse
Differential Revision: https://reviews.llvm.org/D96545
Hafiz Abid Qadeer [Thu, 11 Feb 2021 22:08:25 +0000 (22:08 +0000)]
Replace deprecated %T in 2 tests.
In D91442, @MaskRay commented about a failure. This commit does the following to
address his comments:
1. Replace %T with %t as former is deprecated.
2. Add an explicit --sysroot argument in a test.
Some tests were failing when gcc-10-riscv64-linux-gnu is installed on test machine.
This was happening because the test was checking a case when --gcc-toolchain is not
provided. But if --sysroot was also not provided then code could pick a toolchain
installed in /usr. So to make the test more robust, I have provided an explicit --sysroot
argument. Its value has been chosen to match the existing patterns.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D93023
Pengxuan Zheng [Thu, 11 Feb 2021 22:18:40 +0000 (14:18 -0800)]
[AArch64] Adding Neon Sm3 & Sm4 Intrinsics
This adds SM3 and SM4 Intrinsics support for AArch64, specifically:
vsm3ss1q_u32
vsm3tt1aq_u32
vsm3tt1bq_u32
vsm3tt2aq_u32
vsm3tt2bq_u32
vsm3partw1q_u32
vsm3partw2q_u32
vsm4eq_u32
vsm4ekeyq_u32
Reviewed By: labrinea
Differential Revision: https://reviews.llvm.org/D95655
Guillaume Chatelet [Thu, 11 Feb 2021 21:53:41 +0000 (21:53 +0000)]
Fix errors in distributions
AndreyChurbanov [Thu, 11 Feb 2021 21:43:13 +0000 (00:43 +0300)]
[OpenMP] libomp: minor changes to improve library performance
Three minor changes in this patch:
- added UNLIKELY hint to few rarely executed branches;
- replaced couple of run time checks with debug assertions;
- moved check of presence of ittnotify tool from inside the function call.
Differential Revision: https://reviews.llvm.org/D95816
Hongtao Yu [Thu, 11 Feb 2021 21:29:29 +0000 (13:29 -0800)]
Undo test changs introduced by D96193.
Summary:
The test doesn't work on Windows but there seems no good way to disable the test for Windows only so I'm undoing the test changes.
Douglas Yung [Thu, 11 Feb 2021 21:11:50 +0000 (13:11 -0800)]
NFCI. With the move to the new pass manager by default, sanitize-coverage.c is now passing on ARM.
This change removes the XFAIL from the original test and duplicates the test into sanitize-coverage-old-pm.c
which uses the old pass manager and has the corresponding XFAIL.
This should fix the XPASS from this and similar runs:
http://lab.llvm.org:8011/#/builders/60/builds/1875
Jonas Devlieghere [Thu, 11 Feb 2021 21:16:46 +0000 (13:16 -0800)]
[lldb] Disable x86-multithread-write.test with reproducers
This test is failing on GreenDragon. Disabling it until I have bandwidth
to investigate why the register values are different during replay.
Hansang Bae [Fri, 5 Feb 2021 14:53:40 +0000 (08:53 -0600)]
[OpenMP] Enable omp_get_num_devices() on Windows
This patch enables omp_get_num_devices() and omp_get_initial_device() on
Windows by providing an alternative to dlsym on Windows, and proposes to
add a new libomptarget entry, __tgt_get_num_devices().
Differential Revision: https://reviews.llvm.org/D96182
Guillaume Chatelet [Thu, 11 Feb 2021 20:47:43 +0000 (20:47 +0000)]
Fix incorrect indentation in LangRef.rst
Hongtao Yu [Tue, 9 Feb 2021 17:17:20 +0000 (09:17 -0800)]
[CSSPGO] Process functions in a top-down order on a dynamic call graph.
Functions are currently processed by the sample profiler loader in a top-down order defined by the static call graph. The order is being adjusted to be a top-down order based on the input context-sensitive profile. One benefit is that the processing order of caller and callee in one SCC would follow the context order in the profile to favor more inlining. Another benefit is that the processing order of caller and callee through an indirect call (which is not on the static call graph) can be honored which in turn allows for more inlining.
The profile top-down order for SCC is also extended to support non-CS profiles.
Two switches `-mllvm -use-profile-indirect-call-edges` and `-mllvm -use-profile-top-down-order` are being introduced.
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D95988
Guillaume Chatelet [Thu, 11 Feb 2021 20:34:19 +0000 (20:34 +0000)]
Fix incorrect indentation in LangRef.rst
Guillaume Chatelet [Thu, 11 Feb 2021 20:17:50 +0000 (15:17 -0500)]
Encode alignment attribute for `cmpxchg`
This is a follow up patch to D83136 adding the align attribute to `cmpxchg`.
See also D83465 for `atomicrmw`.
Differential Revision: https://reviews.llvm.org/D87443
Guillaume Chatelet [Thu, 11 Feb 2021 20:17:37 +0000 (15:17 -0500)]
Encode alignment attribute for `atomicrmw`
This is a follow up patch to D83136 adding the align attribute to `atomicwmw`.
Differential Revision: https://reviews.llvm.org/D83465
Stanislav Mekhanoshin [Wed, 10 Feb 2021 00:47:13 +0000 (16:47 -0800)]
[AMDGPU] Fix promote alloca with double use in a same insn
If we have an instruction where more than one pointer operands
are derived from the same promoted alloca, we are fixing it for
one argument and do not fix a second use considering this user
done.
Fix this by deferring processing of memory intrinsics until all
potential operands are replaced.
Fixes: SWDEV-271358
Differential Revision: https://reviews.llvm.org/D96386
Stanislav Mekhanoshin [Thu, 4 Feb 2021 22:21:02 +0000 (14:21 -0800)]
Move implementation of isAssumeLikeIntrinsic into IntrinsicInst
This is remove dependency on ValueTracking in the future patch.
Differential Revision: https://reviews.llvm.org/D96079
Eric Schweitz [Thu, 11 Feb 2021 19:23:49 +0000 (11:23 -0800)]
[flang][fir][NFC] Rename WhereOp to IfOp.
Haojian Wu [Thu, 11 Feb 2021 13:58:16 +0000 (14:58 +0100)]
[clangd] Retire the cross-file-rename command-line flag.
This patch only focuses on the flag. Removing actual single-file mode
(and the flag in RenameOption) will come in a follow-up.
Differential Revision: https://reviews.llvm.org/D96495
Pavel Labath [Thu, 11 Feb 2021 19:25:10 +0000 (20:25 +0100)]
Revert "[lldb/test] Automatically find debug servers to test"
The commit
7df4eaaa937332c0617aa665080533966e2c98a0 appears to
break the windows bot. Revert while I investigate.
peter klausler [Thu, 11 Feb 2021 00:15:20 +0000 (16:15 -0800)]
[flang] Don't perform macro replacement unless *.F, *.F90, &c.
Avoid spurious and confusing macro replacements from things like
-DPIC on Fortran source files whose suffixes indicate that preprocessing
is not expected.
Add gfortran-like "-cpp" and "-nocpp" flags to f18 to force predefinition
of macros independent of the source file suffix.
Differential Revision: https://reviews.llvm.org/D96464
Snehasish Kumar [Tue, 9 Feb 2021 22:13:47 +0000 (14:13 -0800)]
[CodeGen] Split out cold exception handling pads.
Support for splitting exception handling pads was added in D73739. This
change updates the code to split out exception handling pads if profile
information indicates that they are cold. For a given function with
multiple landind pads, if one of them is hot they are all retained as
part of the hot code section.
Differential Revision: https://reviews.llvm.org/D96372
Adrian Prantl [Thu, 11 Feb 2021 19:06:44 +0000 (11:06 -0800)]
llvm-dwarfdump: fix the counting when printing DW_OP_entry_value
The block size is in bytes, and not number of operands.
Differential Revision: https://reviews.llvm.org/D96472
Snehasish Kumar [Wed, 10 Feb 2021 03:14:47 +0000 (19:14 -0800)]
[CodeGen] Basic block sections should take precendence over splitting.
The use of basic block sections should take precedence over the machine
function splitting pass. Since they use the same underlying mechanism
they are kept exclusive. Updated the tests to check that split machine
functions is overridden by all flavours of basic block sections.
Differential Revision: https://reviews.llvm.org/D96392