Rhys Perry [Fri, 13 May 2022 12:39:01 +0000 (13:39 +0100)]
aco: use p_parallelcopy for uniform reduction with zero source
I think v_mov_b32 was only used because a sub-dword p_parallelcopy
couldn't take constants on some gfx levels. That shouldn't be the case
anymore.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16595>
Juan A. Suarez Romero [Fri, 27 May 2022 11:32:50 +0000 (13:32 +0200)]
v3d: expose GL_ARB_draw_buffers_blend
This automatically exposes GL_OES_draw_buffers_indexed too.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16747>
Juan A. Suarez Romero [Fri, 27 May 2022 11:12:11 +0000 (13:12 +0200)]
v3d: fix blending for mixed RT formats
Blending configuration needs to be adapted in case the RT format does
not have an alpha channel. This is handled so far correctly.
But when we have two RT, one with alpha and other without it, we need
to split the blend configuration, so one is adapted and the other not.
Otherwise we would be changing the blend config for the wrong RT.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16747>
Juan A. Suarez Romero [Tue, 31 May 2022 09:23:35 +0000 (11:23 +0200)]
ci: bump VK-GL-CTS to 1.3.2.0
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16689>
Mike Blumenkrantz [Tue, 31 May 2022 13:02:06 +0000 (09:02 -0400)]
zink: lower subgroup width to 1 for unsupported subgroup vote stages
this should handle unsupported gfx subgroup vote
cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16757>
Mike Blumenkrantz [Fri, 27 May 2022 20:40:10 +0000 (16:40 -0400)]
zink: fix subgroup vote detection
this is uses the 1.1 features, not 1.3
also check the shader stages available since the GL extension requires
all of them
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16757>
Mike Blumenkrantz [Fri, 27 May 2022 21:03:43 +0000 (17:03 -0400)]
zink: use correct scope for subgroup vote ops
this is restricted to subgroup for vulkan use
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16757>
Mike Blumenkrantz [Fri, 27 May 2022 21:03:29 +0000 (17:03 -0400)]
zink: emit spirv cap for subgroup vote ops
cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16757>
Mike Blumenkrantz [Fri, 27 May 2022 20:16:04 +0000 (16:16 -0400)]
zink: require draw params ext/cap in ntv if drawid is used
cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16757>
Jason Ekstrand [Mon, 30 May 2022 23:57:58 +0000 (18:57 -0500)]
nir: Add a correctness note for nir_lower_phis_to_regs_block
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16111>
Jason Ekstrand [Fri, 22 Apr 2022 21:37:37 +0000 (16:37 -0500)]
nir: Handle register sources in lower_phis_to_regs_block
During certain control-flow manipulation passes, we go out-of-SSA
temporarily in certain areas of the code to make control-flow
manipulation easier. This can result in registers being in phi sources
temporarily. If two sub-passes run before we get a chance to do
clean-up, we can end up doing some out-of-SSA and then a bit more
out-of-SSA and trigger this case. It's easy enough to handle.
Fixes:
a620f66872c2 ("nir: Add a couple quick-and-dirty out-of-SSA helpers")
Fixes:
79a987ad2a1e ("nir/opt_if: also merge break statements with ones after the branch")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6370
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16111>
Jason Ekstrand [Mon, 30 May 2022 14:52:10 +0000 (09:52 -0500)]
isl: Add some asserts about multisampled surfaces
This isn't really necessary because the API doesn't allow MSAA and
mipmapping at the same time but people forget that pretty often so it's
good to have it as documentation if nothing else.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14129>
Jason Ekstrand [Tue, 6 Jul 2021 15:59:49 +0000 (10:59 -0500)]
anv: Implement VK_EXT_image_view_min_lod
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14129>
Jason Ekstrand [Tue, 6 Jul 2021 15:54:28 +0000 (10:54 -0500)]
intel/isl: Add isl_view::min_lod_clamp for IVB+
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14129>
Jason Ekstrand [Wed, 8 Dec 2021 22:45:33 +0000 (16:45 -0600)]
vulkan/runtime: Add min_lod to vk_image_view
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14129>
Pierre-Eric Pelloux-Prayer [Wed, 25 May 2022 14:05:39 +0000 (16:05 +0200)]
radeonsi: enable use_waterfall_for_divergent_tex_samplers
And run the nir_divergence_analysis pass in si_get_nir_shader to make
sure it's up to date.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2253
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16709>
Pierre-Eric Pelloux-Prayer [Wed, 25 May 2022 13:57:53 +0000 (15:57 +0200)]
ac/llvm: add use_waterfall_for_divergent_tex_samplers option
GLSL says that indexing in a samplers array should be done with
a dynamically uniform value.
If the app doesn't obey this constraint, it'll get incorrect
results.
But there's one case where the app might be correct and yet
get incorrect result: if 2 consecutive draws are used, with no
state changes in between, the hardware might run them in the
same wave and the app will get incorrect result as-if it was
using non-dynamically uniform index.
To prevent this, this commit takes advantage of the divergence
analysis pass - if the index is marked as divergent, then it will
have the same effect as using ACCESS_NON_UNIFORM in SPIR-V.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16709>
Karol Herbst [Tue, 26 Apr 2022 19:22:43 +0000 (21:22 +0200)]
nir/gce: pin call instructions
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16202>
Karol Herbst [Tue, 26 Apr 2022 15:12:07 +0000 (17:12 +0200)]
nir/gather_info: allow to run it before inlining
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16202>
M Henning [Wed, 18 May 2022 19:38:26 +0000 (15:38 -0400)]
nv50: Fix tlsSpace alignment
Commit
d1ff453a added this alignment in the wrong spot - it needs to
happen after RA because spilling can increment this 32 bits at a time.
Also assert that we align this correctly now.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16596>
Timur Kristóf [Thu, 26 May 2022 11:36:14 +0000 (13:36 +0200)]
ac/nir/taskmesh: Use 3 dimensional workgroup ID.
For the sake of consistency, do not rely on a 1-dimensional
workgroup ID anymore.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16721>
Timur Kristóf [Thu, 26 May 2022 11:35:24 +0000 (13:35 +0200)]
ac/nir/taskmesh: Use task shader lowering from common NIR code.
This also implements task_payload atomics for RADV.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16721>
Timur Kristóf [Fri, 13 May 2022 19:32:12 +0000 (21:32 +0200)]
radv, ac/nir: Fix multiview layer export for mesh shaders.
Unfortunately, radv_lower_multiview is not suitable for mesh shaders
because it can't know the mapping between API mesh shader
invocations and output primitives.
Additionally, when lowering view id to layer, it must be created
as a per-primitive PS input.
Fixes:
d32656bc65a7c0165e53d551e23462d626bbf870
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16504>
Erico Nunes [Fri, 20 May 2022 15:25:15 +0000 (17:25 +0200)]
lima/ci: reenable lima-mali450-piglit-gpu:arm64
With the kernel uprev we are no longer affected by the kernel
regression that was causing issues.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16641>
Erico Nunes [Tue, 24 May 2022 12:24:50 +0000 (14:24 +0200)]
lima/ci: update piglit ci expectations
This new test reports a failure and started to run during the time
piglit runs were temporarily disabled.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16641>
Erico Nunes [Fri, 20 May 2022 15:23:53 +0000 (17:23 +0200)]
ci: update docs for linux kernel uprevs
Update a few paths that have changed since this doc was first submitted.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16641>
Erico Nunes [Fri, 20 May 2022 15:21:21 +0000 (17:21 +0200)]
ci: update linux kernel to v5.17
In addition to pushing it to the current latest stable, the v5.17 kernel
for mesa CI pulls a patch to address a regression in drm that affects at
least the lima jobs.
The dtb for sc7180-trogdor-lazor-limozeen-nots is also updated since the
old one no longer exists in v5.17.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16641>
Iago Toral Quiroga [Mon, 30 May 2022 07:12:22 +0000 (09:12 +0200)]
v3dv: limit sync for barriers to hw queues selected by source mask
Until know when we consumed a barrier we would implement it by
setting the serialize flag on a job, which would cause it to
be serialized across all hardware queues (CL, CSD, TFU). However,
now that we track the source(s) of the barrier, we can restrict this
to only the relevant queue(s) instead (multisync path only).
It should be noted that we can implement transfers via TFU or CL
jobs, so if the source of a barrier is a transfer, we currently
synchronize against both the TFU and the CL queues, however, we
may be able to more effectively track this in the future to
restrict this to just one of the queues.
Also, for secondary command buffers we are taking the easy way
out and always synchronize against all queues, but we should
be able to do the same for secondaries without too much effort.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16743>
Iago Toral Quiroga [Mon, 30 May 2022 06:52:31 +0000 (08:52 +0200)]
v3dv: track sources of barriers
Until now we have been tracking the dstStageMask of barriers (where they
are consumed) but not where they are produced (the srcStageMask). With
this change we extend our barrier state to keep track of this as well.
This allows the driver to have better knowledge of the intended barrier
semantics so it can limit the amount of synchronization it does only
to the source stages involved with a barrier. We will do this in a
later patch.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16743>
Iago Toral Quiroga [Mon, 30 May 2022 06:31:17 +0000 (08:31 +0200)]
v3dv: use an explicit struct type to track barrier state
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16743>
Iago Toral Quiroga [Mon, 30 May 2022 06:04:04 +0000 (08:04 +0200)]
v3dv: only clear BCL barrier state if we don't have pending graphics barriers
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16743>
Iago Toral Quiroga [Wed, 25 May 2022 11:56:33 +0000 (13:56 +0200)]
v3dv: consume barriers at the right stages
Until now, we have always consumed barriers with the next GPU job
recorded into the command buffer after the barrier even if the job
was not the target of the barrier itself. This works based on the
idea that when we consume a barrier in a job we serialize it against
all queues, so effectively we are ensuring that whatever came
before it has completed, so if the barrier was intended for an
even later job, it would have served its purpose anyway.
It should be noted that CL jobs are special because they are actually
split in two different queues: the binning queue and the render
queue, with a dependency between them to ensure render runs after
binning. With our current implementation, if we have 3 jobs (A, B,
C) and we have a barrier after job A which is intended to block job C
on A's completion, with our implementation we would instead block
B on A's completion. If C is a CL job, and the barrier was targetting
the binning stage then we can have the following scenarios:
1. If B) is a CL job, it will consume the barrier at its binning
stage, so we know that B's binning will not start until A has
completed. Then C's binning will not start until B's binning
has completed, and thus, will not start until A has completed,
as intended.
2. If B) is not a CL job, it will consume the barrier and will not
start until A has completed, however, C's binning job will be
submitted to the binning queue without any sync requirements
and since B did not put any jobs in the binning queue it will
start as soon as A's binning has completed, but not A's render,
which would be incorrect.
Further, since
a981ac0539 we now skip consumming BCL barriers if
a job does not have draw calls that can be affected by them. In the
same scenarios as before, now case 1) would also be problematic,
since B may skip the binning sync in that case and start immediately,
and since C's binning would be allowe to start immediately after B's
binning, there is no guarantee that this doesn't happen in parallel
with A's render.
With this patch we fix this situation by tracking the intended
consumer of each barrier: graphics, compute or transfer, and we make
sure to consume them only with jobs that match those semantics.
This fixes flakyness in dEQP-VK.device_group.*
Fixes:
a981ac0539 ('v3dv: skip binning sync if binning shaders don't access external resources')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16743>
Marek Olšák [Thu, 26 May 2022 15:55:08 +0000 (11:55 -0400)]
ac/gpu_info: always retile DCC on gfx10 and newer chips
Unaligned DCC doesn't work there.
Fixes:
f8cf5ea982a - amd: add support for gfx1036 and gfx1037 chips
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16726>
Vinson Lee [Mon, 23 May 2022 23:39:10 +0000 (16:39 -0700)]
amd: Initialize Gfx11Lib members in constructor.
Fix defects reported by Coverity Scan.
Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member m_numPkrLog2 is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member m_numSaLog2 is not initialized in this constructor nor in any functions that it calls.
Fixes:
4fdf42b3c29 ("amd: import gfx11 addrlib")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16679>
Ben Skeggs [Mon, 8 Nov 2021 05:33:54 +0000 (15:33 +1000)]
nv50/ir: fix ALD/AST where address comes from AL2P
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16784>
Ben Skeggs [Fri, 5 Nov 2021 23:51:59 +0000 (09:51 +1000)]
nv50/ir: fix scope of memory ops on ampere
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16784>
Ben Skeggs [Fri, 5 Nov 2021 05:58:36 +0000 (15:58 +1000)]
nv50/ir: fix OUT.FINAL on ampere
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16784>
Karol Herbst [Mon, 30 May 2022 21:39:59 +0000 (23:39 +0200)]
nv50/ir: recoginse Ampere
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16784>
Hyunjun Ko [Mon, 30 May 2022 06:26:15 +0000 (06:26 +0000)]
ir3: handle intrinsic_load_draw_id when scanning driver constants
Fixes: #6567
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16769>
Timothy Arceri [Mon, 7 Feb 2022 08:10:13 +0000 (19:10 +1100)]
nir/gcm: fix pushing instructions into if blocks
The previous logic would just set the block to the instructions
original location if we couldn't evict it from a loop.
For now we only push const loads to a later block inside ifs
but we can add more heuristics later. This change helps a
hand full of shaders but also stops a CTS regression caused
by excess spilling after a series I'm working on to disable
more of the GLSL IR optimisation passes.
Shader-db results iris (BDW):
total instructions in shared programs:
17529759 ->
17529749 (<.01%)
instructions in affected programs: 15929 -> 15919 (-0.06%)
helped: 5
HURT: 2
helped stats (abs) min: 1 max: 5 x̄: 2.40 x̃: 2
helped stats (rel) min: 0.06% max: 0.15% x̄: 0.11% x̃: 0.12%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.06% max: 0.06% x̄: 0.06% x̃: 0.06%
95% mean confidence interval for instructions value: -3.34 0.49
95% mean confidence interval for instructions %-change: -0.14% 0.02%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs:
861109994 ->
861099681 (<.01%)
cycles in affected programs: 7027698 -> 7017385 (-0.15%)
helped: 95
HURT: 72
helped stats (abs) min: 1 max: 7995 x̄: 138.54 x̃: 9
helped stats (rel) min: <.01% max: 15.96% x̄: 0.54% x̃: 0.11%
HURT stats (abs) min: 1 max: 474 x̄: 39.56 x̃: 12
HURT stats (rel) min: <.01% max: 1.17% x̄: 0.20% x̃: 0.11%
95% mean confidence interval for cycles value: -159.05 35.54
95% mean confidence interval for cycles %-change: -0.45% 0.01%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 17606 -> 17605 (<.01%)
spills in affected programs: 323 -> 322 (-0.31%)
helped: 1
HURT: 0
total fills in shared programs: 22599 -> 22598 (<.01%)
fills in affected programs: 1348 -> 1347 (-0.07%)
helped: 1
HURT: 0
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14940>
David Heidelberg [Mon, 30 May 2022 11:04:20 +0000 (13:04 +0200)]
ci: traces: temporarily disable nheko trace
Disable nheko trace until apitrace gets fixed.
apitrace currently fails with this trace, when more than 1 run is
requested.
Upstream issue: https://github.com/apitrace/apitrace/issues/800
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16774>
Alyssa Rosenzweig [Fri, 27 May 2022 18:39:14 +0000 (14:39 -0400)]
pan/bi: Interpolate varyings at 16-bit
On Bifrost, we have a single "load float varying" instruction that controls the
bit size of the result, allowing us to fold a f2f16 into the load. However, the
larger benefit is that 16-bit varying loads are interpolated at 16-bit. Arm
claims that the varying unit has a 32-bit data path, allowing 16-bit varyings to
be interpolated in half the cycles from 32-bit. This change should therefore
improve performance for workloads that are varying units. This means we want to
be aggressive about 16-bit varying loads, even if it costs some extra f2f32
instructions.
glmark2 total score on Mali-G52 up from 1173fps to 1218fps with particular wins
in -brefract, -bshadow, -bjellyfish, and -bshading.
total instructions in shared programs: 2432246 -> 2423668 (-0.35%)
instructions in affected programs: 516056 -> 507478 (-1.66%)
helped: 3641
HURT: 432
helped stats (abs) min: 1.0 max: 12.0 x̄: 2.91 x̃: 2
helped stats (rel) min: 0.08% max: 54.55% x̄: 9.88% x̃: 5.71%
HURT stats (abs) min: 1.0 max: 42.0 x̄: 4.71 x̃: 4
HURT stats (rel) min: 0.23% max: 200.00% x̄: 12.58% x̃: 6.37%
95% mean confidence interval for instructions value: -2.21 -2.00
95% mean confidence interval for instructions %-change: -7.92% -7.07%
Instructions are helped.
total tuples in shared programs: 1941309 -> 1934647 (-0.34%)
tuples in affected programs: 353169 -> 346507 (-1.89%)
helped: 3233
HURT: 453
helped stats (abs) min: 1.0 max: 14.0 x̄: 2.46 x̃: 2
helped stats (rel) min: 0.12% max: 50.00% x̄: 9.90% x̃: 5.56%
HURT stats (abs) min: 1.0 max: 25.0 x̄: 2.85 x̃: 2
HURT stats (rel) min: 0.22% max: 150.00% x̄: 8.96% x̃: 5.26%
95% mean confidence interval for tuples value: -1.89 -1.72
95% mean confidence interval for tuples %-change: -8.01% -7.15%
Tuples are helped.
total clauses in shared programs: 357354 -> 356610 (-0.21%)
clauses in affected programs: 25794 -> 25050 (-2.88%)
helped: 994
HURT: 317
helped stats (abs) min: 1.0 max: 3.0 x̄: 1.16 x̃: 1
helped stats (rel) min: 1.49% max: 33.33% x̄: 10.78% x̃: 10.00%
HURT stats (abs) min: 1.0 max: 4.0 x̄: 1.31 x̃: 1
HURT stats (rel) min: 1.19% max: 50.00% x̄: 13.56% x̃: 8.33%
95% mean confidence interval for clauses value: -0.63 -0.50
95% mean confidence interval for clauses %-change: -5.63% -4.16%
Clauses are helped.
total cycles in shared programs: 167697.96 -> 167431.15 (-0.16%)
cycles in affected programs: 12638.29 -> 12371.48 (-2.11%)
helped: 2652
HURT: 350
helped stats (abs) min: 0.
04166399999999726 max: 0.75 x̄: 0.11 x̃: 0
helped stats (rel) min: 0.12% max: 100.00% x̄: 14.39% x̃: 5.04%
HURT stats (abs) min: 0.
041665999999999315 max: 0.
5833329999999997 x̄: 0.11 x̃: 0
HURT stats (rel) min: 0.00% max: 75.00% x̄: 7.90% x̃: 4.71%
95% mean confidence interval for cycles value: -0.09 -0.08
95% mean confidence interval for cycles %-change: -12.56% -11.02%
Cycles are helped.
total arith in shared programs: 74169.46 -> 73891.71 (-0.37%)
arith in affected programs: 13885.87 -> 13608.12 (-2.00%)
helped: 3215
HURT: 445
helped stats (abs) min: 0.
04166399999999726 max: 0.
5416680000000014 x̄: 0.10 x̃: 0
helped stats (rel) min: 0.12% max: 100.00% x̄: 14.16% x̃: 6.67%
HURT stats (abs) min: 0.
041665999999999315 max: 1.125 x̄: 0.12 x̃: 0
HURT stats (rel) min: 0.00% max: 100.00% x̄: 9.76% x̃: 5.49%
95% mean confidence interval for arith value: -0.08 -0.07
95% mean confidence interval for arith %-change: -11.91% -10.59%
Arith are helped.
total texture in shared programs: 11936 -> 11931 (-0.04%)
texture in affected programs: 20 -> 15 (-25.00%)
helped: 10
HURT: 0
helped stats (abs) min: 0.5 max: 0.5 x̄: 0.50 x̃: 0
helped stats (rel) min: 14.29% max: 100.00% x̄: 45.71% x̃: 33.33%
95% mean confidence interval for texture value: -0.50 -0.50
95% mean confidence interval for texture %-change: -73.16% -18.26%
Texture are helped.
total vary in shared programs: 4180.88 -> 3447.19 (-17.55%)
vary in affected programs: 2109.88 -> 1376.19 (-34.77%)
helped: 2202
HURT: 39
helped stats (abs) min: 0.0625 max: 1.4375 x̄: 0.34 x̃: 0
helped stats (rel) min: 2.38% max: 66.67% x̄: 40.43% x̃: 50.00%
HURT stats (abs) min: 0.125 max: 0.375 x̄: 0.26 x̃: 0
HURT stats (rel) min: 0.00% max: 300.00% x̄: 92.54% x̃: 23.08%
95% mean confidence interval for vary value: -0.34 -0.32
95% mean confidence interval for vary %-change: -39.22% -37.01%
Vary are helped.
total quadwords in shared programs: 1689664 -> 1684852 (-0.28%)
quadwords in affected programs: 265522 -> 260710 (-1.81%)
helped: 2864
HURT: 447
helped stats (abs) min: 1.0 max: 14.0 x̄: 2.10 x̃: 2
helped stats (rel) min: 0.15% max: 31.58% x̄: 6.05% x̃: 4.65%
HURT stats (abs) min: 1.0 max: 22.0 x̄: 2.67 x̃: 2
HURT stats (rel) min: 0.27% max: 38.46% x̄: 6.79% x̃: 4.55%
95% mean confidence interval for quadwords value: -1.54 -1.37
95% mean confidence interval for quadwords %-change: -4.55% -4.08%
Quadwords are helped.
total threads in shared programs: 53656 -> 53688 (0.06%)
threads in affected programs: 32 -> 64 (100.00%)
helped: 32
HURT: 0
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for threads value: 1.00 1.00
95% mean confidence interval for threads %-change: 100.00% 100.00%
Threads are helped.
total preloads in shared programs: 116212 -> 103476 (-10.96%)
preloads in affected programs: 45222 -> 32486 (-28.16%)
helped: 3022
HURT: 11
helped stats (abs) min: 1.0 max: 11.0 x̄: 4.23 x̃: 4
helped stats (rel) min: 7.14% max: 68.75% x̄: 30.39% x̃: 25.00%
HURT stats (abs) min: 2.0 max: 4.0 x̄: 3.45 x̃: 4
HURT stats (rel) min: 14.29% max: 50.00% x̄: 25.93% x̃: 25.00%
95% mean confidence interval for preloads value: -4.26 -4.14
95% mean confidence interval for preloads %-change: -30.68% -29.69%
Preloads are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Tested-by: Chris Healy cphealy@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16752>
Alyssa Rosenzweig [Mon, 30 May 2022 19:29:56 +0000 (15:29 -0400)]
pan/bi: Model Valhall source formats
LD_VAR_BUF instructions on Valhall take a source format, indicating the
in-memory format of the varying independent from the register format, which we
still model within the compiler for compatibility with Bifrost. (Prior to
Valhall, source format is specified in the attribute descriptor as a physical
pixel format.)
Model this information, allowing us to generate fp16 LD_VAR_BUF instructions
correctly on Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16752>
Alyssa Rosenzweig [Fri, 27 May 2022 19:32:59 +0000 (15:32 -0400)]
pan/bi: Make LD_VAR w=format instead of w=vecsize
Fixes a vector dimension validation failure in
dEQP-GLES3.functional.shaders.indexing.varying_array.vec4_static_write_dynamic_read
after we enable fp16 varyings.
No shader-db changes, as we don't yet support fp16 varyings.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16752>
Alyssa Rosenzweig [Mon, 30 May 2022 19:28:09 +0000 (15:28 -0400)]
pan/va: Fill in missing src_flat16 enum
Valhall gains(?) the ability to flatshade 16-bit varyings, this is indicated by
a particular source format.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16752>
Alyssa Rosenzweig [Fri, 27 May 2022 18:13:40 +0000 (14:13 -0400)]
pan/bi: Add VAR_TEX fusing unit test
As fusing VAR_TEX is an optimization, it's helpful to have unit tests since
functional tests won't check that the optimization triggers when expected.
Originally written when I was touching the VAR_TEX code. Those changes have
since been dropped by the unit test remains useful.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16752>
Konstantin Seurer [Sat, 28 May 2022 10:11:20 +0000 (12:11 +0200)]
radv: Use vk_buffer
Use vk_buffer as a base for radv_buffer and
replace manual handling of VK_WHOLE_SIZE with
vk_buffer_range.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16764>
Konstantin Seurer [Sat, 28 May 2022 09:34:11 +0000 (11:34 +0200)]
vulkan: Use the correct enum in vk_buffer
VkBufferCreateFlags is correct.
Fixes: f6ae21b ("vulkan: Add a base struct for buffers")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16764>
Matt Turner [Sun, 29 May 2022 18:25:37 +0000 (14:25 -0400)]
mesa: Drop dead #include "sparc/sparc.h"
sparc.h was removed in when the classic drivers were removed. It only
contained a prototype for _mesa_init_all_sparc_transform_asm() which
wasn't even called by context.c. Remove the #include to fix the build on
sparc.
Fixes:
e030d5ba8ac ("mesa: Delete libmesa_classic")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6425
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16765>
Rhys Perry [Wed, 11 May 2022 14:10:22 +0000 (15:10 +0100)]
aco/ra: fix usage of invalidated iterator
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
58bd9a379ef ("aco/ra: fix live-range splits of phi definitions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16454>
Alyssa Rosenzweig [Fri, 27 May 2022 15:36:01 +0000 (11:36 -0400)]
pan/bi: Don't allow spilling coverage mask writes
The register precolouring logic assumes that coverage masks are always in R60,
so spilling them causes incorrect results. We could do better. Fixes on Valhall:
dEQP-GLES3.functional.ubo.random.all_per_block_buffers.28
Fixes:
3df5446cbd4 ("pan/bi: Simplify register precolouring in the IR")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16748>
Alyssa Rosenzweig [Fri, 27 May 2022 13:06:31 +0000 (09:06 -0400)]
panfrost: Set allow_rotating_primitives
On Valhall, the driver should set this flag if the hardware may rotate
primitives. This happens if:
1. The rasterization of lines does not matter, AND
2. The provoking vertex does not matter.
The first condition we may satisfy by checking for LINES and the second by
checking for flat shading. Otherwise, we should set this flag to allow
optimizations. This may be more efficient for tiling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16748>
Alyssa Rosenzweig [Fri, 27 May 2022 12:46:46 +0000 (08:46 -0400)]
panfrost: Set overdraw_alpha[01] flags
These basically correspond to the alpha_zero_nop and alpha_one_store flags we
already compute and set. Except those flags don't exist on Valhall, so these
need to be used instead (on Bifrost, in addition .. unclear why the duplication
on Bifrost).
Set these flags when we can. Ostensibly this is for performance (neglible
improvement on glmark2 score), but mostly I want to get us using the hardware
optimally.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16748>
Alyssa Rosenzweig [Wed, 25 May 2022 21:29:17 +0000 (17:29 -0400)]
panfrost: Allow FPK on Valhall
Reuse the logic from Bifrost for a performance win.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16748>
Samuel Pitoiset [Mon, 23 May 2022 09:33:30 +0000 (11:33 +0200)]
radv: init states from VkPipelineFragmentShadingRateState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
Samuel Pitoiset [Fri, 20 May 2022 13:44:57 +0000 (15:44 +0200)]
radv: init states from VkPipelineDiscardRectangleState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
Samuel Pitoiset [Fri, 20 May 2022 13:25:12 +0000 (15:25 +0200)]
radv: init states from VkAttachmentSampleCountInfo at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
Samuel Pitoiset [Fri, 20 May 2022 11:44:42 +0000 (13:44 +0200)]
radv: init states from pColorBlendState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
Samuel Pitoiset [Fri, 20 May 2022 09:56:11 +0000 (11:56 +0200)]
radv: use AMD values for computing blend related state
This will allow to translate the function and factors earlier.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
Samuel Pitoiset [Fri, 20 May 2022 06:25:13 +0000 (08:25 +0200)]
radv: init states from VkPipelineRenderingCreateInfo at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
Samuel Pitoiset [Wed, 18 May 2022 07:22:59 +0000 (09:22 +0200)]
radv: init states from pDepthStencilState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
Samuel Pitoiset [Thu, 19 May 2022 14:04:17 +0000 (16:04 +0200)]
radv: init states from pMultisampleState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
Samuel Pitoiset [Fri, 20 May 2022 14:07:13 +0000 (16:07 +0200)]
radv: copy viewport/scissor when initializing radv_viewport_info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
Marcin Ślusarz [Tue, 24 May 2022 10:53:53 +0000 (12:53 +0200)]
anv: remove invalid copy/pasted comment
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16773>
Marcin Ślusarz [Tue, 24 May 2022 10:49:14 +0000 (12:49 +0200)]
anv: remove redundant code calculating dynamic states mask
pipeline->dynamic_states is already set by anv_graphics_pipeline_init
since
231651fd89fb007610568b3ca76837253e7683ff.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16773>
David Heidelberg [Mon, 30 May 2022 07:48:01 +0000 (09:48 +0200)]
ci/iris: skqp: remove flaking atlastext for TGL (gl version)
gles version of atlastext was already removed due to same behavior
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16772>
Tatsuyuki Ishi [Mon, 30 May 2022 05:40:37 +0000 (14:40 +0900)]
radv/ci: skip image.sample_texture.*_compressed_format*
These tests are flaky due to missing barriers, exposed by
211db6d3336
("radv: Fix redundant subpass barriers due to erroneous comparison").
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16762>
Tatsuyuki Ishi [Sat, 28 May 2022 02:11:59 +0000 (11:11 +0900)]
radv/ci: Move transient_attachment_bit from fail to skip list
These tests are flaky and should not be treated as expected-fail.
This also removes the duplicates from the fail list which was breaking CTS
runner.
Fixes:
cd14431b8ca ("radv/ci: skip dEQP-VK.fragment_operations.transient_attachment_bit")
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16762>
Jesse Natalie [Wed, 18 May 2022 19:42:04 +0000 (12:42 -0700)]
microsoft/compiler: Fixup sampler derefs in tex instrs that don't *need* samplers
Sometimes you can end up with tex instructions that have sampler deref srcs, even though
they don't need them, e.g. a txs. In this case, still fix up those derefs in the sampler
splitting pass rather than leaving them pointing to a typed sampler.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16639>
Konstantin Seurer [Thu, 26 May 2022 14:38:56 +0000 (16:38 +0200)]
radv: Ignore transformOffset if transformData is 0
There is also a hypothetical scenario where
transformData is 0 and transformOffset is not 0
and we end up reading from transformOffset because
transform_addr is not 0.
VkAccelerationStructureBuildRangeInfoKHR spec:
If VkAccelerationStructureGeometryTrianglesDataKHR::transformData is not NULL, a single VkTransformMatrixKHR structure is consumed from VkAccelerationStructureGeometryTrianglesDataKHR::transformData, at an offset of transformOffset. This matrix describes a transformation from the space in which the vertices for all triangles in this geometry are described to the space in which the acceleration structure is defined.
Which I think means, that we should ignore
transformOffset if transformData is NULL.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16719>
Konstantin Seurer [Thu, 26 May 2022 11:24:45 +0000 (13:24 +0200)]
radv: Fix handling of primitiveOffset
VkAccelerationStructureBuildRangeInfoKHR spec:
If the geometry uses indices, primitiveCount × 3 indices are consumed from VkAccelerationStructureGeometryTrianglesDataKHR::indexData, starting at an offset of primitiveOffset. The value of firstVertex is added to the index values before fetching vertices.
If the geometry does not use indices, primitiveCount × 3 vertices are consumed from VkAccelerationStructureGeometryTrianglesDataKHR::vertexData, starting at an offset of primitiveOffset + VkAccelerationStructureGeometryTrianglesDataKHR::vertexStride × firstVertex.
Meaning: We always add firstVertex * vertexStride
to the vertex address and add primitiveOffset
either to the vertex address or the index address,
depending on wether indices are used.
Also add missing handling with instances.
Fixes: 0dad88b ("radv: Implement device-side BVH building.")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16719>
SureshGuttula [Fri, 27 May 2022 10:49:42 +0000 (16:19 +0530)]
Revert "radeonsi: Set display_remote for non-refernced frames"
This reverts commit
ef76b83633dc34eefed11f295cb3185c3991fecd.
Reason for revert: This only helps in using I MBs.To further
fix in dpb , reverting this.
Fix added : https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16745
Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16744>
Jesse Natalie [Fri, 27 May 2022 23:31:29 +0000 (16:31 -0700)]
d3d12: Fix forward decl for sw_winsys
Closes part of: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4099
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16760>
SureshGuttula [Fri, 27 May 2022 11:00:52 +0000 (16:30 +0530)]
radeonsi/vcn : update enc->dpb ref_use for index 0
Currently dpb_enc referneces not updated properly when index 0, as
we are skipping clearing that ref.
This patch will fix this for index 0. So that when ever we set
non_referenced flag, that is not used as ref and not pushed to DPB.
This is helping in SVC encoding.
Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16745>
Lionel Landwerlin [Fri, 27 May 2022 08:27:55 +0000 (11:27 +0300)]
anv: move internal RT shaders to the internal cache
Those shaders are just like the blorp ones.
v2: Use a single internal cache for blorp/RT (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
7f1e82306c9b ("anv: Switch to the new common pipeline cache")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16741>
Jason Ekstrand [Thu, 19 May 2022 14:20:33 +0000 (09:20 -0500)]
panvk: Use the vk_buffer base struct
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16607>
Jason Ekstrand [Thu, 19 May 2022 14:00:30 +0000 (09:00 -0500)]
anv: Use the base vk_buffer struct
This mostly gets us the vk_buffer_range() helper but may be useful in
the future.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16607>
Jason Ekstrand [Thu, 19 May 2022 13:41:21 +0000 (08:41 -0500)]
vulkan: Add a base struct for buffers
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16607>
Vinson Lee [Tue, 24 May 2022 00:02:20 +0000 (17:02 -0700)]
d3d12: Initialize d3d12_video_encoder_bitstream member m_uiOffset.
Fix defect reported by Coverity Scan.
Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member m_uiOffset is not initialized in
this constructor nor in any functions that it calls.
Fixes:
b171a6baa21 ("d3d12: Add video encode implementation of pipe_video_codec")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16682>
Jason Ekstrand [Fri, 7 Jun 2019 23:17:36 +0000 (18:17 -0500)]
intel: Only set VectorMaskEnable when needed
For cases with lots of very small primitives, this may improve
performance because we're not executing those dead channels all the
time.
Shader-db reports no instruction or cycle-count changes. However, by
hacking up the driver to report when this optimization triggers, it
appears to affect about 10% of shader-db.
v2 (Kenneth Graunke): Always enable VMask prior to XeHP for now,
because using VMask on those platforms allows us to perform the
eliminate_find_live_channel() optimization. However, XeHP doesn't
seem to have packed fragment shader dispatch, so we lose that
optimization regardless, and there's no reason not to avoid vmask.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1054>
Erico Nunes [Fri, 27 May 2022 18:54:40 +0000 (20:54 +0200)]
egl: Fix DETECT_OS macro usage
As described in src/util/detect_os.h, the DETECT_OS macros are always
defined to a 0 or 1 value, and they should be used with #if rather
than #ifdef.
Commit
54b7227f158 accidentally disabled those extensions on all
platforms, so enable them again.
Fixes:
54b7227f158 ("egl/wgl: On win32, there is no support for EGL_EXT_device and EGL_EXT_platform_device")
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16751>
Jason Ekstrand [Fri, 13 May 2022 22:09:52 +0000 (17:09 -0500)]
anv: Don't disable the fragment shader if XFB is enabled
It turns out that we need a fragment shader for streamout. Whh? From
Lionel's reading of simulator sources, it seems the streamout unit is
looking at enabled next stages. It'll generate output to the clipper in
the following cases :
- 3DSTATE_STREAMOUT::ForceRendering = ON
- PS enabled
- Stencil test enabled
- depth test enabled
- depth write enabled
- some other depth/hiz clear condition
Forcing rendering without a PS seems like a recipe for hangs so it's
probably better to just enable the PS in this case.
Fixes:
36ee2fd61c8f ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
Jason Ekstrand [Fri, 13 May 2022 22:06:50 +0000 (17:06 -0500)]
anv: Handle the null FS optimization after compiling shaders
Actually compile and cache the no-op fragment shader but remove it from
the pipeline if we determine it's a no-op. This way we always have it
even if it's not strictly needed.
Fixes:
36ee2fd61c8f ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
Jason Ekstrand [Fri, 13 May 2022 22:01:06 +0000 (17:01 -0500)]
anv: Drop alpha_to_coverage from the NULL FS optimization
Starting with Ivy Bridge, we implement alpha-to-coverage by writting
gl_SampleMask with a pattern based on alpha. This will show up in
wm_prog_data::uses_omask so we don't need to look at the key.
Fixes:
36ee2fd61c8f ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
Jason Ekstrand [Fri, 13 May 2022 21:54:26 +0000 (16:54 -0500)]
intel/fs: Copy color_outputs_valid into wm_prog_data
Fixes:
36ee2fd61c8f ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
Jason Ekstrand [Fri, 13 May 2022 21:47:35 +0000 (16:47 -0500)]
intel/fs: Drop fs_visitor::emit_alpha_to_coverage_workaround()
It no longer exists.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
Mike Blumenkrantz [Sat, 21 May 2022 22:53:26 +0000 (18:53 -0400)]
vtn: assert that composite members have the same bit size as the result
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16667>
Mike Blumenkrantz [Sat, 21 May 2022 22:53:07 +0000 (18:53 -0400)]
vtn: assert that vector shuffle indices are in-bounds
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16667>
Alyssa Rosenzweig [Thu, 6 Jan 2022 21:43:07 +0000 (16:43 -0500)]
pan/bi: Test CMP result_type optimization
Add unit tests ensuring the optimization applies in all the cases we care about,
as functional integration tests (CTS and Piglit) won't test this. Also add unit
tests for a few cases where we specifically cannot fuse, in case these cases are
missed by the tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16725>
Alyssa Rosenzweig [Thu, 6 Jan 2022 22:12:56 +0000 (17:12 -0500)]
pan/bi: Fuse result types
In NIR, comparison instructions always produce 0/~0 results. For other result
types, a separate b2f32 or b2i32 instruction is used to transform the result.
However, Mali's comparison instructions have modifiers for these alternate
result types, so we can implement expressions like int(a < b) and float(a ==
b) in single instruction. Add a peephole optimization to fuse comparisons
with result type transformations.
Results on Mali-G52:
total instructions in shared programs: 2439696 -> 2434339 (-0.22%)
instructions in affected programs: 418703 -> 413346 (-1.28%)
helped: 1630
HURT: 0
helped stats (abs) min: 1.0 max: 28.0 x̄: 3.29 x̃: 2
helped stats (rel) min: 0.11% max: 19.35% x̄: 1.64% x̃: 1.39%
95% mean confidence interval for instructions value: -3.44 -3.13
95% mean confidence interval for instructions %-change: -1.72% -1.56%
Instructions are helped.
total tuples in shared programs: 1946581 -> 1943005 (-0.18%)
tuples in affected programs: 251742 -> 248166 (-1.42%)
helped: 1113
HURT: 11
helped stats (abs) min: 1.0 max: 32.0 x̄: 3.23 x̃: 2
helped stats (rel) min: 0.17% max: 15.38% x̄: 1.80% x̃: 1.38%
HURT stats (abs) min: 1.0 max: 2.0 x̄: 1.45 x̃: 1
HURT stats (rel) min: 0.21% max: 3.12% x̄: 1.23% x̃: 0.89%
95% mean confidence interval for tuples value: -3.35 -3.01
95% mean confidence interval for tuples %-change: -1.88% -1.66%
Tuples are helped.
total clauses in shared programs: 357791 -> 357349 (-0.12%)
clauses in affected programs: 15879 -> 15437 (-2.78%)
helped: 371
HURT: 3
helped stats (abs) min: 1.0 max: 8.0 x̄: 1.20 x̃: 1
helped stats (rel) min: 0.80% max: 33.33% x̄: 3.85% x̃: 2.17%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 2.94% max: 5.26% x̄: 4.49% x̃: 5.26%
95% mean confidence interval for clauses value: -1.27 -1.09
95% mean confidence interval for clauses %-change: -4.21% -3.36%
Clauses are helped.
total cycles in shared programs: 167922.04 -> 167810.71 (-0.07%)
cycles in affected programs: 6772.08 -> 6660.75 (-1.64%)
helped: 655
HURT: 12
helped stats (abs) min: 0.
041665999999999315 max: 1.
3333319999999986 x̄: 0.17 x̃: 0
helped stats (rel) min: 0.18% max: 20.00% x̄: 2.02% x̃: 1.60%
HURT stats (abs) min: 0.
041665999999999315 max: 0.125 x̄: 0.05 x̃: 0
HURT stats (rel) min: 0.21% max: 3.80% x̄: 1.23% x̃: 0.88%
95% mean confidence interval for cycles value: -0.18 -0.16
95% mean confidence interval for cycles %-change: -2.10% -1.81%
Cycles are helped.
total arith in shared programs: 74393.17 -> 74243.08 (-0.20%)
arith in affected programs: 10157.50 -> 10007.42 (-1.48%)
helped: 1129
HURT: 12
helped stats (abs) min: 0.
041665999999999315 max: 1.
3333319999999986 x̄: 0.13 x̃: 0
helped stats (rel) min: 0.18% max: 50.00% x̄: 1.94% x̃: 1.40%
HURT stats (abs) min: 0.
041665999999999315 max: 0.125 x̄: 0.05 x̃: 0
HURT stats (rel) min: 0.21% max: 3.80% x̄: 1.23% x̃: 0.88%
95% mean confidence interval for arith value: -0.14 -0.12
95% mean confidence interval for arith %-change: -2.06% -1.76%
Arith are helped.
total quadwords in shared programs: 1692019 -> 1688164 (-0.23%)
quadwords in affected programs: 216669 -> 212814 (-1.78%)
helped: 1148
HURT: 11
helped stats (abs) min: 1.0 max: 41.0 x̄: 3.37 x̃: 2
helped stats (rel) min: 0.17% max: 17.24% x̄: 2.25% x̃: 1.73%
HURT stats (abs) min: 1.0 max: 2.0 x̄: 1.09 x̃: 1
HURT stats (rel) min: 0.60% max: 1.32% x̄: 0.85% x̃: 0.83%
95% mean confidence interval for quadwords value: -3.49 -3.16
95% mean confidence interval for quadwords %-change: -2.33% -2.10%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16725>
Timur Kristóf [Thu, 26 May 2022 17:03:19 +0000 (19:03 +0200)]
nir: Keep track of cross-invocation mesh shader output access.
On some implementations eg. AMD RDNA2 the driver can generate a
more optimal code path knowing whether outputs are indexed using the
local invocation index or not.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16736>
Tatsuyuki Ishi [Thu, 26 May 2022 10:39:03 +0000 (19:39 +0900)]
radv/ci: skip dEQP-VK.fragment_operations.transient_attachment_bit
Until the CTS bug is fixed.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16663>
Tatsuyuki Ishi [Mon, 23 May 2022 10:14:25 +0000 (19:14 +0900)]
radv: Fix redundant subpass barriers due to erroneous comparison
We accidentally compared the stencil layout to the color/depth layout.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16663>
Yogesh Mohan Marimuthu [Sat, 21 May 2022 17:34:21 +0000 (23:04 +0530)]
vulkan/wsi: fix extra free if buffer_blit_queue
In wsi_destroy_image(), if buffer_blit_queue then
do not call extra free. This will fix assert in
debug release and accessing out of allocated memory.
Fixes:
7bd5aa111cf
("vulkan/wsi: add a private transfer pool to exec the DRI_PRIME blit")
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16649>
Timur Kristóf [Mon, 23 May 2022 15:00:44 +0000 (17:00 +0200)]
radv: Add mesh and task stage names to pipeline executable properties.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16712>
Timur Kristóf [Thu, 26 May 2022 11:20:36 +0000 (13:20 +0200)]
nir: Add common task shader lowering to make the backend's job easier.
1. Lowers NV_mesh_shader TASK_COUNT output to launch_mesh_workgroups.
2. Removes all code after launch_mesh_workgroups, enforcing the
fact that it's a terminating instruction.
3. Ensures that task shaders always have at least one
launch_mesh_workgroups instruction, so the backend doesn't
need to implement a special case when the shader doesn't have it.
4. Optionally, implements task_payload using shared memory when
task_payload atomics are used.
This is useful when the backend is otherwise not capable of
handling the same atomic features as it can for shared memory.
If this is used, the backend only has to implement the basic
load/store operations for task_payload.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16720>
Timur Kristóf [Thu, 26 May 2022 11:24:58 +0000 (13:24 +0200)]
nir: Add new launch_mesh_workgroups intrinsic.
The new intrinsic launches mesh shader workgroups
from a task shader, with explicit task_payload.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16720>
David Heidelberg [Wed, 18 May 2022 19:01:15 +0000 (21:01 +0200)]
ci/panfrost: add RoR and Nheko traces
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16633>
David Heidelberg [Thu, 19 May 2022 17:57:40 +0000 (19:57 +0200)]
ci/virgl: traces: add RoR and Nheko traces
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16633>
David Heidelberg [Fri, 20 May 2022 11:44:17 +0000 (13:44 +0200)]
ci/radeonsi: add RoR and Nheko traces
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16633>