radeonsi: don't clamp z_samples to fix Unreal Tournament 99

Fixes: a29218b5 - radeonsi/gfx11: always set MSAA_NUM_SAMPLES=0 for DCC_DECOMPRESS
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8261

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: query the per-SIMD VGPR counts from the kernel, don't hardcode them

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: rename esgs_itemsize -> esgs_vertex_stride

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: correct and clean up obsolete vs_state_bits comments

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: always add 1 to lshs_vertex_stride now that LS_OUT_PATCH_SIZE is gone

LS_OUT_PATCH_SIZE limited the maximum value.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: remove unused VS_STATE_LS_OUT_PATCH_SIZE

This became unused when we switched to nir_lower_hs_inputs_to_mem.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: remove a gfx11 check in si_shader_gs (legacy GS)

Gfx11 doesn't support legacy GS.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: reformat emit_cb_render_state, create_blend_state, create_rs_state

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: remove returns from si_emit_global_shader_pointers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: replace SI_BIG_ENDIAN with UTIL_ARCH_BIG_ENDIAN

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd/registers: unify VRS combiner definition names between gfx103 and gfx11

use gfx11 names

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd,radeonsi: remove unused LLVM functions

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: disable Smart Access Memory because CPU access has large overhead

It will be remove completely in the next commit.

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8176

Cc: mesa-stable
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: replace si_screen::has_out_of_order_rast with the radeon_info field

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi/gfx11: ignore alpha_is_on_msb because the hw ignores it

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: set PA_SU_VTX_CNTL consecutively with PA_CL_GB_VERT_CLIP_ADJ

because they are all next to each other.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: use SPI_SHADER_USER_DATA_HS_0 definition instead of LS_0

The value is the same, but LS_0 is for gfx9 only, and HS_0 is for everything
except gfx9.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: remove no-op setting of THDS_PER_SUBGRP

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: change si_shader::ctx_reg to a nameless union for better readability

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: move a few DB_SHADER_CONTROL states into si_shader_ps

They can be set si_shader_ps.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi/gfx11: set CB_COLORi_INFO.MAX_COMP_FRAG on GFX1103_R2

Fixes: caa09f66ae4 - amd: add chip identification for gfx1100-1103

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi/gfx11: don't set non-existent VGT_STRMOUT_BUFFER_CONFIG

Fixes: 9fecac091f3 - radeonsi/gfx11: scattered register deltas

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi/gfx11: fix the CU_EN clear mask for RSRC4_GS

Fixes: 9fecac091f3 - radeonsi/gfx11: scattered register deltas

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: bump AMD_MAX_SE and change the CU mask type to 16 bits

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: add missing gfx11 register definitions

Fixes: caa09f66ae4 - amd: add chip identification for gfx1100-1103

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: fix LOD_BIAS on gfx6-9 and adjust the lod bias CAP

Fixes: e673bb4ae44 - amd,util: fix how lod bias is converted to fixed-point

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: fix COMPAT_MODE on gfx8-9

It was set in the wrong dword.

Fixes: e673bb4ae44 ("amd,util: fix how lod bias is converted to fixed-point")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

Revert "radeonsi/ci: Update stoney test expectations"

This reverts commit 53cc5092885d5d8dd01a66302e2f762f5b00e045.

This MR fixes it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

spirv: Always emit deref_buffer_array_length intrinsics

All the drivers have been converted to setting this option now except
imagination and they don't support SSBOs yet.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3993
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

v3dv: Set spirv_options::use_deref_buffer_array_length

It'll get lowered to get_ssbo_size by nir_lower_explicit_io() so the
driver should never notice this change.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

lavapipe: Set spirv_options::use_deref_buffer_array_length

It'll get lowered to get_ssbo_size by nir_lower_explicit_io() so the
driver should never notice this change.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

turnip: Set spirv_options::use_deref_buffer_array_length

It'll get lowered to get_ssbo_size by nir_lower_explicit_io() so the
driver should never notice this change.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

panvk: Drop our manual SSBO size handling

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

hasvk: Drop our manual SSBO size handling

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

anv: Drop our manual SSBO size handling

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

nir/lower_io: Handle buffer_array_length for more address modes

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

frontend/va: Remove duplicate code in format support checking/reporting.

In config.c there are multiple copies of the code checking for VA_FORMAT_RT_*, this can lead
to confusion and is hard to maintain without knowing to change the code in all the places.

This commit extracts out the duplicated code into a function that checks format support
for a given profile and entrypoint, then this function is called from several places that
had the copies of this code in vlVaCreateConfig/vlVaGetConfigAttributes.

Please also note that after this change, all entrypoints/profiles will be checked for all
formats in the pipe_screen: YUV420/YUV420_10/YUV422/RGB32/YUV400/YUV444

Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21466>

frontend/va: Add format support checks for VA_RT_FORMAT_* in VaCreateConfig/VaGetConfigAttributes

Before this change some formats like YUV420, YUV422 and RGB32 are hardcoded as supported
in VaCreateConfig/VaGetConfigAttributes. This is not always the case, different gallium
drivers and hardware will support different formats. The frontend should delegate the support
check call by using the is_video_format_supported(...) function from pipe_screen.

Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21466>

lavapipe, nir: Fix wrong array index scaling in nir_collect_src_uniforms

The scaling needs to be ubo * MAX_INLINABLE_UNIFORMS, not
ubo * PIPE_MAX_CONSTANT_BUFFERS, otherwise accesses beyond buffer size
will result for ubo >= 4 (and we'd also access the wrong values later
for other non-zero ubo indices).

Fixes: a7696a4d98bc ("lavapipe: Fix bad array index scale factor in lvp_inline_uniforms pass")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21506>

r600/sfn: Fix readport cylce map

This is currently of no consequence, because the bank swizzle
codes are only used to check legal ALU group configuration
and the bank swizzles are not yet allocated to the instruictions
here.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21516>

r600/sfn: be more conservative with channel use in multi-slot ops

The current approach to check the bank swizzle doesn't allow to
re-evaluate bank-swizzle for instructions that where emitted
earlier, so we might end up with impossile constellations when we
allow three uses of the same channel

Fixes: edabd5cd8425
  r600/sfn: check used channels when evaluating allowed mask

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8350

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21516>

radv: Use indirect header filling for compact builds

Sets the accel struct size fields to the correct values which should
allow for more compaction.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv/bvh: Add a shader for filling the header

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv/bvh: Move the size header field up

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv: Move the geometry infos before the BVH

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv: Use compact encoding

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv/bvh: Implement compact encoding

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv: Add a build config for compact builds

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv/bvh/encoder: Move dst_node initialization into the loop

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv/bvh/encode: Introduce is_root_node

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv/bvh/encode: Move bvh_offset NULL check to the top of the loop

NULL nodes don't have to be encoded and they also don't carry over any
information to their children.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv/bvh: Replace is_final_tree with bvh_offset

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

radv/bvh/encode: Use the node type for identifying internal nodes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>

freedreno: Add A2xx REG_A2XX_RBBM_PM_OVERRIDE2 bitfields

Required for good-looking kernel code

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21480>

freedreno: Add A2xx perf counter reg values

Required for good-looking kernel code

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[rob: fixup CI expectations]

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21480>

pvr: Remove component_alignment

We don't support output register subdivision so no need to keep
track of how many bytes have been allocated within the output regs.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21386>

pvr: Remove unused msaa_mode field

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21386>

pvr: Setup SPM EOT state

On entering SPM we need to store the tile data for the current
render into the scratch buffer so we need to setup an EOT program
to do so.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21386>

pvr: Move PBE START_POS into csb enum helpers header

This commit adds 'pvr_pbestate_source_pos()' and moves
`enum pvr_pbe_source_start_pos` into pvr_csb_enum_helpers.h .
The enum will be needed in other files in the commits following.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21386>

radv: advertise VK_EXT_image_sliced_view_of_3d on GFX10+

Pass dEQP-VK.pipeline.monolithic.sliced_view_of_3d_image.* on NAVI21.

Looks like older generations can't support it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21359>

radv: implement VK_EXT_image_sliced_view_of_3d on GFX10+

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21359>

ac/nir: add resinfo lowering for sliced storage 3D views

The first layer isn't necessarily 0 and depth shouldn't be minified.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21359>

pvr: Add support for blend constants.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21388>

util/process_test: make the error variable static

Make the `error` variable static to prevent a clash with
the glibc error() function when LTO is used.

Fixes the LTO build.
Otherwise, it'll fail in the linking phase with a conflict:
```
[411/2321] Linking target src/util/process_test
FAILED: src/util/process_test
c++  -o src/util/process_test src/util/process_test.p/tests_process_test.c.o -flto -Wl,--as-needed -Wl,--no-undefined -Wl,--fatal-warnings -Wl,--start-group src/util/libmesa_util.a src/util/format/libmesa_format.a src/util/libmesa_util_sse41.a src/c11/impl/libmesa_util_c11.a subprojects/perfetto/libperfetto.a /usr/lib/x86_64-linux-gnu/libz.so -pthread -lm -ldl /usr/lib/x86_64-linux-gnu/libunwind.so -Wl,--end-group
mold: error: symbol type mismatch: error
>>> defined in /tmp/process_test.SLc9I6.ltrans0.ltrans.o as STT_OBJECT
>>> defined in /lib/x86_64-linux-gnu/libc.so.6 as STT_FUNC
```

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21511>

pvr: Add encodings for index registers

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Amend definitions for ST and IDF

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add late op lowering pass and conditional execution

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for MOVC

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add basic support for manual instruction grouping

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for TST

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add branch support

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for ST

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for IDF

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for generating NOP program

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for generating per-job EOT program

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Fix descriptor set address calculation

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Register allocation improvements

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for WOP

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for emitpix

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for validating modifier combos

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for sample instructions

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add support for fitr.pixel

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Amend subarray ownership code

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

pvr: Add NIR pass to lower vars to SSA

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21474>

anv: Move WA MEDIA_VFE_STATE after stalling PIPE_CONTROL

Fixes: bc612536 ("anv: Emit a dummy MEDIA_VFE_STATE before switching from GPGPU to 3D")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6172
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21472>

mesa: Report GL_SHADER_BINARY_FORMAT_SPIR_V as supported

GL_ARB_gl_spirv introduced it, but its corresponding format was never listed in GL_SHADER_BINARY_FORMATS.

Fixes: 5bc03d25 ("mesa: implement SPIR-V loading in glShaderBinary")
Closes: #7644
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19559>

radeonsi: fix incorrect vgpr indices in the ps_prolog

In monolithic PS shaders, we need to account for PERSP_PULL_MODEL even
if we don't use it; si_get_ps_prolog_key already does the same thing
to determine color_interp_vgpr_index.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8280
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21483>

r300: simplify KILL transformation

We had some special cases before when we could actually get some IFs on
R300 with VDPAU. Now that VDPAU is gone and everything goes through
ntt, we don't have to worry anymore. Remove the complicated logic and
just always transform KILL into KIL none.-1

No shader-db change on RV530 or RV370.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21503>

ci/zink: Add a glx flake on anv

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21366>

ci: Fix stage of etnaviv manual runs.

Fixes: f6c06ef2f66a ("ci: Add manual rules variations to disable irrelevant driver jobs.")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21366>

ci/hasvk: Add a synchronization flake.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21366>

ci/zink+turnip: Disable flaky minetest trace.

random 1-pixel changes sometimes.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21366>

ci/turnip: Drop the #8219 xfail.

It hasn't showed up in the last couple runs, the other test is no longer
showing up in the caselist so the fail isn't triggered.  Bug is still
there, though.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21366>

ci/freedreno: Drop a530 piglit_gl coverage.

It hasn't worked in a long time -- the board gets wedged 20 minutes in and
then we reboot it and try again until failure.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21366>

ci/etnaviv: Drop one more gc7000 xfail.

Looks like I missed it in the last full-run update.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21366>

anv: Handle all fields in VkAccelerationStructureBuildRangeInfoKHR

Add handling of primitiveOffset and firstVertex.

Fixes: f3ddfd81 ("anv: Build BVHs on the GPU with GRL")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8296
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21342>

spirv: Implement SPV_KHR_subgroup_rotate

Map SpvOpGroupNonUniformRotateKHR to nir_intrinsic_rotate.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19797>

nir/lower_subgroups: Add option lower_rotate_to_shuffle

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19797>

nir: Add nir_intrinsic_rotate

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19797>

r300: drop VDPAU support

There is no UVD and the mpeg2 shader-based decoding is broken and doesn't
lead to CPU savings anyway. VDPAU output works, but there is no real
benefit so just disable VDPAU altogether so we can clean the backend a
bit and also open a way to potentially drop the mpeg2 deconding altogether
from the fronted.

Acked-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20524>