Xiang, Haihao [Wed, 28 Nov 2012 02:19:11 +0000 (10:19 +0800)]
Update QM/FQM matrices for MPEG-2 encoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 27 Nov 2012 08:13:18 +0000 (16:13 +0800)]
No emulation bytes for MPEG-2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 27 Nov 2012 08:08:26 +0000 (16:08 +0800)]
Internal flag for the coded buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 27 Nov 2012 07:49:24 +0000 (15:49 +0800)]
rename I965_CODEDBUFFER_SIZE
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 23 Nov 2012 08:49:51 +0000 (16:49 +0800)]
Insert some redunrant data around a slice
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 23 Nov 2012 08:30:40 +0000 (16:30 +0800)]
Setup MFC pipeline for MPEG-2 encoding on Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 22 Nov 2012 01:37:18 +0000 (09:37 +0800)]
Explicitly clarify features
Also simplify some MACROs
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li,Xiaowei [Tue, 16 Oct 2012 21:43:39 +0000 (05:43 +0800)]
VPP: Add video sharpening processing feature on HSW
Video sharpening feature is implemented based on media
shared function pipeline, Y component of NV12 surface
will be sharpened.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li, Xiaowei A [Tue, 27 Nov 2012 02:28:41 +0000 (10:28 +0800)]
Fix H264 YUV400 surface render issue
All decoded frame are considered as NV12 format in driver's,
for YUV400 format senerios, we need set the chroma component
of NV12 to a constant value(0x80), otherwise the converted ARGB
from NV12 format is not correct and cause render issue.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li, Xiaowei A [Fri, 14 Dec 2012 02:05:43 +0000 (10:05 +0800)]
vc1: fix bitplane buffer size(HSW)
This fixes buffer overflow in the newly allocated Gen buffer
that holds VC-1 bitplanes.
Signed-off-by: Li,Xiaowei <xiaowei.a.li@intel.com>
Gwenole Beauchesne [Thu, 2 Feb 2012 13:42:11 +0000 (14:42 +0100)]
vc1: fix bitplane buffer size (SNB, IVB).
This fixes buffer overflow in the newly allocated Gen buffer that holds
VC-1 bitplanes.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Li,Xiaowei [Tue, 27 Nov 2012 01:08:29 +0000 (09:08 +0800)]
Render: Add four subpicture support
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li,Xiaowei [Fri, 23 Nov 2012 07:24:26 +0000 (15:24 +0800)]
Render: Add AI88/IA88 surface foramt support for subpicture
Signed off by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li,Xiaowei [Fri, 23 Nov 2012 03:13:48 +0000 (11:13 +0800)]
Render: Add global alpha support for subpicture
Signed-off-by: Li Xiaowei A <xiaowei.a.li@intel.com>
Zhao Yakui [Thu, 13 Dec 2012 01:24:27 +0000 (09:24 +0800)]
Feed MFC PAK with correct MV of VME output on haswell
This is helpful to improve the video compress rate of H264 encoding.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Mon, 10 Dec 2012 08:29:37 +0000 (16:29 +0800)]
Adjust the mode/mv cost for VME parameter based on QP for HSW
Currently it will use the same mode/mv cost regardless of QP during VME
prediction, which causes that we get the same VME prediction. It is better
that we get the different VME prediction mode based on QP, which can be
adopted by using mode/mv cost.
Now it is only applied on HSW.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Mon, 10 Dec 2012 08:29:37 +0000 (16:29 +0800)]
Add the support of the chroma intra prediction on Haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Mon, 10 Dec 2012 08:29:36 +0000 (16:29 +0800)]
Fix the corrupted macroblock for AVC encoding on HSW
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 7 Dec 2012 02:21:09 +0000 (10:21 +0800)]
Add CSC conversion between RGBX and NV12 for HSW by using AVS shader
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 7 Dec 2012 02:21:09 +0000 (10:21 +0800)]
Optimize the sampler 8x8 coefficients for AVS shader
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 7 Dec 2012 02:21:09 +0000 (10:21 +0800)]
Add the csc conversion from RGBX to NV12 on Ivy
It also applies when the source type is BGRX.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 7 Dec 2012 02:21:09 +0000 (10:21 +0800)]
Add CSC conversion from NV12 to RGBX for VPP on Ivy
It also applies to the conversion from NV12 to BGRX.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Joe Konno [Tue, 20 Nov 2012 15:42:27 +0000 (07:42 -0800)]
configure: add missing dependency to libm.
Build broke when trying to compile with expressive debug CFLAGS (-g3).
This was root-caused to the lack of the "-lm" linker flag. By adding a
simple autoconf check we ensure that libm is linked.
More specifically, recent VEBOX changes depend on cos() and sin() math
functions.
Signed-off-by: Joe Konno <joe.konno@intel.com>
(cherry picked from commit
eb39abb70886d9277cf7d5114125cb7b22e7c362)
Rob Bradford [Fri, 19 Oct 2012 17:49:56 +0000 (18:49 +0100)]
wayland: port to 1.0 protocol.
Previously some of the functions that this code relied upon were exported as
symbols from the wayland-client .so. However those are now autogenerated
instead and are thus included as static inlines in the header file. Therefore
we must recreated the desired functions using the function pointers found in
the vtable.
Also following the removal of the globals hash from the client code it is
necessary to setup a registry with a listener on it to receive the global
objects.
Signed-off-by: Rob Bradford <rob@linux.intel.com>
(cherry picked from commit
63db874e9c924f086bcd3518cc0f3d8c6df9ecec)
Zhao Yakui [Wed, 31 Oct 2012 08:47:59 +0000 (16:47 +0800)]
Avoid the dup of gen_free_avc_surface during compile
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 31 Oct 2012 08:47:58 +0000 (16:47 +0800)]
Restrict the max MV number in MV prediction
This is to follow the level limits for MV number for the two
consecutive MBs in H264 Spec.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 31 Oct 2012 08:47:57 +0000 (16:47 +0800)]
Allow to create batchbuffer based on the expected buffer size
This is to support the 4Kx4K encoding on Haswell. Otherwise the default batch
buffer size can't hold the encoding command for 4Kx4K encoding.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 31 Oct 2012 08:47:56 +0000 (16:47 +0800)]
Remove the dup code of XXX_mfc_avc_prepare
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 31 Oct 2012 08:47:55 +0000 (16:47 +0800)]
Remove the hard coded value to suppor the 4Kx4K encoding
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 31 Oct 2012 08:47:54 +0000 (16:47 +0800)]
Fix the issue in i965_UnlockSurface to lock it next time
It uses the variable of locked_image_id to check whether one surface is locked
or not. But as the locked_image_id is not assigned correctly, it causes that
it can't lock one surface next time although it calls the vaUnlockSurfaces.
Then the libva trace log can't dump the content of decoded/
encoded surface even after adding LIBVA_TRACE_SURFACE=XXX.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Gwenole Beauchesne <gb.devel@gmail.com>
Zhao Yakui [Wed, 31 Oct 2012 08:47:53 +0000 (16:47 +0800)]
Unify the XXX_free_avc_surface for media encoding/decoding
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Gautam [Wed, 31 Oct 2012 08:47:52 +0000 (16:47 +0800)]
Fix thread issue with AVC private surafce
https://bugs.freedesktop.org/show_bug.cgi?id=55282
Signed-off-by: Gautam <manamgautam@gmail.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 31 Oct 2012 08:47:51 +0000 (16:47 +0800)]
Unify the code for xxx_free_avc_surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 24 Oct 2012 08:47:53 +0000 (16:47 +0800)]
Make it built against the current upstream libdrm
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
a97403b2b9b5542aa6dd311b23b562a413abd431)
Li, Xiaowei A [Thu, 25 Oct 2012 03:28:44 +0000 (11:28 +0800)]
VEBOX: avoid allocing surface memory for vebox pipeline when external input or output surface is refered.
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Xiang, Haihao [Thu, 25 Oct 2012 07:09:13 +0000 (15:09 +0800)]
CSC on Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 25 Oct 2012 07:07:37 +0000 (15:07 +0800)]
Build VPP shaders for Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li, Xiaowei A [Fri, 19 Oct 2012 02:05:07 +0000 (10:05 +0800)]
VEBOX: Enable vebox pipeline for video process on HSW
Basic vebox pipeline is enabled to do deinterlacing, denoising
and color balance for NV12 format surfaces.
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li,Xiaowei [Thu, 23 Aug 2012 06:42:03 +0000 (14:42 +0800)]
Expose the vpp internal scaling function as an external interface for VEBOX.
Signed-off-by Li,Xiaowei <xiaowei.a.li@intel.com>
root [Thu, 18 Oct 2012 01:51:49 +0000 (09:51 +0800)]
Add special macro and command for vebox batch buffer execution.
Signed-off-by Li,Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Mon, 15 Oct 2012 15:10:18 +0000 (11:10 -0400)]
Haswell: Disable Picture ID Remapping for AVC decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Mon, 24 Sep 2012 21:22:43 +0000 (17:22 -0400)]
Add the default SEI info for CBR mode
This is to add the default SEI info in CBR mode when the upper application
doesn't pass the SEI package. Otherwise when SEI is not passed for CBR mode,
it will fail in HRD test.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Mon, 24 Sep 2012 21:20:44 +0000 (17:20 -0400)]
Use the common API to write avc SPS/PPS/SEI info on SNB/IVY/HSW
This is to remove the dup code.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 12 Sep 2012 20:31:07 +0000 (16:31 -0400)]
Handle the MFX change between A stepping and B-stepping for haswell
The A0-stepping is still covered.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 12 Sep 2012 20:13:51 +0000 (16:13 -0400)]
Add the seperate decoding callback API for Haswell
As the MFX involves quite a lot of changes between Ivy and Haswell,
the seperate decoding callback API is added for haswell. This
can avoid the complex backward logic for Ivy.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 7 Sep 2012 16:58:27 +0000 (12:58 -0400)]
Fix the incorrect syntax in VME shaders for Haswell
There is no functional change.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Tue, 28 Aug 2012 17:48:01 +0000 (13:48 -0400)]
Fix the incorrect mb_intra_struct for multi-slice on Haswell
Now the incorrect macroblock intra struct is passed under the multi-slice
scenario, which causes the wrong intra prediction for some macroblocks.
At the same time it also consider the scenario that the x coordinate
of the first macroblock in slice is not zero.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Tue, 28 Aug 2012 17:47:56 +0000 (13:47 -0400)]
Pass the mb_intra_struct by using thread payload on haswell
Now the mb_intra_struct is calculated by the GPU thread.
But when handling the logic for multi-slice, the GPU calculation will
become complex.So pass the intra struct flag of macroblock by using
thread payload.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 16 Aug 2012 20:45:40 +0000 (16:45 -0400)]
Add the support of encoding P/B-frame on haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Tue, 7 Aug 2012 19:33:11 +0000 (15:33 -0400)]
Add the Intra VME for I-frame on Haswell
At the same time the command buffer of MFC pak is constructed
by using CPU instead of GPU.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 20 Jul 2012 01:19:35 +0000 (21:19 -0400)]
Config the media chroma surface in the binding table for Haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 20 Jul 2012 01:16:04 +0000 (21:16 -0400)]
Add the common BRC API to avoid the duplicated code
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Fri, 20 Jul 2012 01:15:56 +0000 (21:15 -0400)]
Add the separated files for media encoder on haswell
There exist a lot of changes about the media encoder between Haswell
and IvyBridge. For example: the VME programming and the corresponding
general media command. To be simple, the separated files are added for
Haswell. Otherwise it has to consider the complex backward compatibility.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Gwenole Beauchesne [Fri, 18 May 2012 09:40:59 +0000 (11:40 +0200)]
haswell: fix video post-processing setup.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Wed, 9 May 2012 12:40:53 +0000 (14:40 +0200)]
haswell: fix render kernels.
Regenerate render kernels for Haswell because JMPI instruction semantics
changed there. In particular, the offset is now expressed in bytes instead
of 64-bit units.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Mon, 7 May 2012 09:29:46 +0000 (11:29 +0200)]
haswell: fix MPEG-2 decoding.
Fix MPEG-2 decoding, though disable error concealment logic for now.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Mon, 7 May 2012 07:17:55 +0000 (09:17 +0200)]
haswell: set "Shader Channel Select" fields in surface state.
For normal behaviour, each Shader Channel Select should be set to the
value indicating that same channel. i.e. Shader Channel Select Red is
set to SCS_RED, Shader Channel Select Green is set to SCS_GREEN, etc.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Mon, 7 May 2012 07:12:04 +0000 (09:12 +0200)]
haswell: fix 3DSTATE_PS to fill in number of samples.
The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen7_emit_invarient_states().
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Mon, 7 May 2012 07:09:48 +0000 (09:09 +0200)]
haswell: fix max PS threads shift value.
The maximum number of threads is now a 9-bit value. Thus, one more bit
towards LSB was re-used. i.e. bit position is now 23 instead of 24 on
Ivy Bridge.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Mon, 7 May 2012 07:05:21 +0000 (09:05 +0200)]
intel: fix max number of threads used on Ivy Bridge.
Fix the max number of threads to be used on Ivy Bridge. In particular,
the GEN7_PS_MAX_THREADS_SHIFT offset was wrong, thus causing the GPU
to use half of what was specified.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Mon, 7 May 2012 06:54:56 +0000 (08:54 +0200)]
haswell: use at least 64 URB entries for GT2+.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Mon, 7 May 2012 06:50:21 +0000 (08:50 +0200)]
Add PCI IDs for Haswell
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Halley [Fri, 21 Sep 2012 02:30:55 +0000 (10:30 +0800)]
fix ttmbf/ttfrm when vstransform is 0
(cherry picked from commit
c7d23b1e9376808dfa88192ee66a1af5acdf3b16)
Homer Hsing [Thu, 27 Sep 2012 05:24:09 +0000 (13:24 +0800)]
Change ILLEGAL instructions to NOP instructions in avc_mc.g4b.gen5
(cherry picked from commit
3b02b9d396c4ec7ab07ca0429023f3f54201d51b)
Gwenole Beauchesne [Wed, 29 Aug 2012 16:37:25 +0000 (18:37 +0200)]
render: add support for display rotation attribute.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit
8098e75a2a7d1dab08819e851a0eeb884f8e7f69)
Gwenole Beauchesne [Wed, 29 Aug 2012 15:27:25 +0000 (17:27 +0200)]
render: prepare for display attributes.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit
8dda3077e56d95c937e92ee6d6964fe6a22e9fd0)
Gwenole Beauchesne [Thu, 20 Sep 2012 08:01:30 +0000 (10:01 +0200)]
build: use libva-intel-driver as the package name.
Most OSVs adopted XXX-intel-driver as their shipping packages for the
Intel VA driver, with XXX = { vaapi, libva }. Adopt libva-intel-driver
from now on for upstream packages too.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit
a52e577cc78abcfe5f008a9bffe08927a02908ac)
Xiang, Haihao [Wed, 12 Sep 2012 07:27:46 +0000 (03:27 -0400)]
The block mask workaround is only available for Sandy bridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Halley [Thu, 2 Aug 2012 09:28:48 +0000 (12:28 +0300)]
work around hw limitation(dword alignment) of horizontal offset
on dst surface left edge for nv12 scaling (not avs)
Zhao Halley [Thu, 2 Aug 2012 09:22:33 +0000 (12:22 +0300)]
work around hw limitation(dword alignment) of horizontal offset
on dst surface left edge for load/save procedure
Zhao Halley [Thu, 2 Aug 2012 09:15:01 +0000 (12:15 +0300)]
use load/save procedure instead of scaling only when
src and dst rect have exactly same geometry
Zhao Halley [Mon, 13 Aug 2012 01:12:14 +0000 (09:12 +0800)]
reload horizontal mask after the first block in asm code
work around hw limiration(dword alignment) of horizontal offset
Zhao Halley [Thu, 2 Aug 2012 09:04:37 +0000 (12:04 +0300)]
work around hw limitation(dword alignment) of horizontal offset
on dst surface left edge (nv12 avs)
Zhao Halley [Thu, 26 Jul 2012 09:56:14 +0000 (12:56 +0300)]
PL8x4_Save_IMC3.asm fix of masked block
Zhao Halley [Thu, 26 Jul 2012 09:53:23 +0000 (12:53 +0300)]
reload block mask for the last(bottom/right) block in a strip
Zhao Halley [Thu, 26 Jul 2012 08:27:45 +0000 (11:27 +0300)]
enable horizontal and vertical mask for bottom/right boundary blocks
- usually it is 0xff/0xffff for common blocks in grf5
- one mask is setup in object_walker when the last group of blocks are met
- another mask should setup when the last block (in a group) is met.
it will be done in asm code, we make it ready in grf6
Zhao Halley [Thu, 16 Aug 2012 06:03:11 +0000 (14:03 +0800)]
add RGBX/BGRX to supported image list
Zhao Halley [Fri, 31 Aug 2012 00:35:21 +0000 (08:35 +0800)]
add format conversion stage in video post processing
Xiang, Haihao [Wed, 29 Aug 2012 05:24:00 +0000 (01:24 -0400)]
Adjust vertical scaling step for AVS on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 29 Aug 2012 05:29:44 +0000 (01:29 -0400)]
AVS workaround on IVB
Update AVS shaders and add CURBE parameters for AVS workaround
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 23 Aug 2012 02:55:00 +0000 (22:55 -0400)]
Update the shader for DI on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 29 Jun 2012 08:51:00 +0000 (16:51 +0800)]
Add support DN on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 22 Aug 2012 06:51:40 +0000 (02:51 -0400)]
New combined shaders for Ivybridge
In addtion, add the license header.
You need the latest intel-gen4asm to build these shaders
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Haitao Huang [Wed, 15 Aug 2012 17:43:56 +0000 (12:43 -0500)]
encode: sequence params should be reusable across frames
Client should not be required to send seq for each picture.
Change-Id: I4f24ac7dd7ad2d0657a641fb82793c9bae665694
Stéphane Marchesin [Fri, 3 Aug 2012 03:06:26 +0000 (20:06 -0700)]
intel-driver: Call intel_driver_terminate after i965_destroy_heap
Otherwise this leads to use-after-free of the bufmgr.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
(cherry picked from commit
5a449f5d2608adaf29c4c052aa28687d9e80a37a)
Zhao Halley [Thu, 19 Jul 2012 10:26:12 +0000 (13:26 +0300)]
add nv12 to rgb conversion in post processing
Zhao Halley [Thu, 12 Jul 2012 08:13:40 +0000 (11:13 +0300)]
add GPU shader for NV12->RGBX conversion
Zhao Halley [Thu, 19 Jul 2012 10:12:41 +0000 (13:12 +0300)]
add rgbx to nv12 conversion in post-processing
Zhao Halley [Thu, 12 Jul 2012 08:04:39 +0000 (11:04 +0300)]
add GPU shader for RGB->NV12 conversion
Zhao Halley [Thu, 19 Jul 2012 09:52:47 +0000 (12:52 +0300)]
define RGB layout in static parameter
Zhao Halley [Thu, 19 Jul 2012 09:49:08 +0000 (12:49 +0300)]
distinguish first plane width in pixel or in byte
Zhao Halley [Thu, 19 Jul 2012 09:34:29 +0000 (12:34 +0300)]
add RGB format surface support
Gwenole Beauchesne [Mon, 6 Aug 2012 14:11:47 +0000 (16:11 +0200)]
wayland: drop explicit dependencies to Wayland libraries.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Zhao halley [Thu, 24 May 2012 09:13:31 +0000 (17:13 +0800)]
wayland: ship with wayland-drm protocol.
Signed-off-by: Zhao Halley <halley.zhao@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Sat, 7 Apr 2012 18:08:03 +0000 (20:08 +0200)]
Add Wayland support.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Fri, 29 Jun 2012 12:56:28 +0000 (14:56 +0200)]
Drop explicit dependency on libva-x11.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Dmitry Ermilov [Thu, 7 Jun 2012 12:03:01 +0000 (08:03 -0400)]
Allow build without VA/X11 API.
Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Dmitry Ermilov [Thu, 7 Jun 2012 12:03:01 +0000 (08:03 -0400)]
Add raw DRM support.
Signed-off-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Mon, 6 Aug 2012 11:22:07 +0000 (13:22 +0200)]
Add shared library utils.
Add a few helpers to open shared libraries and load specific symbols
from there.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Fri, 6 Apr 2012 15:24:36 +0000 (17:24 +0200)]
dri: cope with drm_state changes.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>