Sanjay Patel [Wed, 20 Jun 2018 13:22:26 +0000 (13:22 +0000)]
[InstCombine] ignore debuginfo when removing redundant assumes (PR37726)
This is similar to:
rL335083
Fixes::
https://bugs.llvm.org/show_bug.cgi?id=37726
llvm-svn: 335121
Alex Bradbury [Wed, 20 Jun 2018 12:54:02 +0000 (12:54 +0000)]
[RISCV] Add InstAlias definitions for sgt and sgtu
These are produced by GCC and supported by GAS, but not currently contained in
the pseudoinstruction listing in the RISC-V ISA manual.
llvm-svn: 335120
Tim Northover [Wed, 20 Jun 2018 12:09:44 +0000 (12:09 +0000)]
ARM: convert ORR instructions to ADD where possible on Thumb.
Thumb has more 16-bit encoding space dedicated to ADD than ORR, allowing both a
3-address encoding and a wider range of immediates. So, particularly when
optimizing for code size (but it doesn't make things worse elsewhere) it's
beneficial to select an OR operation to an ADD if we know overflow won't occur.
This is made even better by LLVM's penchant for putting operations in canonical
form by converting the other way.
llvm-svn: 335119
Tim Northover [Wed, 20 Jun 2018 12:09:01 +0000 (12:09 +0000)]
[AArch64] Implement FLT_ROUNDS macro.
Very similar to ARM implementation, just maps to an MRS.
Should fix PR25191.
Patch by Michael Brase.
llvm-svn: 335118
Clement Courbet [Wed, 20 Jun 2018 11:54:35 +0000 (11:54 +0000)]
[llvm-exegesis] Add mechanism to add target-specific passes.
Summary:
createX86FloatingPointStackifierPass is disabled until we handle
TracksLiveness correctly.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48360
llvm-svn: 335117
Mikhail R. Gadelha [Wed, 20 Jun 2018 11:42:12 +0000 (11:42 +0000)]
[analyzer] Optimize constraint generation when the range is a concrete value
Summary:
If a constraint is something like:
```
$0 = [1,1]
```
it'll now be created as:
```
assert($0 == 1)
```
instead of:
```
assert($0 >= 1 && $0 <= 1)
```
In general, ~3% speedup when solving per query in my machine. Biggest improvement was when verifying sqlite3, total time went down from 3000s to 2200s.
I couldn't create a test for this as there is no way to dump the formula yet. D48221 adds a method to dump the formula but there is no way to do it from the command line.
Also, a test that prints the formula will most likely fail in the future, as different solvers print the formula in different formats.
Reviewers: NoQ, george.karpenkov, ddcc
Reviewed By: george.karpenkov
Subscribers: xazax.hun, szepet, a.sidorin
Differential Revision: https://reviews.llvm.org/D48227
llvm-svn: 335116
Guillaume Chatelet [Wed, 20 Jun 2018 11:09:36 +0000 (11:09 +0000)]
[llvm-exegesis] Fix failing test.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48358
llvm-svn: 335115
Pavel Labath [Wed, 20 Jun 2018 10:45:29 +0000 (10:45 +0000)]
IRInterpreter: fix sign extension of small types (pr37840)
Sign-extension of small types (e.g. short) was not handled correctly.
The reason for that was that when we were assigning the a value to the
Scalar object, we would accidentally promote the type to int (even
though the assignment code in AssignTypeToMatch tried to cast the value
to the appropriate type, it would still invoke the "int" version of
operator=). Instead, I use the APInt version of operator=, where the
bitwidth is specified explicitly. Among other things, this allows us to
fold the individual size cases into one.
llvm-svn: 335114
Andrea Di Biagio [Wed, 20 Jun 2018 10:08:11 +0000 (10:08 +0000)]
[llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register.
This patch teaches llvm-mca how to identify register writes that implicitly zero
the upper portion of a super-register.
On X86-64, a general purpose register is implemented in hardware as a 64-bit
register. Quoting the Intel 64 Software Developer's Manual: "an update to the
lower 32 bits of a 64 bit integer register is architecturally defined to zero
extend the upper 32 bits". Also, a write to an XMM register performed by an AVX
instruction implicitly zeroes the upper 128 bits of the aliasing YMM register.
This patch adds a new method named clearsSuperRegisters to the MCInstrAnalysis
interface to help identify instructions that implicitly clear the upper portion
of a super-register. The rest of the patch teaches llvm-mca how to use that new
method to obtain the information, and update the register dependencies
accordingly.
I compared the kernels from tests clear-super-register-1.s and
clear-super-register-2.s against the output from perf on btver2. Previously
there was a large discrepancy between the estimated IPC and the measured IPC.
Now the differences are mostly in the noise.
Differential Revision: https://reviews.llvm.org/D48225
llvm-svn: 335113
Pavel Labath [Wed, 20 Jun 2018 09:53:30 +0000 (09:53 +0000)]
Fix compilation with mingw-w64 (pr37873)
llvm-svn: 335112
Sjoerd Meijer [Wed, 20 Jun 2018 09:49:40 +0000 (09:49 +0000)]
[SPIR] Prevent SPIR targets from using half conversion intrinsics
The SPIR target currently allows for half precision floating point types to be
emitted using the LLVM intrinsic functions which convert half types to floats
and doubles. However, this is illegal in SPIR as the only intrinsic allowed by
SPIR is memcpy, as per section 3 of the SPIR specification. Currently this is
leading to an assert being hit in the Clang CodeGen when attempting to emit a
constant or literal _Float16 type in a comparison operation on a SPIR or SPIR64
target. This assert stems from the CodeGen attempting to emit a constant half
value as an integer because the backend has specified that it is using these
half conversion intrinsics (which represents half as i16). This patch prevents
SPIR targets from using these intrinsics by overloading the responsible target
info method, marks SPIR targets as having a legal half type and provides
additional regression testing for the _Float16 type on SPIR targets.
Patch by: Stephen McGroarty
Differential Revision: https://reviews.llvm.org/D48188
llvm-svn: 335111
Simon Pilgrim [Wed, 20 Jun 2018 09:39:01 +0000 (09:39 +0000)]
[SLPVectorizer] Split Tree/Reduction cost calls to simplify debugging. NFCI.
llvm-svn: 335110
Clement Courbet [Wed, 20 Jun 2018 09:18:37 +0000 (09:18 +0000)]
[llvm-exegesis] Remove noexcept in r335105.
gcc checks for transitivity (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53903)
llvm-svn: 335109
Clement Courbet [Wed, 20 Jun 2018 09:18:32 +0000 (09:18 +0000)]
[llvm-exegesis] Fix missing move in r335105.
llvm-svn: 335108
Martin Storsjo [Wed, 20 Jun 2018 09:17:19 +0000 (09:17 +0000)]
[Support] Add missing includes of <system_error> for std::error_code
This fixes compilation with MinGW after SVN r333798, which added
a few functions within _WIN32 ifdefs, functions returning
std::error_code. Include everything that is needed instead of
hoping that this header being inclued transitively (which it apparently
is in MSVC builds).
llvm-svn: 335107
Pavel Labath [Wed, 20 Jun 2018 09:00:30 +0000 (09:00 +0000)]
Fix windows build broken by r335104
lldb-python.h needs to be included first to work around some
incompatibilities between windows and python headers.
llvm-svn: 335106
Guillaume Chatelet [Wed, 20 Jun 2018 08:52:30 +0000 (08:52 +0000)]
[llvm-exegesis] Use a Prototype to defer picking a value for free vars.
Summary: Introducing a Prototype object to capture Variables that must be set but keeps degrees of freedom as Invalid. This allows exploring non constraint variables later on.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48316
llvm-svn: 335105
Pavel Labath [Wed, 20 Jun 2018 08:35:45 +0000 (08:35 +0000)]
Remove dependency from Host to python
Summary:
The only reason python was used in the Host module was to compute the
python path. I resolve this the same way as D47384 did for clang, by
moving the path computation into the python plugin and modifying
SBHostOS class to call into this module for ePathTypePythonDir.
Reviewers: zturner, jingham, davide
Subscribers: mgorny, lldb-commits
Differential Revision: https://reviews.llvm.org/D48215
llvm-svn: 335104
Alexey Bader [Wed, 20 Jun 2018 08:31:24 +0000 (08:31 +0000)]
[Sema] Allow creating types with multiple of the same addrspace.
Summary:
The comment with the OpenCL clause about this clearly
says: "No type shall be qualified by qualifiers for
two or more different address spaces."
This must mean that two or more qualifiers for the
_same_ address space is allowed. However, it is
likely unintended by the programmer, so emit a
warning.
For dependent address space types, reject them like
before since we cannot know what the address space
will be.
Patch by Bevin Hansson (ebevhan).
Reviewers: Anastasia
Reviewed By: Anastasia
Subscribers: bader, cfe-commits
Differential Revision: https://reviews.llvm.org/D47630
llvm-svn: 335103
Pavel Labath [Wed, 20 Jun 2018 08:12:50 +0000 (08:12 +0000)]
BreakpointIDList: Use llvm::ArrayRef instead of pointer+length pair
NFC
llvm-svn: 335102
Roman Lebedev [Wed, 20 Jun 2018 07:54:11 +0000 (07:54 +0000)]
[NFC][SCEV] Add tests related to bit masking (PR37793)
Summary:
Related to https://bugs.llvm.org/show_bug.cgi?id=37793, https://reviews.llvm.org/D46760#1127287
We'd like to do this canonicalization https://rise4fun.com/Alive/Gmc
But it is currently restricted by rL155136 / rL155362, which says:
```
// This is a constant shift of a constant shift. Be careful about hiding
// shl instructions behind bit masks. They are used to represent multiplies
// by a constant, and it is important that simple arithmetic expressions
// are still recognizable by scalar evolution.
//
// The transforms applied to shl are very similar to the transforms applied
// to mul by constant. We can be more aggressive about optimizing right
// shifts.
//
// Combinations of right and left shifts will still be optimized in
// DAGCombine where scalar evolution no longer applies.
```
I think these tests show that for *constants*, SCEV has no issues with that canonicalization.
Reviewers: mkazantsev, spatel, efriedma, sanjoy
Reviewed By: mkazantsev
Subscribers: sanjoy, javed.absar, llvm-commits, stoklund, bixia
Differential Revision: https://reviews.llvm.org/D48229
llvm-svn: 335101
Sjoerd Meijer [Wed, 20 Jun 2018 07:27:45 +0000 (07:27 +0000)]
[PatternMatch] Add m_Store pattern match helper
Differential Revision: https://reviews.llvm.org/D48279
llvm-svn: 335100
Roman Lebedev [Wed, 20 Jun 2018 07:01:14 +0000 (07:01 +0000)]
[X86][Znver1] Specify Register Files, RCU; FP scheduler capacity.
Summary:
First off: i do not have any access to that processor,
so this is purely theoretical, no benchmarks.
I have been looking into b**d**ver2 scheduling profile, and while cross-referencing
the existing b**t**ver2, znver1 profiles, and the reference docs
(`Software Optimization Guide for AMD Family {15,16,17}h Processors`),
i have noticed that only b**t**ver2 scheduling profile specifies these.
Also, there is no mca test coverage.
Reviewers: RKSimon, craig.topper, courbet, GGanesh, andreadb
Reviewed By: GGanesh
Subscribers: gbedwell, vprasad, ddibyend, shivaram, Ashutosh, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D47676
llvm-svn: 335099
Clement Courbet [Wed, 20 Jun 2018 06:44:13 +0000 (06:44 +0000)]
[X86] Fix r335097
Missed `Generic` test in llvm-mca.
llvm-svn: 335098
Clement Courbet [Wed, 20 Jun 2018 06:13:39 +0000 (06:13 +0000)]
[X86] Add sched class WriteLAHFSAHF and fix values.
Summary:
I ran llvm-exegesis on SKX, SKL, BDW, HSW, SNB.
Atom is from Agner and SLM is a guess.
I've left AMD processors alone.
Reviewers: RKSimon, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48079
llvm-svn: 335097
Hiroshi Inoue [Wed, 20 Jun 2018 05:29:26 +0000 (05:29 +0000)]
[NFC] fix trivial typos in comments
llvm-svn: 335096
Craig Topper [Wed, 20 Jun 2018 04:32:07 +0000 (04:32 +0000)]
[DAGCombiner] Add some comments to some true/false arguments to make it obvious what they are. NFC
llvm-svn: 335095
Craig Topper [Wed, 20 Jun 2018 04:32:06 +0000 (04:32 +0000)]
[X86] Remove a fptosi from the test_mm512_mask_reduce_max_pd fast-isel test.
The clang test inadvertently turned a floating point value into a double by having the wrong return type on the test function relative to the intrinsic it was testing.
This resulted in an extra fptosi instruction that propagated into this test when I copied the clang output.
llvm-svn: 335094
Craig Topper [Wed, 20 Jun 2018 04:32:05 +0000 (04:32 +0000)]
[SelectionDAG] Don't crash on inline assembly errors when the inline assembly return type is a struct.
Summary:
If we get an error building the SelectionDAG for inline assembly we try to continue and still build the DAG.
But if the return type for the inline assembly is a struct we end up crashing because we try to create an UNDEF node with a struct type which isn't valid.
Instead we need to create an UNDEF for each element of the struct and join them with merge_values.
This patch relies on single operand merge_values being handled gracefully by getMergeValues. If the return type is void there will be no VTs returned by ComputeValueVTs and now we just return instead of calling setValue. Hopefully that's ok, I assumed nothing would need to look up the mapped value for void node.
Fixes PR37359
Reviewers: rengolin, rovka, echristo, efriedma, bogner
Reviewed By: efriedma
Subscribers: craig.topper, llvm-commits
Differential Revision: https://reviews.llvm.org/D46560
llvm-svn: 335093
Craig Topper [Wed, 20 Jun 2018 04:32:04 +0000 (04:32 +0000)]
[X86] Use binary search of the EVEX->VEX static tables instead of populating two DenseMaps for lookups
Summary:
After r335018, the static tables are guaranteed sorted by the EVEX opcode to convert. We can use this to do a binary search and remove the need for any secondary data structures.
Right now one table is 736 entries and the other is 482 entries. It might make sense to merge the two tables as a follow up. The effort it takes to select the table is probably similar to the extra binary search step it would require for a larger table.
I haven't done any measurements to see if this has any effect on compile time, but I don't imagine that EVEX->VEX conversion is a place we spend a lot of time.
Reviewers: RKSimon, spatel, chandlerc
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48312
llvm-svn: 335092
Philip Reames [Wed, 20 Jun 2018 02:43:46 +0000 (02:43 +0000)]
Add more test cases for deopt-operands via regalloc
This time, focused on reuse of arguments slots. Only one minor todo here.
llvm-svn: 335091
Fangrui Song [Wed, 20 Jun 2018 02:06:01 +0000 (02:06 +0000)]
[ELF] Support -z initfirst
Summary:
glibc uses this option to link libpthread.so
glibc/nptl/Makefile:
LDFLAGS-pthread.so = -Wl,--enable-new-dtags,-z,nodelete,-z,initfirst
Reviewers: ruiu, echristo, espindola
Subscribers: emaste, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D48329
llvm-svn: 335090
Reid Kleckner [Wed, 20 Jun 2018 01:09:51 +0000 (01:09 +0000)]
[asan] Add flushes to try to fix test
llvm-svn: 335089
Douglas Yung [Wed, 20 Jun 2018 01:05:09 +0000 (01:05 +0000)]
Add a test to verify the x86 intrinsic headers compile cleanly with no warnings or errors.
llvm-svn: 335088
Reid Kleckner [Wed, 20 Jun 2018 00:45:54 +0000 (00:45 +0000)]
[asan] Add Windows test for handle_segv and SetUnhandledExceptionFilter
llvm-svn: 335087
Craig Topper [Wed, 20 Jun 2018 00:31:39 +0000 (00:31 +0000)]
[X86] Undefine _mm512_mask_reduce_operator macro in avx512fintrin.h before redefining it.
llvm-svn: 335086
Vlad Tsyrklevich [Wed, 20 Jun 2018 00:02:32 +0000 (00:02 +0000)]
Revert r334980 and 334983
This reverts commits r334980 and r334983 because they were causing build
timeouts on the x86_64-linux-ubsan bot.
llvm-svn: 335085
Michael Kruse [Tue, 19 Jun 2018 23:46:52 +0000 (23:46 +0000)]
Append new attributes to the end of an AttributeList.
... instead of prepending it at the beginning (the original behavior
since implemented in r122535 2010-12-23). This builds up an
AttributeList in the the order in which the attributes appear in the
source.
The reverse order caused nodes for attributes in the AST (e.g. LoopHint)
to be in the reverse, and therefore printed in the wrong order by
-ast-dump. Some TODO comments mention this. The order was explicitly
reversed for enable_if attribute overload resolution and name mangling,
which is not necessary anymore with this patch.
The change unfortunately has some secondary effects, especially for
diagnostic output. In the simplest cases, the CHECK lines or expected
diagnostic were changed to the the new output. If the kind of
error/warning changed, the attribute's order was changed instead.
It also causes some 'previous occurrence here' hints to be textually
after the main marker. This typically happens when attributes are
merged, but are incompatible. Interchanging the role of the the main
and note SourceLocation will also cause the case where two different
declaration's attributes (in contrast to multiple attributes of the
same declaration) are merged to be reversed. There is no easy fix
because sometimes previous attributes are merged into a new
declaration's attribute list, sometimes new attributes are added to a
previous declaration's attribute list. Since 'previous occurrence here'
pointing to locations after the main marker is not rare, I left the
markers as-is; it is only relevant when the attributes are declared in
the same declaration anyway, which often is on the same line.
Differential Revision: https://reviews.llvm.org/D48100
llvm-svn: 335084
Vedant Kumar [Tue, 19 Jun 2018 23:42:17 +0000 (23:42 +0000)]
[IR] Introduce helpers to skip debug instructions (NFC)
This patch introduces two helpers to make it easier to ignore debug
intrinsics:
- Instruction::getNextNonDebugInstruction()
This is just like Instruction::getNextNode(), except that it skips debug
info.
- skipDebugInfo(BasicBlock::iterator)
A free function which advances a BasicBlock iterator past any debug
info. This is a no-op when the iterator already points to a non-debug
instruction.
Part of: llvm.org/PR37728
Related to: https://reviews.llvm.org/D47874
Differential Revision: https://reviews.llvm.org/D48305
llvm-svn: 335083
Nico Weber [Tue, 19 Jun 2018 23:19:34 +0000 (23:19 +0000)]
clang-cl: Emit narrowing diag for initializer lists if -fmsc-version is at least 1900 (i.e. MSVC2015).
Diagnostics for narrowing conversions in initializer lists are currently
DefaultIgnored in Microsoft mode. But MSVC 2015 did add warnings about
narrowing conversions (C2397), so clang-cl can remove its special case code if
MSCompatibilityVersion is new enough.
(In MSVC, C2397 is just a warning and in clang it's default-mapped to an error,
but it can be remapped, and disabled with -Wno-c++11-narrowing, so that should
be fine.)
Fixes PR37314.
https://reviews.llvm.org/D48296
llvm-svn: 335082
Alex Lorenz [Tue, 19 Jun 2018 22:47:53 +0000 (22:47 +0000)]
Recommit r335063: [Darwin] Add a warning for missing include path for libstdc++
The recommit ensures that the tests that failed on bots don't trigger the warning.
Xcode 10 removes support for libstdc++, but the users just get a confusing
include not file warning when including an STL header (when building for iOS6
which uses libstdc++ by default for example).
This patch adds a new warning that lets the user know that the libstdc++ include
path was not found to ensure that the user is more aware of why the error occurs.
rdar://
40830462
Differential Revision: https://reviews.llvm.org/D48297
llvm-svn: 335081
Kuba Mracek [Tue, 19 Jun 2018 22:22:48 +0000 (22:22 +0000)]
[llvm] Document "%T" as deprecated in TestingGuide.rst
Differential Revision: https://reviews.llvm.org/D48189
llvm-svn: 335080
Jason Molenda [Tue, 19 Jun 2018 21:39:10 +0000 (21:39 +0000)]
Correct the pathname that PlatformDarwinKernel::ExamineKextForMatchingUUID
passes to the recursive search function so we only recursively
search the kext bundle directory, instead of its parent directory.
<rdar://problem/
41227170>
Differential Revision: https://reviews.llvm.org/D48302
llvm-svn: 335079
Raphael Isemann [Tue, 19 Jun 2018 21:25:59 +0000 (21:25 +0000)]
Refactor OnExit utility class in ClangUserExpression
Summary:
OnExit ensures we call `ResetDeclMap` before this method ends. However,
we also have a few manual calls to ResetDeclMap in there that are actually unnecessary
because of this (calling the method multiple times has no effect). This patch also moves
the class out of the method that we can reuse it for the upcoming method that handles
parsing for completion.
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D48337
llvm-svn: 335078
Philip Reames [Tue, 19 Jun 2018 21:19:59 +0000 (21:19 +0000)]
[InlineSpiller] Fix a crash due to lack of forward progress from remat specifically for STATEPOINT
This patch covers up a fairly fundemental issue around remat and register allocation which shows up with psuedo instructions with more vreg uses than there are physical registers. This patch essentially just disables remat for STATEPOINTs which are the only case we've seen so far, but long term we need a better fix.
For STATEPOINTs specifically, this is a strict improvement. It unblocks progress towards enabling a currently off-by-default mode which integrates deopt bundle operand lowering with register allocator spilling so that we end up with smaller stack sizes and more optimally placed spills. Assming no other issues turn up during my next round of integration testing - which based on experience so far, is admittedly unlikely - we might finally be able to enable something I've been working towards in small bits and pieces for years now. :)
For psuedo ops in general, there are a couple of ideas for a "proper fix" discussed on the bug, but I'm far enough outside my knowledge area to not be able to see any of them through to a successful conclusion. If anyone wants to help out here, please do.
Differential Revision: https://reviews.llvm.org/D41098
llvm-svn: 335077
Jessica Paquette [Tue, 19 Jun 2018 21:14:48 +0000 (21:14 +0000)]
[MachineOutliner] NFC: Remove insertOutlinerPrologue, rename insertOutlinerEpilogue
insertOutlinerPrologue was not used by any target, and prologue-esque code was
beginning to appear in insertOutlinerEpilogue. Refactor that into one function,
buildOutlinedFrame.
This just removes insertOutlinerPrologue and renames insertOutlinerEpilogue.
llvm-svn: 335076
Craig Topper [Tue, 19 Jun 2018 21:00:30 +0000 (21:00 +0000)]
Recommit r335070 "[X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible.""
Test has been updated to reflect the IRGen.
llvm-svn: 335075
Heejin Ahn [Tue, 19 Jun 2018 20:30:42 +0000 (20:30 +0000)]
[WebAssembly] Fix liveness tracking info after drop insertion
Summary:
This fixes liveness tracking information after `drop` instruction
insertion in ExplicitLocals pass.
When a drop instruction is inserted to drop a dead register operand, the
original operand should be marked not dead anymore because it is now
used by the new drop instruction. And the operand to the new drop
instruction should be marked killed instead. This bug caused some
programs to fail when `llc` is run with `-verify-machineinstrs` option.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D48253
llvm-svn: 335074
Alex Lorenz [Tue, 19 Jun 2018 19:43:07 +0000 (19:43 +0000)]
Revert r335063 as it causes bot failures
llvm-svn: 335073
Craig Topper [Tue, 19 Jun 2018 19:37:07 +0000 (19:37 +0000)]
Revert r335070 "[X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible."
The test changes are failing the buildbot and its going to take me some time to fix it.
llvm-svn: 335072
Craig Topper [Tue, 19 Jun 2018 19:14:50 +0000 (19:14 +0000)]
[X86] Update fast-isel tests for clang's avx512f reduction intrinsics to match the codegen from r335070.
llvm-svn: 335071
Craig Topper [Tue, 19 Jun 2018 19:13:54 +0000 (19:13 +0000)]
[X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible.
We only need to use 512 bit vectors all the way through v8i64 reductions since those max instructions are new to avx512f and only available in 512 bits until SKX.
For v16i32 and floating point we have legacy 128/256 bit instructions we can use.
I've tried to use other intrinsics to reduce the verbosity of the code and avoid having to mention all the shuffles. I've also removed all the -1 shuffle indices so the output sequence is fully specified and not left to backend optimization.
Differential Revision: https://reviews.llvm.org/D47401
llvm-svn: 335070
Jonas Hahnfeld [Tue, 19 Jun 2018 19:08:17 +0000 (19:08 +0000)]
Remove liboffload from repository
See the mailing list for the proposal and discussion:
http://lists.llvm.org/pipermail/openmp-dev/2018-June/002041.html
llvm-svn: 335069
Craig Topper [Tue, 19 Jun 2018 18:52:15 +0000 (18:52 +0000)]
[X86] Add fast-isel tests for clang's AVX512F vector reduction intrinsics.
llvm-svn: 335068
Sanjay Patel [Tue, 19 Jun 2018 18:44:00 +0000 (18:44 +0000)]
[IR] move shuffle mask queries from TTI to ShuffleVectorInst
The optimizer is getting smarter (eg, D47986) about differentiating shuffles
based on its mask values, so we should make queries on the mask constant
operand generally available to avoid code duplication.
We'll probably use this soon in the vectorizers and instcombine (D48023 and
https://bugs.llvm.org/show_bug.cgi?id=37806).
We might clean up TTI a bit more once all of its current 'SK_*' options are
covered.
Differential Revision: https://reviews.llvm.org/D48236
llvm-svn: 335067
Matt Davis [Tue, 19 Jun 2018 18:39:40 +0000 (18:39 +0000)]
[MIRParser] Update a diagnostic message to use the correct register sigil. NFC
Summary:
Patch r323922 changed the sigil for physical registers to '$', instead of '%'.
An error message was missed during this change, and reports the wrong sigil.
This patch corrects that diagnostic and the tests that check that error string.
Reviewers: zer0, bjope
Reviewed By: bjope
Subscribers: bjope, thegameg, plotfi, llvm-commits
Differential Revision: https://reviews.llvm.org/D48086
llvm-svn: 335066
Krzysztof Parzyszek [Tue, 19 Jun 2018 18:09:54 +0000 (18:09 +0000)]
[Hexagon] Fix the value of HexagonII::TypeCVI_FIRST
This value is the first vector instruction type in numerical order. The
previous value was incorrect, leaving TypeCVI_GATHER outside of the range
for vector instructions. This caused vector .new instructions to be
incorrectly encoded in the presence of gather.
llvm-svn: 335065
Craig Topper [Tue, 19 Jun 2018 18:06:52 +0000 (18:06 +0000)]
[X86] Initialize FMA3Info directly in its constructor instead of relying on std::call_once
FMA3Info only exists as a managed static. As far as I know the ManagedStatic construction proccess is thread safe. It doesn't look like we ever access the ManagedStatic object without immediately doing a query on it that would require the map to be populated. So I don't think we're ever deferring the calculation of the tables from the construction of the object.
So I think we should be able to just populate the FMA3Info map directly in the constructor and get rid of all of the initGroupsOnce stuff.
Differential Revision: https://reviews.llvm.org/D48194
llvm-svn: 335064
Alex Lorenz [Tue, 19 Jun 2018 17:56:03 +0000 (17:56 +0000)]
[Darwin] Add a warning for missing include path for libstdc++
Xcode 10 removes support for libstdc++, but the users just get a confusing
include not file warning when including an STL header (when building for iOS6
which uses libstdc++ by default for example).
This patch adds a new warning that lets the user know that the libstdc++ include
path was not found to ensure that the user is more aware of why the error occurs.
rdar://
40830462
Differential Revision: https://reviews.llvm.org/D48297
llvm-svn: 335063
Craig Topper [Tue, 19 Jun 2018 17:51:42 +0000 (17:51 +0000)]
[X86] Don't fold unaligned loads into SSE ROUNDPS/ROUNDPD for ceil/floor/nearbyint/rint/trunc.
Incorrect patterns were added in r334460. This changes them to check alignment properly for SSE.
llvm-svn: 335062
Krzysztof Parzyszek [Tue, 19 Jun 2018 17:26:20 +0000 (17:26 +0000)]
[Hexagon] Enforce restrictions on packetizing cache instructions
llvm-svn: 335061
Pavel Labath [Tue, 19 Jun 2018 17:24:03 +0000 (17:24 +0000)]
Scalar: Use llvm integer conversion functions
StringConvert was the only non-Utility dependency of this class. Getting
rid of it means it will be easy to move this class to a lower layer.
While I was in there, I also added a couple of unit tests for the Scalar
string conversion function.
llvm-svn: 335060
Simon Atanasyan [Tue, 19 Jun 2018 16:48:30 +0000 (16:48 +0000)]
[ELF][MIPS] Temporarily mark failed MIPS tests as XFAIL.
microMIPS 64-bit is unsupported by LLVM starting from r335057. But such
code can be generated by GCC. Mark failed test cases as XFAIL while
decide to drop microMIPS 64-bit support from LLD too or use binary
inputs for the test.
llvm-svn: 335059
Saleem Abdulrasool [Tue, 19 Jun 2018 16:47:31 +0000 (16:47 +0000)]
docs: document CodeView directives
Add documentation for assembler directives added to support CodeView
emission.
Patch by Ellis Hoag!
llvm-svn: 335058
Simon Dardis [Tue, 19 Jun 2018 16:05:44 +0000 (16:05 +0000)]
[mips] Mark microMIPS64 as being unsupported.
There are no provided instruction definitions for this architecture.
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D48320
llvm-svn: 335057
Simon Atanasyan [Tue, 19 Jun 2018 15:57:24 +0000 (15:57 +0000)]
Remove empty unused folders. NFC
llvm-svn: 335056
Fangrui Song [Tue, 19 Jun 2018 15:39:19 +0000 (15:39 +0000)]
[XRay] Fix error message. NFC
Reviewers: dberris
Subscribers: delcypher, llvm-commits, #sanitizers
Differential Revision: https://reviews.llvm.org/D48313
llvm-svn: 335055
Kostya Kortchinsky [Tue, 19 Jun 2018 15:36:30 +0000 (15:36 +0000)]
[scudo] Move noinline functions definitions out of line
Summary:
Mark `isRssLimitExceeded` as `NOINLINE`, and move it's definition as well as
the one of `performSanityChecks` out of the class definition, as requested.
Reviewers: filcab, alekseyshl
Reviewed By: alekseyshl
Subscribers: delcypher, #sanitizers, llvm-commits
Differential Revision: https://reviews.llvm.org/D48228
llvm-svn: 335054
Simon Dardis [Tue, 19 Jun 2018 15:25:01 +0000 (15:25 +0000)]
[mips] Fix the predicates of some aliases
Previously, some aliases were marked as not being available for microMIPS32R6,
but this was overridden at the top level.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D48321
llvm-svn: 335053
Pavel Labath [Tue, 19 Jun 2018 15:09:07 +0000 (15:09 +0000)]
Replace HostInfo::GetLLDBPath with specific functions
Summary:
Instead of a function taking an enum value determining which path to
return, we now have a suite of functions, each returning a single path
kind. This makes it easy to move the python-path function into a
specific plugin in a follow-up commit.
All the users of GetLLDBPath were converted to call specific functions
instead. Most of them were hard-coding the enum value anyway, so this
conversion was simple. The only exception was SBHostOS, which I've
changed to use a switch on the incoming enum value.
Reviewers: clayborg, zturner
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D48272
llvm-svn: 335052
Pavel Labath [Tue, 19 Jun 2018 15:07:22 +0000 (15:07 +0000)]
Make TestCommandScript.py NO_DEBUG_INFO_TESTCASE
llvm-svn: 335051
Aaron Ballman [Tue, 19 Jun 2018 14:59:11 +0000 (14:59 +0000)]
Implement semantic checking for __builtin_signbit.
r242675 changed the signature for the signbit builtin but did not introduce proper semantic checking to ensure the arguments are as-expected. This patch groups the signbit builtin along with the other fp classification builtins. Fixes PR28172.
llvm-svn: 335050
Aaron Ballman [Tue, 19 Jun 2018 14:53:20 +0000 (14:53 +0000)]
Reverting due to line ending changes; will reapply after addressing that.
llvm-svn: 335049
Aaron Ballman [Tue, 19 Jun 2018 14:36:04 +0000 (14:36 +0000)]
Implement semantic checking for __builtin_signbit.
r242675 changed the signature for the signbit builtin but did not introduce proper semantic checking to ensure the arguments are as-expected. This patch groups the signbit builtin along with the other fp classification builtins. Fixes PR28172.
llvm-svn: 335048
Pavel Labath [Tue, 19 Jun 2018 14:23:31 +0000 (14:23 +0000)]
Attempt to fix windows build broken by r334968
The issue was that there was no dependency from lldb-suite target to liblldb in
the no-framework scenario. This caused the finish-swig target to be executed
prematurely and fail (because it cannot copy liblldb to the python folder). On
other platforms this did not matter because there just creates a symlink.
The extra lldb-suite -> liblldb edge should fix this. Technically, I could add
this just to the !framework case as the framework target will take care of the
transitive dep, but it seemed more clear to make the dep unconditional.
llvm-svn: 335047
Guansong Zhang [Tue, 19 Jun 2018 14:05:38 +0000 (14:05 +0000)]
[OpenMP] [CUDA] Expose teamid to the debug path
Summary: Small bug fix for debug build. A previous fix causing trouble for debug build.
Reviewers: grokos
Reviewed By: grokos
Subscribers: openmp-commits
Tags: #openmp
Differential Revision: https://reviews.llvm.org/D48286
llvm-svn: 335046
Simon Pilgrim [Tue, 19 Jun 2018 13:40:00 +0000 (13:40 +0000)]
[SLPVectorizer] Remove default OperandValueKind arguments from getArithmeticInstrCost calls (NFC)
The getArithmeticInstrCost calls for shuffle vectors entry costs specify TargetTransformInfo::OperandValueKind arguments, but are just using the method's default values. This seems to be a copy + paste issue and doesn't affect the costs in anyway. The TargetTransformInfo::OperandValueProperties default arguments are already not being used.
Noticed while working on D47985.
Differential Revision: https://reviews.llvm.org/D48008
llvm-svn: 335045
Strahinja Petrovic [Tue, 19 Jun 2018 13:07:40 +0000 (13:07 +0000)]
[PowerPC] Fix label address calculation for ppc32
This patch fixes calculating address of label on ppc32 (for -fPIC).
Differential Revision: https://reviews.llvm.org/D46582
llvm-svn: 335043
Roman Lebedev [Tue, 19 Jun 2018 11:58:10 +0000 (11:58 +0000)]
llvm-exegesis: mark ~ExegesisTarget() as virtual. Fixes build.
/build/llvm/tools/llvm-exegesis/lib/X86/../Target.h:32:3: error: 'exegesis::ExegesisTarget' has virtual functions but non-virtual destructor [-Werror,-Wnon-virtual-dtor]
~ExegesisTarget();
^
/build/llvm/tools/llvm-exegesis/lib/X86/Target.cpp:15:7: error: 'exegesis::(anonymous namespace)::ExegesisX86Target' has virtual functions but non-virtual destructor [-Werror,-Wnon-virtual-dtor]
class ExegesisX86Target : public ExegesisTarget {
^
llvm-svn: 335042
Clement Courbet [Tue, 19 Jun 2018 11:28:59 +0000 (11:28 +0000)]
Re-land r335038 "[llvm-exegesis] A mechanism to add target-specific functionality.""
Fix typo: LLVM_NATIVE_ARCH -> LLVM_EXEGESIS_NATIVE_ARCH.
llvm-svn: 335041
Clement Courbet [Tue, 19 Jun 2018 10:54:12 +0000 (10:54 +0000)]
Revert r335038 "[llvm-exegesis] A mechanism to add target-specific functionality."
Breaks buildbots.
llvm-svn: 335040
Mikhail Dvoretckii [Tue, 19 Jun 2018 10:49:12 +0000 (10:49 +0000)]
[InstCombine] Replacing X86-specific rounding intrinsics with generic floor-ceil
This patch replaces calls to X86-specific intrinsics with floor-ceil semantics
with calls to target-independent @llvm.floor.* and @llvm.ceil.* intrinsics. This
doesn't affect the resulting machine code, as those intrinsics are lowered to
the same instructions, but exposes these specific rounding cases to generic
optimizations.
Differential Revision: https://reviews.llvm.org/D48067
llvm-svn: 335039
Clement Courbet [Tue, 19 Jun 2018 10:39:50 +0000 (10:39 +0000)]
[llvm-exegesis] A mechanism to add target-specific functionality.
Summary: This is a step towards implementing memory operands and X87.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48210
llvm-svn: 335038
Mikhail Dvoretckii [Tue, 19 Jun 2018 10:37:52 +0000 (10:37 +0000)]
[X86] VRNDSCALE* folding from masked and scalar ffloor and fceil patterns
This patch handles back-end folding of generic patterns created by lowering the
X86 rounding intrinsics to native IR in cases where the instruction isn't a
straightforward packed values rounding operation, but a masked operation or a
scalar operation.
Differential Revision: https://reviews.llvm.org/D45203
llvm-svn: 335037
David Green [Tue, 19 Jun 2018 09:43:36 +0000 (09:43 +0000)]
[LoopSimplifyCFG] Invalidate SCEV in LoopSimplifyCFG
LoopSimplifyCFG, being a loop pass, needs to preserve scalar
evolution. This invalidates SE for the loops altered during
block merging.
Differential Revision: https://reviews.llvm.org/D48258
llvm-svn: 335036
Eric Liu [Tue, 19 Jun 2018 09:33:53 +0000 (09:33 +0000)]
[clangd] Use workspace root path as hint path for resolving URIs in workspace/symbol
Summary:
Some URI schemes require a hint path to be provided, and workspace root
path seems to be a good fit.
Reviewers: sammccall, malaperle
Reviewed By: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, cfe-commits
Differential Revision: https://reviews.llvm.org/D48290
llvm-svn: 335035
Roman Lebedev [Tue, 19 Jun 2018 09:21:27 +0000 (09:21 +0000)]
[MCA][NFC] Add generic XOP resource tests
Summary:
Based on
* [[ https://support.amd.com/TechDocs/43479.pdf | AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions ]],
* [[ https://support.amd.com/TechDocs/24594.pdf | AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions]],
* https://en.wikipedia.org/wiki/XOP_instruction_set
Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.
Reviewers: RKSimon, craig.topper, andreadb, spatel
Reviewed By: RKSimon
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48264
llvm-svn: 335034
Roman Lebedev [Tue, 19 Jun 2018 09:21:22 +0000 (09:21 +0000)]
[MCA][NFC] Add generic TBM resource tests
Summary:
Based on https://support.amd.com/TechDocs/24594.pdf,
https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)
Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.
Reviewers: RKSimon, craig.topper, simark, andreadb
Reviewed By: RKSimon
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48252
llvm-svn: 335033
Simon Pilgrim [Tue, 19 Jun 2018 09:16:06 +0000 (09:16 +0000)]
[SLPVectorizer] Pull out AltOpcode determination from reorderAltShuffleOperands.
Minor step towards making the alternate opcode system work with a wider range of opcode pairs.
llvm-svn: 335032
Bjorn Pettersson [Tue, 19 Jun 2018 08:41:34 +0000 (08:41 +0000)]
Remove valueCoversEntireFragment asserts in ConvertDebugDeclareToDebugValue
This is a fixup for r334830 causing problems in polly-aosp buildbot.
Focus in r334830 was to fix a problem seen with
ConvertDebugDeclareToDebugValue involving store instructions.
It also added some asserts to find out of similar problems
existed for the ConvertDebugDeclareToDebugValue functions
involving load and phi instructions. One of those asserts seems
to blow in the polly-aosp buildbot, so I'll revert the asserts
while debugging.
llvm-svn: 335031
Kristof Umann [Tue, 19 Jun 2018 08:35:02 +0000 (08:35 +0000)]
[analyzer] Made a buildbot happy.
Since `isPrimitiveType` was only used in an assert, a builbot with `-Werror`
and no asserts enabled failed to build it as it was unused.
llvm-svn: 335030
Tobias Grosser [Tue, 19 Jun 2018 08:13:53 +0000 (08:13 +0000)]
Move ScopInfo to isl++
llvm-svn: 335029
Adrian Kuegel [Tue, 19 Jun 2018 08:12:28 +0000 (08:12 +0000)]
Add a factory method to ConstantDataArray that allows to pass in the data as StringRef
This simplifies the case if we already have access to the raw data that we need to store in a ConstantDataArray.
The new factor method can also be reused for implementing the factory method that gets the data as ArrayRef.
Differential Revision: https://reviews.llvm.org/D47706
llvm-svn: 335028
Florian Hahn [Tue, 19 Jun 2018 08:03:24 +0000 (08:03 +0000)]
[LoopInterchange] Move PHI handling to adjustLoopBranches.
This patch moves the logic to handle reduction PHI nodes to the end of
adjustLoopBranches. Reduction PHI nodes in the outer loop header can be
moved to the inner loop header and reduction PHI nodes from the inner loop
header can be moved to the outer loop header. In the latter situation,
we have to deal with 1 kind of PHI nodes:
PHI nodes that are part of inner loop-only reductions.
We can replace the PHI node with the value coming from outside
the inner loop.
Reviewers: mcrosier, efriedma, karthikthecool
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D46198
llvm-svn: 335027
Mikhail Dvoretckii [Tue, 19 Jun 2018 07:55:10 +0000 (07:55 +0000)]
Test commit.
llvm-svn: 335026
Fangrui Song [Tue, 19 Jun 2018 07:11:33 +0000 (07:11 +0000)]
[XRay] rm GLOB || true -> rm -f
Summary: `rm -f` does not write diagnostic message when there is no file argument.
Reviewers: dberris
Subscribers: delcypher, llvm-commits, #sanitizers
Differential Revision: https://reviews.llvm.org/D48311
llvm-svn: 335025
QingShan Zhang [Tue, 19 Jun 2018 06:54:51 +0000 (06:54 +0000)]
If the arch is P9, we will select the DFLOADf32/DFLOADf64 pseudo instruction when we are loading a floating,
and expand it post RA basing on the register pressure. However, we miss to do the add-imm peephole for these pseudo instruction.
Differential Revision: https://reviews.llvm.org/D47568
Reviewed By: Nemanjai
llvm-svn: 335024
Roger Ferrer Ibanez [Tue, 19 Jun 2018 06:45:47 +0000 (06:45 +0000)]
[RISCV] Add tests for overflow intrinsics
This is using the existing codegen so we can see the change once we custom
lower ISD::{U,S}{ADD,SUB}O nodes.
llvm-svn: 335023
Taiju Tsuiki [Tue, 19 Jun 2018 05:35:30 +0000 (05:35 +0000)]
Revert r335019 "Update NRVO logic to support early return (Attempt 2)"
llvm-svn: 335022
Akira Hatanaka [Tue, 19 Jun 2018 05:04:44 +0000 (05:04 +0000)]
[Sema] Produce diagnostics for attribute 'trivial_abi' that appears
after the closing brace of a class declaration.
Merge the two call sites of checkIllFormedTrivialABIStruct and sink it
into CheckCompletedCXXClass so that it is called after the attribute has
been attached to the CXXRecordDecl.
rdar://problem/
40873297
llvm-svn: 335021