tgsi_to_nir: translate SAMPLEID

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8906>

st/mesa: do scissored clears on depth/stencil as well when supported

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8905>

zink: support nir_intrinsic_memory_barrier_buffer

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8884>

panfrost: Fix clear color packing for 12-byte formats

Make the case for 6 bytes the same as for 8 while we're at it.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8886>

radv: Update JSON generator if Windows

Use vulkan_radeon.dll, and apply current working directory.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8911>

nv50,nvc0: add scissored clear support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8901>

nv50: add PIPE_CAP_NIR_IMAGES_AS_DEREF to unsupported list

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8901>

radeonsi: don't use cp_dma prefetch on GFX6

It's not supported.

Fixes: 47587758f21 ("radeonsi: prefetch VB descriptors right after uploading")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4211
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8914>

spirv: Allow variable pointers pointing to an array of blocks

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8864>

ci: Move out expect files from .gitlab-ci

This way, when such a file is modified only the affected driver gets
tested.

It also helps to declutter the .gitlab-ci directory.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8757>

ci: Move container files into their own dir

To be more consistent and to declutter the .gitlab-ci dir.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8757>

ci: Fix selection of linker in Android builds

Otherwise, Clang will error out when it doesn't link:

Compiler stderr:
 clang: error: argument unused during compilation: '-fuse-ld=lld' [-Werror,-Wunused-command-line-argument]

When that happens when Meson is checking for the presence of macros in
sys/sysmacros.h, that file won't be included resulting in the following
errors:

ld.lld: error: undefined symbol: makedev
ld.lld: error: undefined symbol: major
ld.lld: error: undefined symbol: minor

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Eric Anholt <eric@anholt.net>
Gitlab: #4137
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8757>

pan/bi: Add nosched debug option

Forces a trivial schedule to replicate the old behaviour (for debugging
or benchmarking). Actually the new scheduler is still used, just highly
constrained; the net result should still do what's expected.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Remove older cube map lowering

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Remove old FAU assignment code

Replaced by the scheduler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Switch to new scheduler

Delete the old.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Schedule blocks

Replicate the pattern, greedily select clauses until we run out of
instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant modifier handling

Once we've merged the clauses' constants, we need to....

1. Swap where necessary so non-pcrel constants are correctly encoded.
2. Swap where necessary so pcrel constants are in canonical positions.
3. Force M1 values for pcrel constants and final single constants.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant merging routines

These work as you would expect: first handling paired constants
(swapping to a canonical form to deduplicate), then handling unpaired
constants (packing together in a canonical form). Most of the added
complexity is from pcrel handling, but we impose strict invariants on
pcrel (no more than one PC-relative constant per clause, only M1=4 mode)
without which the algorithm would be even uglier.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant state constructor

Based on the tuple state's constants, satisfying the pcrel invariant we
impose.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant to passthrough rewrite

Mimicks the one previously done at pack time, but designed for schedule
time instead.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add trivial rewrite helpers

We need to do certain rewrites during scheduling before RA runs in order
to satsify scheduler post-conditions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Derive M0 from pcrel_idx while packing

Assumes the usual M1=4 mode.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add pcrel_idx to bi_clause

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Move bi_constant_field to bifrost.h

It's a hardware invariant, and useful for the scheduler (not just
packing).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add bi_foreach_instr_and_src_in_tuple

Rather specialized but keeps down obnoxious indentation in scheduler
passes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Extract bi_ec0_packed helper

Useful for scheduling decisions as well as packing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add passthrough register rewriting helper

Passthroughs are _required_ for correct scheduling, so we have to handle
this now. The legitimacy of using passthroughs is justified by the
constraint checks and verified with asserts at pack time.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Destructively schedule a single instruction

Wrapper to select the best legal instruction, pop it off the worklist,
update the clause/tuple states, and return it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Choose instructions to schedule

In the future we'll want a heuristic minimizing register pressure but
for in-order this will suffice.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add bi_instr_schedulable predicate

Using the previously defined checks for architectural scheduling
constraints, define one top-level predicate to check if an instruction
on the worklist is ready for scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add writes_reg predicate

ATEST is a bit of a wrinkle in this, so let's keep it in one place.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add T0/T1 constraint check

Not visible on real shaders yet, but it will be when we schedule
out-of-order (or implement 64-bit multiplication).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Validate reads_t

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add bi_count_succ_reads helper

The number of register writes in a tuple must be bounded by a number
based on the number of register reads in the succeeding tuple, since
writes and reads are interleaved. This helper calculates that number of
reads, noting that not every read actually counts - if the preceding
tuple writes to a read source, that will become a temporary instead of
consuming a register slot.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add bi_tuple_is_new_src

To determine the number of register reads in a tuple (which must be
bounded by 3, or 5 if you force writes), we need to count "new" sources:
those that are not already in a partially scheduled tuple.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add FAU update helper

This comes in destructive and nondestructive flavours, to be used to
insert an instruction into a tuple and check if an instruction is
insertable respectively. It is responsible for FAU slot matching.

It's annoying this sort of logic is duplicated in 3 places
(bi_lower_fau, here, and packing) but they each work with different sets
of assumptions...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add constant count estimates to scheduler

Needed to satisfy max constant constaints. These aren't precise but
they should be a good enough approximation for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Stub worklist routines

In the near future we'll schedule out-of-order via a dependendency graph
and worklist. For now, emulate in-order operation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Flatten block lists

From Midgard scheduler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add cubeface lowering

For the new schedule infrastructure. This supports multiple tuples per
clause, unlike the old hack lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Add scheduler data structures

To satisfy the numerous architectural scheduler constraints, quite a bit
of state is required per-tuple, per-clause, and per-block. These data
structures allow maintaining this state separate from the main IR
data structures, allowing for partial constructions and nondestructive
operations.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Include ATEST datum in the instruction

Rather than doing this at pack time like before, or adding extra
constraints to the already overcomplicated scheduler, let's just include
it like a regular FAU source.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Dead code eliminate per-channel

We already track the full liveness so this is a trivial optimization,
with an especial win for shaders reading only a subset of components of
gl_FragCoord.

More importantly, it's required for proper scheduling (in soft mode)
when vectors are used and some (but not all components) are promoted to
temporary registers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Cleanup terminal block check

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Print program size in shader-db

Less critical than other metrics, but still matters for instruction
cache hit rate, and worth being aware of.

And, fine, it makes the scheduler look like a bigger win on another
axis.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Fix shader prefetch size

The prefetch buffer size is larger than first thought, but includes
the final clause, so subtract the size of the final clause from the
prefetch size.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Return the size of the last clause from bi_pack

Will be used for calculating prefetch size.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>

pan/bi: Lower transcendentals on G71

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower FP32 transcendentals where required

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Fix bi quirks detection

There is no Bifrost v8...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Rename NO_FP32_TRANSCENDENTALS quirk

Make it more obvious what the issue is. "_FAST" is not a suffix on
Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower flog2 to a table and polynomial

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower FEXP2 with a table

Connor's code, not the blob's, amusingly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower frsq to Newton-Raphson

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Lower frcp to Newton-Raphson

For G71 but should work on any Bifrost, probably overlaps some CL stuff.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Fix FLOG_TABLE modifier handling

These should not be in a union together.

[Note: this does not need to be backported, since the affected
instruction is not emitted under any circumstances in the stable
branches]

Fixes: dd11e5076e6 ("pan/bi: Add new bi_instr data structure")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

pan/bi: Add bi_fmul_f32 convenience method

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>

v3dv: add a perf trace when a device is created with robust buffer access

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8913>

v3dv: serialize pipeline compilation when debugging shaders

It is possible to compile pipelines in multiple threads, but when we
are dumping debug information for shaders, we want all the outputs
serialized so we can make sense of it.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8913>

v3d/common: use spaces instead of TABs

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8913>

CI: always expose docs artifacts

This makes it easier to preview docs changes in merge-requests. Also
make sure we build the docs right away, rather than waiting for when
marge merges. This allows us to see the artifacts right away.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8398>

radv: stop using VM_ALWAYS_VALID on APUs

It seems that VM_ALWAYS_VALID means that all BOs must fit in
memory (VRAM+GTT) for each submission. This is causing a lot of
troubles when the total allocated memory is greater than the
available memory, especially on APUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8779>

radv: add radeon_winsys_bo::use_global_list

This will allow us to use the global BO list even without
RADEON_FLAG_PREFER_LOCAL_BO which can cause a lot of troubles
on APUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8779>

nouveau: print warning about unhandled cap only once

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8831>

radv: use less AMDGPU contexts by creating only one per queue priority

It should be more efficient. Suggested by Bas.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8878>

radv/winsys: stop zeroing radv_amdgpu_cs_request

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove unused fields in radv_amdgpu_cs_request

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: simplify the user fence logic for submission

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove unused radeon_bo_usage enum

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove useless is_local check in radv_amdgpu_cs_add_buffer()

radv_cs_add_buffer() already guarantees that and virtual buffers
are added via radv_amdgpu_cs_add_virtual_buffer().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove useless continue preamble CS for IBs path

It's only used for the sysmem path which is GFX6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: remove the radv_amdgpu_winsys_bo::ws indirection

This saves a 64-bit pointer from radv_amdgpu_winsys_bo and it's
also common to pass a winsys pointer as the first parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

radv/winsys: use an array for the global BO list instead of a list

This allows to remove one 64-bit pointer from radv_amdgpu_winsys_bo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>

Revert "broadcom/compiler: improve generation of if conditions"

This reverts commit 93f8f83a95383e38769bca8cd3c236d3b1c4c87f.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8903>

ci/freedreno: Run a3xx gles3 in parallel and increase coverage.

It seems that recent fixes have made its results stable (other than
existing flakiness in texturegrad), so we can use all the CPUs and a
couple more boards and get more coverage.

Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8787>

ci/freedreno: bump VK coverage to 1/4 of the CTS.

With the runner fixes, we were down to 2 minutes of boot time and 2
minutes of CTS time for a total of 4 minutes.  We've got plenty of time
budget now to increase our coverage.

Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8787>

ci/deqp: Bump runner to 0.5.1 for recent runtime perf improvements.

3 commits in 0.5.0:

- 20-40s savings on many of our CI runs by dropping the clever test size
  scaling code.

- Even bigger savings (especially on deqp-vk runs) by increasing maximuim
  test group size (~1/4 of runtime was spawning deqp on cheza, that cost
  is cut by ~75%)

- No more needing to manually set MESA_DEBUG=silent

2 commits in 0.5.1:

- Fixed automatic thread pool sizing to keep all CPUs busy (thanks for
  catching that Bas!).

- Automatically size down test groups on short test lists and many CPUs,
  so split the list evenly between CPUs (such as on freedreno -options
  jobs).

Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8787>

nir/algebraic: Partially revert 3f782cdd2591

I'm not sure what the logic was, but there is no opportunity for
anything to flush to zero here.  'a' is a Boolean value, and b2f
produces 1.0 or 0.0.

This was originally part of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3765/.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: Andres Gomez <agomez@igalia.com>
Cc: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8910>

nir/algebraic: add patterns for a >> #b << #b and a << #b >> #b

Commit 5476d181830 ("nir/algebraic: add patterns for a >> #b << #b")
added the ushr version, but it missed the ishr.  A bunch of compute
shaders with stores to shared storage generate the ishr pattern.

Enabling this optimization also enables the iadd/iand reassociation
(right after this hunk), and that enables merging of stores to shared
storage.  A couple shaders have spills and fills hurt on some
platforms.  These all occur in shaders that also have SENDs helped.
On Gen9 and Gen11, the helped SENDs more than makes up for the extra
spills and fills.

On Gen7 and Gen8, it's not as clear.  All of the shaders affected are
compute shaders in DiRT Rally 2 or Bioshock Inifinite.  The most
affected Bioshock shader on Broadwell looks like:

Before: CS SIMD8 shader: 1335 inst, 0 loops, 22411 cycles, 42:36 spills:fills, 159 sends, scheduled with mode lifo, Promoted 2 constants, compacted 21360 to 16528 bytes.

After:  CS SIMD8 shader: 1175 inst, 0 loops, 25916 cycles, 96:135 spills:fills, 72 sends, scheduled with mode lifo, Promoted 2 constants, compacted 18800 to 13648 bytes.

The results on Haswell and Ivy Bridge are similar.  Given that there
are only 2 promoted constants, MR !7698 won't have any effect.

There were no statistically significant changes on Gen9+ in Bioshock in
our performance CI.  Gen8 isn't in that CI, and DiRT Showdown 2 is also
not included in that CI.  It is possible that these shaders aren't used
in the settings or demos used in the CI.

The other pattern, which switches the order of the shifts, only helps a
couple shaders.  If I wasn't already adding another pattern, I
definitely wouldn't bother with that one.

v2: s/ishr/ushr/ in the replacement for the ushr pattern.  Noticed by
Rhys.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tiger Lake
total instructions in shared programs: 21052760 -> 21049269 (-0.02%)
instructions in affected programs: 59497 -> 56006 (-5.87%)
helped: 46
HURT: 0
helped stats (abs) min: 2 max: 552 x̄: 75.89 x̃: 53
helped stats (rel) min: 0.28% max: 43.43% x̄: 5.87% x̃: 4.10%
95% mean confidence interval for instructions value: -108.96 -42.82
95% mean confidence interval for instructions %-change: -8.38% -3.35%
Instructions are helped.

total cycles in shared programs: 855229761 -> 855148518 (<.01%)
cycles in affected programs: 8491373 -> 8410130 (-0.96%)
helped: 33
HURT: 15
helped stats (abs) min: 42 max: 26940 x̄: 6200.70 x̃: 4329
helped stats (rel) min: 0.09% max: 38.78% x̄: 7.97% x̃: 4.29%
HURT stats (abs)   min: 2 max: 18132 x̄: 8225.33 x̃: 7288
HURT stats (rel)   min: <.01% max: 13.37% x̄: 5.72% x̃: 4.53%
95% mean confidence interval for cycles value: -4331.52 946.40
95% mean confidence interval for cycles %-change: -6.78% -0.61%
Inconclusive result (value mean confidence interval includes 0).

total sends in shared programs: 989947 -> 989694 (-0.03%)
sends in affected programs: 523 -> 270 (-48.37%)
helped: 5
HURT: 0
helped stats (abs) min: 9 max: 87 x̄: 50.60 x̃: 37
helped stats (rel) min: 25.71% max: 54.72% x̄: 43.49% x̃: 42.53%
95% mean confidence interval for sends value: -93.95 -7.25
95% mean confidence interval for sends %-change: -58.48% -28.50%
Sends are helped.

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 20033498 -> 20030552 (-0.01%)
instructions in affected programs: 59220 -> 56274 (-4.97%)
helped: 48
HURT: 0
helped stats (abs) min: 1 max: 465 x̄: 61.38 x̃: 39
helped stats (rel) min: 0.03% max: 42.27% x̄: 5.19% x̃: 3.90%
95% mean confidence interval for instructions value: -89.57 -33.18
95% mean confidence interval for instructions %-change: -7.49% -2.89%
Instructions are helped.

total cycles in shared programs: 979993675 -> 979840773 (-0.02%)
cycles in affected programs: 6738454 -> 6585552 (-2.27%)
helped: 46
HURT: 0
helped stats (abs) min: 42 max: 6265 x̄: 3323.96 x̃: 3579
helped stats (rel) min: 0.09% max: 37.38% x̄: 4.34% x̃: 2.39%
95% mean confidence interval for cycles value: -3664.70 -2983.21
95% mean confidence interval for cycles %-change: -6.63% -2.06%
Cycles are helped.

total spills in shared programs: 10659 -> 10661 (0.02%)
spills in affected programs: 36 -> 38 (5.56%)
helped: 1
HURT: 1

total fills in shared programs: 11551 -> 11551 (0.00%)
fills in affected programs: 70 -> 70 (0.00%)
helped: 1
HURT: 1

total sends in shared programs: 1032117 -> 1031785 (-0.03%)
sends in affected programs: 711 -> 379 (-46.69%)
helped: 5
HURT: 0
helped stats (abs) min: 18 max: 87 x̄: 66.40 x̃: 74
helped stats (rel) min: 27.69% max: 54.72% x̄: 44.49% x̃: 44.31%
95% mean confidence interval for sends value: -101.79 -31.01
95% mean confidence interval for sends %-change: -58.42% -30.55%
Sends are helped.

Broadwell
total instructions in shared programs: 17865005 -> 17862757 (-0.01%)
instructions in affected programs: 66438 -> 64190 (-3.38%)
helped: 49
HURT: 0
helped stats (abs) min: 1 max: 266 x̄: 45.88 x̃: 39
helped stats (rel) min: 0.03% max: 11.99% x̄: 3.73% x̃: 3.92%
95% mean confidence interval for instructions value: -59.15 -32.61
95% mean confidence interval for instructions %-change: -4.35% -3.12%
Instructions are helped.

total cycles in shared programs: 1031298803 -> 1031219023 (<.01%)
cycles in affected programs: 7253602 -> 7173822 (-1.10%)
helped: 45
HURT: 2
helped stats (abs) min: 18 max: 7828 x̄: 1928.33 x̃: 1918
helped stats (rel) min: <.01% max: 10.51% x̄: 1.58% x̃: 1.31%
HURT stats (abs)   min: 3490 max: 3505 x̄: 3497.50 x̃: 3497
HURT stats (rel)   min: 15.56% max: 15.64% x̄: 15.60% x̃: 15.60%
95% mean confidence interval for cycles value: -2174.88 -1220.01
95% mean confidence interval for cycles %-change: -2.00% 0.30%
Inconclusive result (%-change mean confidence interval includes 0).

total spills in shared programs: 20799 -> 20924 (0.60%)
spills in affected programs: 843 -> 968 (14.83%)
helped: 0
HURT: 4

total fills in shared programs: 27110 -> 27334 (0.83%)
fills in affected programs: 1824 -> 2048 (12.28%)
helped: 1
HURT: 4

total sends in shared programs: 1017935 -> 1017603 (-0.03%)
sends in affected programs: 711 -> 379 (-46.69%)
helped: 5
HURT: 0
helped stats (abs) min: 18 max: 87 x̄: 66.40 x̃: 74
helped stats (rel) min: 27.69% max: 54.72% x̄: 44.49% x̃: 44.31%
95% mean confidence interval for sends value: -101.79 -31.01
95% mean confidence interval for sends %-change: -58.42% -30.55%
Sends are helped.

Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs: 16397496 -> 16395411 (-0.01%)
instructions in affected programs: 59384 -> 57299 (-3.51%)
helped: 49
HURT: 0
helped stats (abs) min: 1 max: 208 x̄: 42.55 x̃: 39
helped stats (rel) min: 0.03% max: 8.18% x̄: 3.74% x̃: 3.91%
95% mean confidence interval for instructions value: -53.59 -31.51
95% mean confidence interval for instructions %-change: -4.24% -3.23%
Instructions are helped.

total cycles in shared programs: 1035483504 -> 1035397592 (<.01%)
cycles in affected programs: 9379739 -> 9293827 (-0.92%)
helped: 45
HURT: 4
helped stats (abs) min: 10 max: 5600 x̄: 2164.51 x̃: 2350
helped stats (rel) min: <.01% max: 11.61% x̄: 1.93% x̃: 1.56%
HURT stats (abs)   min: 2 max: 5756 x̄: 2872.75 x̃: 2866
HURT stats (rel)   min: <.01% max: 24.65% x̄: 12.29% x̃: 12.26%
95% mean confidence interval for cycles value: -2293.06 -1213.56
95% mean confidence interval for cycles %-change: -2.42% 0.88%
Inconclusive result (%-change mean confidence interval includes 0).

total spills in shared programs: 17672 -> 17803 (0.74%)
spills in affected programs: 364 -> 495 (35.99%)
helped: 2
HURT: 2

total fills in shared programs: 20752 -> 20937 (0.89%)
fills in affected programs: 656 -> 841 (28.20%)
helped: 2
HURT: 2

total sends in shared programs: 1044703 -> 1044450 (-0.02%)
sends in affected programs: 523 -> 270 (-48.37%)
helped: 5
HURT: 0
helped stats (abs) min: 9 max: 87 x̄: 50.60 x̃: 37
helped stats (rel) min: 25.71% max: 54.72% x̄: 43.49% x̃: 42.53%
95% mean confidence interval for sends value: -93.95 -7.25
95% mean confidence interval for sends %-change: -58.48% -28.50%
Sends are helped.

No changes on Gen6 or earlier GPUs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8852>

nir/algebraic: Fix a >> #b << #b for sizes other than 32-bit

The base mask previously used was 0xffffffff.  This is not correct (but
should still work) for 16-bit and 8-bit values, but it means the high
32-bits of 64-bit values will get chopped off.

Instead of just restricting the pattern to 32-bits (as was done before
00b28a50b2c), this extends the optimization in two ways:

1. Make it correct for other bit sizes.
2. Make it work for arbitrary shift counts.

This has the added benefit of reducing the number of patterns actually
added (7 previously, 4 now).

The "Reassociate for improved CSE" part is just reverted to its
pre-00b28a50b2c behavior.  I doubt that pattern is likely to have much
impact outside 32-bits.

This change fixes the piglit tests
tests/spec/arb_gpu_shader_int64/fs-shl-of-shr-int64.shader_test and
tests/spec/arb_gpu_shader_int64/fs-iand-of-iadd-int64.shader_test.

All of the shaders helped in shader-db are vertex shaders on platforms
with vector-oriented vertex processing.  The shaders contain ((x >> 16)
<< 16).  These platforms set lower_extract_word, so the optimization
that transforms (x >> 16) to extract_u16 doesn't trigger.  With only ~60
shaders involved, I didn't bother trying to add extract_XYZ versions of
these patterns to try to get those cases.

Fixes: 00b28a50b2c ("nir/algebraic: trivially enable existing 32-bit patterns for all bit sizes")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Haswell and earlier Intel GPUs had simlar results. (Haswell shown)
total instructions in shared programs: 16397554 -> 16397496 (<.01%)
instructions in affected programs: 7961 -> 7903 (-0.73%)
helped: 58
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.36% max: 1.89% x̄: 0.99% x̃: 0.78%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -1.13% -0.85%
Instructions are helped.

total cycles in shared programs: 1035483770 -> 1035483504 (<.01%)
cycles in affected programs: 75922 -> 75656 (-0.35%)
helped: 44
HURT: 2
helped stats (abs) min: 2 max: 12 x̄: 6.14 x̃: 2
helped stats (rel) min: 0.05% max: 1.67% x̄: 0.87% x̃: 0.72%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.06% max: 0.06% x̄: 0.06% x̃: 0.06%
95% mean confidence interval for cycles value: -7.28 -4.29
95% mean confidence interval for cycles %-change: -1.03% -0.63%
Cycles are helped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8852>

zink: force 4 component formats for samplerview/render textures

this fixes a bunch of issues with 3-component formats, which aren't supported
for various operations on certain drivers

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8697>

android: radv: fix building error in radv_android.c

Fixes the following building error:

external/mesa/src/amd/vulkan/radv_android.c:752:77: error: too few arguments to function call, expected 4, have 3
                VkResult result = radv_image_create_layout(device, create_info, mem->image);
                                  ~~~~~~~~~~~~~~~~~~~~~~~~                                ^
external/mesa/src/amd/vulkan/radv_private.h:2175:1: note: 'radv_image_create_layout' declared here
VkResult
^
1 error generated.

Fixes: 7f7da82dbb78 ("radv: Add image layout with drm format modifiers.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8899>

android: radv: port to using common dispatch code.

Fixes the following building error in Android:

FAILED: ninja: 'external/mesa/src/amd/vulkan/radv_entrypoints_gen.py',
needed by 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_radv_common_intermediates/radv_entrypoints.c',
missing and no known rule to make it

Fixes: 23f8ca0c9dba ("radv: port to using common dispatch code.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8899>

nouveau/nv50: fix linear buffer alignment for scan-out/cursors

The hardware can only scan-out linear buffers with a pitch
aligned to 256. It can only use packed buffers for cursors.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8500>

nouveau/nvc0: fix linear buffer alignment for scan-out/cursors

The hardware can only scan-out linear buffers with a pitch
aligned to 256. It can only use packed buffers for cursors.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Closes: https://gitlab.freedesktop.org/drm/nouveau/-/issues/36
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8500>

nouveau: reinstate fencing on screen destroy

As it turns out, the wait is required as the driver expects for
rendering to be quiesced on exit. This can trigger channel failures,
which in turn trigger recovery. This can fail and destroy the whole
system.

Fixes: 28a781323fb ("nouveau: change fence destruction logic on screen destroy")
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4223
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8867>

ci: remove nouveau from shader-db runs

This is needed since we're about to reinstate the fencing mechanism on
screen destruction. Until we figure out another way to handle it, this
will cause hangs on exit with the shim.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable # 21.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8867>

radv: Improve spilling on discrete GPUs.

The linked bug gets better performance and I personally verified
better spilling performance on HZD so let us make this step for now.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3183
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3698
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6833>

android: iris: implement iris layer of INTEL_MEASURE

Fixes the following building errors in Android:

FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/LINKED/gallium_dri.so
...
ld.lld: error: undefined symbol: _iris_measure_snapshot
ld.lld: error: undefined symbol: iris_init_batch_measure
ld.lld: error: undefined symbol: iris_measure_batch_end
ld.lld: error: undefined symbol: iris_destroy_batch_measure
ld.lld: error: undefined symbol: iris_destroy_ctx_measure
ld.lld: error: undefined symbol: iris_measure_frame_end
ld.lld: error: undefined symbol: iris_destroy_screen_measure
ld.lld: error: undefined symbol: iris_init_screen_measure

Fixes: e67b8f504b4c ("iris: implement iris layer of INTEL_MEASURE")

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8887>

android: anv: implement anv layer of INTEL_MEASURE

Fixes the following building errors in Android:

FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/vulkan.android-x86_intermediates/LINKED/vulkan.android-x86.so
...
ld.lld: error: undefined symbol: _anv_measure_add_secondary
ld.lld: error: undefined symbol: anv_measure_init
ld.lld: error: undefined symbol: anv_measure_destroy
ld.lld: error: undefined symbol: anv_measure_reset
ld.lld: error: undefined symbol: anv_measure_device_destroy
ld.lld: error: undefined symbol: anv_measure_device_init
ld.lld: error: undefined symbol: _anv_measure_submit
ld.lld: error: undefined symbol: anv_measure_acquire
ld.lld: error: undefined symbol: _anv_measure_snapshot
ld.lld: error: undefined symbol: _anv_measure_endcommandbuffer
ld.lld: error: undefined symbol: _anv_measure_beginrenderpass

Fixes: 4a2d9e44ff26 ("anv: implement anv layer of INTEL_MEASURE")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8887>

android: intel: Print GPU timing data based on INTEL_MEASURE

Fixes the following building errors in Android:

FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/vulkan.android-x86_intermediates/LINKED/vulkan.android-x86.so
...
ld.lld: error: undefined symbol: intel_measure_init
ld.lld: error: undefined symbol: intel_measure_state_changed
ld.lld: error: undefined symbol: intel_measure_snapshot_string
ld.lld: error: undefined symbol: intel_measure_gather
ld.lld: error: undefined symbol: intel_measure_frame_transition

Fixes: 0f4143ec3787 ("intel: Print GPU timing data based on INTEL_MEASURE")

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8887>

winsys/amdgpu: try not to skip any code with RADEON_NOOP=1 to test CPU perf

This enables more accurate estimation of the maximum achievable CPU-bound
performance.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

winsys/amdgpu: don't set unused usage for backing BOs of sparse BOs

This is never used.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

winsys/amdgpu: don't inc/dec num_active_ioctls for backing BOs of sparse BOs

It's not correct.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

winsys/amdgpu: move amdgpu_winsys_bo::use_reusable_pool to the u.real union

It's never true with slab and sparse buffers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

winsys/amdgpu: move amdgpu_winsys_bo::is_user_ptr to the u.real union

It's never true with slab and sparse buffers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

winsys/amdgpu: move amdgpu_winsys_bo::is_shared to the u.real union

It's never true with slab and sparse buffers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

winsys/amdgpu: move amdgpu_winsys_bo::cpu_ptr into the u.real union

It's never used with slab and sparse buffers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

winsys/amdgpu: pack amdgpu_winsys_bo::is_shared and protect it by a mutex

The initialization of abs_timeout fixes a warning that started appearing
with this commit.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>