Alyssa Rosenzweig [Tue, 19 Apr 2022 14:10:48 +0000 (10:10 -0400)]
panfrost: Adapt compute job emit for Valhall
Similar data structure, simpler packing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 14:09:28 +0000 (10:09 -0400)]
panfrost: Use common state emit for compute jobs
This reduces the "specialness" of the Bifrost compute job emit path. It's not
useful in its own right since we currently put compute jobs in their own batch.
This could be optimized.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 13:54:15 +0000 (09:54 -0400)]
panfrost: Don't fix up alpha test on Bifrost
Since
7d1d7cdf575 ("panfrost: Don't check alpha test in fs_required on
Bifrost+"), we don't use the alpha testing state on Bifrost. So the fixup isn't
needed either.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Thu, 7 Apr 2022 15:27:28 +0000 (11:27 -0400)]
panfrost: Port uniform/UBO logic to Valhall
Use Valhall descriptors, and report sizes so we can accurately inform the
hardware of sizes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Thu, 7 Apr 2022 15:26:30 +0000 (11:26 -0400)]
panfrost: Add helper to emit UBOs
Either as uniform remap table entries on Bifrost, or as simple buffer
descriptors on Valhall. The underlying hardware is different (and there are
compiler changes for load_ubo handling), but the high level UBO upload logic
does not have to care about that.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 5 Apr 2022 16:37:59 +0000 (12:37 -0400)]
panfrost: Compile libpanfrost for v9
Now that everything is ported.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Thu, 13 Jan 2022 22:42:15 +0000 (17:42 -0500)]
panfrost: Don't allocate storage for PSIZ on Valhall
It's implicit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 26 Apr 2022 14:13:14 +0000 (10:13 -0400)]
pan/blit: Support v9 data structures
Now that everything is appropriately refactored, we can support Valhall's data
structures in the blitter. Things look similar to Bifrost, but the RSD no longer
exists.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 26 Apr 2022 14:01:33 +0000 (10:01 -0400)]
pan/blit: Prepare for Valhall port
Valhall's data structures are organized differently. In particular, they don't
use RSDs. So we need to reshuffle the blitter's data structures so we can map to
Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 26 Apr 2022 14:06:02 +0000 (10:06 -0400)]
pan/blit: Generalize texture alignment
For Valhall compat.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 26 Apr 2022 14:02:15 +0000 (10:02 -0400)]
pan/blit: Compile blit shaders without IDVS
On Valhall, the fragment shader differs based on whether IDVS or the legacy
geometry flow is used be. In particular, varyings are accessed differently.
We use the legacy geometry flow for blitting on all GPUs, so indicate this in
the shader inputs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 14:15:01 +0000 (10:15 -0400)]
panfrost: Add texture features enum to v9.xml
Required to query texture features on Valhall. It's technically the same as
previous Malis (except for narrow ASTC), but conceptually it's different as
plane descriptors have superseded indexed pixel formats for block compressed
textures.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Adam Jackson [Mon, 7 Mar 2022 16:53:05 +0000 (11:53 -0500)]
docs: Update supported drivers for 22.x
nouveau doesn't support pre-nv30 anymore, pre-DX9 drivers are no longer
supported generally, and llvmpipe jits on more than just x86.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15489>
Adam Jackson [Thu, 10 Mar 2022 21:14:21 +0000 (16:14 -0500)]
docs: Note EGL enum allocation for EGL_EXT_present_opaque
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15489>
Jason Ekstrand [Mon, 25 Apr 2022 17:25:17 +0000 (12:25 -0500)]
vulkan: Use ALL_COMMANDS_BIT for waits/signals instead of ~0
This is a bit more accurate for what's going on and, while all Mesa
drivers today seem to be ok with extra bits, ensures we're passing a
valid Vulkan thing.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16145>
Jason Ekstrand [Mon, 25 Apr 2022 16:08:42 +0000 (11:08 -0500)]
vulkan: Set signals[i].stageMask = ALL_COMMANDS for QueueSubmit2 wrapping
My understanding of the signal masks is that they control what stages
must complete before the semaphore is signaled. Using 0 theoretically
means the semaphore could be signaled immediately without waiting on
anything. Use ~0 instead to say it depends on everything.
Fixes:
97f0a4494b97 ("vulkan: implement legacy entrypoints on top of VK_KHR_synchronization2")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16145>
David Heidelberg [Fri, 15 Apr 2022 15:18:32 +0000 (17:18 +0200)]
ci: skqp: update URL
The file and functionality isn't present in `main` branch anymore.
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15973>
Erik Faye-Lund [Tue, 19 Apr 2022 12:51:03 +0000 (14:51 +0200)]
panvk: quiet non-conformant warning on ci
This helper has built-in support to be quieted, which seems like a good
idea to do on ci.
We're already setting the env var in the CI environment, so no need to
do that here.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16033>
Erik Faye-Lund [Tue, 19 Apr 2022 12:50:47 +0000 (14:50 +0200)]
lavapipe: quiet non-conformant warning on ci
This helper has built-in support to be quieted, which seems like a good
idea to do on ci.
Let's enable the quieting while we're at it.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16033>
Sviatoslav Peleshko [Thu, 31 Mar 2022 13:44:15 +0000 (16:44 +0300)]
anv: workaround apps that assume full subgroups without specifying it
Without this we might choose 8 or 16 width, while the app assumes 32.
With subgroup operations it may cause wrong calculations and thus bugs.
Examples of such games are Aperture Desk Job and DOOM Eternal.
v2: Make it a driconf option instead of applying unconditionally, move
from brw_required_dispatch_width to brw_compile_cs
v3: Rename allow_assuming_full_subgroups -> assume_full_subgroups.
Include assume_full_subgroups value in anv_pipeline_hash_compute().
v4: Move actual workaround code from brw_fs.c -> anv_pipeline.c.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6171
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15708>
Rhys Perry [Mon, 25 Apr 2022 18:42:30 +0000 (19:42 +0100)]
radv: fix clearing of TRUNC_COORD with tg4 and immutable samplers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes:
15640e58d96 ("radv,aco: lower texture descriptor loads in NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16148>
Charmaine Lee [Thu, 10 Mar 2022 02:20:46 +0000 (18:20 -0800)]
gallium/util: Increase the debug_flush map depth to 64
Piglit tests fbo-generatemipmap-3d RGB9_E5 and
fbo-generatemipmap-cubemap array RGB9_E5 hit assert when debug_flush
is active. Increase the debug map depth to 64.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16061>
Zack Rusin [Tue, 8 Feb 2022 21:41:32 +0000 (16:41 -0500)]
svga: Add support for SVGAv3
SVGAv3 changes the PCI id due to differences in how PCI configuration
is handled - removal of VRAM and FIFO PCI resources, switch to MMIO
registers and MSI/MSI-X IRQ support but the 3D commands remain largely
the same.
This enables 3D/graphics acceleration support on SVGAv3.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16061>
Zack Rusin [Tue, 8 Feb 2022 21:03:21 +0000 (16:03 -0500)]
svga: Use direct maps when GB objects are present
SVGA device always supports direct maps which are preferable in all cases
because they avoid temporary surfaces and extra transfers. Furthermore
DMA transfers on devices with GB objects have undefined timing semantics.
Also the DMA transfers can not work on SVGAv3 because the device lacks
VRAM to be able to perform them.
Fix the last paths still using DMA transfers to make sure they're never
used on GB enabled configs. This fixes gnome-shell startup on SVGAv3.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Martin Krastev <krastevm@vmware.com>
Reviewed-by: Michael Banack <banackm@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16061>
Zack Rusin [Wed, 2 Mar 2022 19:08:09 +0000 (14:08 -0500)]
svga: finish readbacks before mapping resources
Flushing the command queue before mapping a resource is not enough
to guaruantee that the mapped content is not stale. We have to finish
to make sure that the gb readback actually updated the guest surface.
This fixes races in direct maps (map reads raced with gb readbacks)
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16061>
Zack Rusin [Mon, 16 Aug 2021 18:25:36 +0000 (14:25 -0400)]
svga: Don't try to build x86/x64 assembly on different arch's
svga used to use vmx backdoor directly to send logs to the host.
This functionality has been implemented in vmwgfx 2.17, but
to make sure we still work with old kernels the functionality
to use the backdoor directly has been kept.
There's no reason to port that code to arm since vmwgfx
implements it and arm64 (or other new platforms) would
depend on vmwgfx versions a lot newer than 2.17, so everywhere
but on x86/x64 it's fine to assume vmwgfx always support the host
logging ioctls.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Martin Krastev <krastevm@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16061>
Alyssa Rosenzweig [Sat, 23 Apr 2022 20:53:38 +0000 (16:53 -0400)]
pan/bi: Implement pack_uvec[24]_to_uint
This maps nicely to Mali's weirdo MKVEC, so implement it rather than
scalarizing. The scalarization wants an extract implemented which we don't have.
Fixes dEQP-VK.glsl.builtin.function.pack_unpack.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16120>
Alyssa Rosenzweig [Tue, 19 Apr 2022 16:46:43 +0000 (12:46 -0400)]
nir: Use u_worklist to back nir_block_worklist
u_worklist is nir_block_worklist, suitably generalized. All we need to do is
define the macros to translate between the APIs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16046>
Alyssa Rosenzweig [Tue, 19 Apr 2022 15:57:45 +0000 (11:57 -0400)]
util: Add a generic worklist implementation
Models a double-ended queue of elements from an a list. Based on NIR's worklist
data structure. This is useful in most backend compilers for data flow analysis.
Using this data structure has several advantages for backends:
* Simplicity, avoids open-coding a worklist data structure.
* Performance, the data structure is lighter weight than e.g sets
* Correctness, e.g. sets are nondeterministic and can cause random bugs.
Using a worklist approach at all is good for performance of liveness analysis
to avoid performing excess walks over the IR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16046>
Samuel Pitoiset [Mon, 25 Apr 2022 07:46:08 +0000 (09:46 +0200)]
radv: add an SQTT workaround for chips with disabled RBs
Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16133>
Mike Blumenkrantz [Mon, 25 Apr 2022 18:06:12 +0000 (14:06 -0400)]
vk/cache: unbreak vk_pipeline_cache_create with flags
long ago I fixed this in individual drivers
now I fix it in all drivers
Fixes:
591da987790 ("vulkan: Add a common VkPipelineCache implementation"
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16149>
Jason Ekstrand [Mon, 25 Apr 2022 17:12:10 +0000 (12:12 -0500)]
nir: Lower all bit sizes of usub_borrow
It's not clear why this is restricted to 32-bit besides that being the
only bit size where GLSL has an intrinsic for this. All drivers that
set this probably want it lowered for all bit sizes as far as I can
tell.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6353
Fixes:
8a3e3441802c ("nir/opt_algebraic: Fix some expressions with ambiguous bit sizes")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16146>
Vinson Lee [Mon, 25 Apr 2022 04:28:50 +0000 (21:28 -0700)]
panfrost: Fix memory leaks on unit test failures.
Change ASSERT_EQ to EXPECT_EQ to avoid aborting before freeing memory.
Fix defects reported by Coverity Scan.
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable tiled going out of scope leaks the storage it points to.
leaked_storage: Variable linear going out of scope leaks the storage it points to.
leaked_storage: Variable ref going out of scope leaks the storage it points to.
Fixes:
bb6c14a6978 ("panfrost: Unit test u-interleaved tiling routines")
Suggested-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16127>
Mike Blumenkrantz [Mon, 25 Apr 2022 12:48:15 +0000 (08:48 -0400)]
vulkan: bump layer api versions to current vk header version
should probably try to keep these in sync? maybe?
cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16138>
Michel Zou [Wed, 6 Apr 2022 18:09:27 +0000 (20:09 +0200)]
meson: call run_command with check=true
This avoids a warning in meson since the default value will change:
WARNING: You should add the boolean check kwarg to the run_command call.
It currently defaults to false,
but it will default to true in future releases of meson.
See also: https://github.com/mesonbuild/meson/issues/9300
It's probably best to use the new default (true) that the old (false)
Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15776>
Eric Engestrom [Mon, 18 Apr 2022 15:52:48 +0000 (16:52 +0100)]
meson: replace deprecated dep.get_pkgconfig_variable(...) with dep.get_variable(pkgconfig : ...)
The former is deprecated since meson 0.56, while the latter is available since meson 0.51, and we currently require meson 0.53+.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16012>
Pavel Ondračka [Sun, 24 Apr 2022 16:58:14 +0000 (18:58 +0200)]
r300: set PIPE_BIND_CONSTANT_BUFFER for const_uploader
Fixes constant uploads with nine.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5966
CC: mesa-stable
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16125>
Cristian Ciocaltea [Mon, 25 Apr 2022 13:33:18 +0000 (16:33 +0300)]
virgl/ci: Update checksums for some virgl iris traces
A few trace tests started to fail recently due to invalid checksums.
A visual inspection of the images didn't reveal a regression, hence
let's just update the expected checksums to match the actual values.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16141>
Cristian Ciocaltea [Mon, 25 Apr 2022 09:01:18 +0000 (12:01 +0300)]
virgl/ci: Rename virgl-lava-* jobs to virgl-iris-*
Rename 'virgl-lava-*' jobs to a more descriptive 'virgl-iris-*'.
Suggested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16141>
Alyssa Rosenzweig [Sat, 23 Apr 2022 23:04:43 +0000 (19:04 -0400)]
panvk: Lower shared memory
Copy the code. Fixes workgroup tests, now compute kernels should work properly
on Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16123>
Alyssa Rosenzweig [Sat, 23 Apr 2022 22:55:00 +0000 (18:55 -0400)]
panvk: Handle empty shaders gracefully
Fixes dEQP-VK.spirv_assembly.instruction.compute.shader_default_output.int.uninitialized
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16123>
Alyssa Rosenzweig [Sat, 23 Apr 2022 21:33:47 +0000 (17:33 -0400)]
pan/bi: Implement fquantize2f16
Implement as f2f32(f2f16(x)) with the conversions in flush-to-zero mode.
Accessing flush-to-zero mode on Bifrost is nontrivial: it is specified
per-clause, rather than per-instruction. I've opted to pipe support for ftz
clauses through the scheduler. This solution has two nice properties:
* It uses the native hardware for flushing subnormals, avoiding extra lowering.
* It's "smart" about scheduling around FTZ requirements, meaning we get good
code generated even for a shader that e.g. quantizes a vector.
With an unrelated scheduler fix, the *V2F32_TO_V2F16/+F16_TO_F32 operation fits
in a single tuple, minimizing the overhead of the special FTZ clause.
We'll have to do something a bit different for Valhall (FLUSH.f32), but we'll
worry about when we actually have PanVK brought up on Valhall.
Fixes dEQP-VK.spirv_assembly.instruction.compute.opquantize.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16123>
Alyssa Rosenzweig [Mon, 25 Apr 2022 14:28:29 +0000 (10:28 -0400)]
panvk: Consider primitive restart in index buffer walks
Fixes:
dEQP-VK.pipeline.input_assembly.primitive_restart.index_type_uint32.line_strip
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16140>
Alyssa Rosenzweig [Mon, 25 Apr 2022 14:24:24 +0000 (10:24 -0400)]
panvk: Respect line width
Fixes:
dEQP-VK.pipeline.input_assembly.primitive_topology.index_type_uint16.line_list
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16140>
Erik Faye-Lund [Mon, 25 Apr 2022 08:36:51 +0000 (10:36 +0200)]
vulkan: do not depend on alignof(void)
alignof(void) is a non-standard GCC extension, and it doesn't compile on
MSVC. But since the Windows CI has been disabled due to stability
issues, a breakage snuk in nevertheless.
Since alignof(char) works the same as alignof(void), let's pass char
instead of void here. That hides the GCC weirdness without doing any
functional changes.
Fixes:
591da987790 ("vulkan: Add a common VkPipelineCache implementation")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16134>
Erico Nunes [Sun, 24 Apr 2022 15:13:22 +0000 (17:13 +0200)]
ci: put lima farm back online
There was an issue with the network router in the lab, which
should be resolved now.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16135>
Italo Nicola [Wed, 13 Apr 2022 15:24:54 +0000 (12:24 -0300)]
mesa/st: call pipe->link_shader even if ir loaded from cache when linking
Previously, if the shader was already cached, the pipe->link_shader hook
wouldn't be called, and the gallium driver wouldn't know that shaders
were being linked.
This helps VirGL, because sometimes the guest shader cache can be hit,
while the host shader cache would be missed. VirGL uses this hook to
make the host immediately link shaders, instead of lazily linking them
when a draw call happens, which can degrade performance.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15927>
Marek Olšák [Sat, 23 Apr 2022 01:31:45 +0000 (21:31 -0400)]
radeonsi/ci: add polaris11 baseline
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16112>
Marek Olšák [Fri, 22 Apr 2022 18:16:52 +0000 (14:16 -0400)]
winsys/amdgpu: fix a mutex deadlock when we fail to create pipe_screen
Fixes:
2eb067db0fe - winsys/amdgpu: add a new winsys for the new kernel driver
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16112>
Marek Olšák [Fri, 22 Apr 2022 18:10:03 +0000 (14:10 -0400)]
radeonsi: fail to create pipe_screen if LLVM doesn't support the GPU
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16112>
Marek Olšák [Fri, 22 Apr 2022 17:14:04 +0000 (13:14 -0400)]
radeonsi: remove an obsolete comment about LLVM 14
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16112>
Marek Olšák [Fri, 22 Apr 2022 18:05:18 +0000 (14:05 -0400)]
ac/llvm: don't create the target machine if the LLVM processor is unsupported
If a processor is unsupported, LLVM chooses "tahiti", which hangs
everything except gfx6. Check for support manually.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16112>
Marek Olšák [Fri, 22 Apr 2022 18:04:32 +0000 (14:04 -0400)]
ac/llvm: remove unused LLVM helpers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16112>
Lionel Landwerlin [Wed, 13 Apr 2022 08:42:45 +0000 (11:42 +0300)]
anv: skip acceleration structure in binding table emission
With mutable descriptor types, we can end up in a situation where a
binding can be, for instance, both a UBO and an acceleration
structure.
While we can promote the UBO to a binding table entry and the shader
can use it, this isn't true of acceleration structures that have no
surface state. In that case just skip the entry. The shader is already
compiled to use the descriptor entry.
In the non mutable case, the entry will not be created by
anv_nir_apply_pipeline_layout.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
63e91148b7fe ("anv: Enable VK_VALVE_mutable_descriptor_type")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15969>
Mike Blumenkrantz [Fri, 22 Apr 2022 17:58:11 +0000 (13:58 -0400)]
zink: fix group memory barrier emission
same as glslang
cc: mesa-stable
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16108>
Konstantin Seurer [Wed, 20 Apr 2022 12:39:14 +0000 (14:39 +0200)]
radv: Fix lowering ignore_ray_intersection
Fixes dEQP-VK.ray_tracing_pipeline.misc.report_intersection_result
Fixes: c3d82a9 ("radv: Add pass to lower anyhit shader into an intersection shader.")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16056>
Lionel Landwerlin [Wed, 20 Apr 2022 16:29:08 +0000 (19:29 +0300)]
anv: fix acceleration structure descriptor template writes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
d258b0bf0e07 ("anv: Add support for binding acceleration structures")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16058>
Lionel Landwerlin [Wed, 20 Apr 2022 16:28:12 +0000 (19:28 +0300)]
anv: remove unused enum
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16058>
Samuel Pitoiset [Thu, 14 Apr 2022 10:57:44 +0000 (12:57 +0200)]
radv: remove redundant VK_PIPELINE_STAGE_2_TRANSFER_BIT for CP DMA idle
They are equivalent.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15943>
Samuel Pitoiset [Thu, 14 Apr 2022 07:20:14 +0000 (09:20 +0200)]
radv: clarify why STAGE_2_CLEAR_BIT needs to wait for CP DMA to be idle
To clarify that other clear operations like vkCmdFillBuffer() are
implicitly synchronized. So, STAGE_2_CLEAR_BIT is only needed for
vkCmdUpdateBuffer() in some rare cases (GFX10+ dGPUs with GTT BOs).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15943>
Lionel Landwerlin [Wed, 13 Apr 2022 12:53:51 +0000 (15:53 +0300)]
intel: fixup number of threads per EU on XeHP
Computations for indexing in-memory data structures for ray queries
depend on this.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
4f9141607f40 ("intel: Add device info for DG2")
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15925>
Samuel Pitoiset [Fri, 22 Apr 2022 08:13:56 +0000 (10:13 +0200)]
nir: mark XFB varyings as unmoveable to prevent them to be remapped
XFB varyings are considered as always active IO to prevent them to
be removed or compacted. Though, if the NIR linker doesn't mark XFB
varyings as unmoveable it still possible to remap other varyings to
the same location/component.
Fixes KHR-Single-GL46.enhanced_layouts.xfb_override_qualifiers_with_api
with Zink and a bunch of other dEQP XFB tests.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6301
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16092>
Samuel Pitoiset [Fri, 22 Apr 2022 07:50:16 +0000 (09:50 +0200)]
nir: fix marking XFB varyings as always active IO
Components need to be handled, otherwise if a shader has two XFB
varyings at the same location, only one will be marked as always active.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16092>
Samuel Pitoiset [Fri, 22 Apr 2022 13:15:33 +0000 (15:15 +0200)]
aco: fix load_barycentric_at_{sample,offset} on GFX6-7
The computation was wrong.
Fixes dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_offset.*
with Zink on GFX6 (Pitcairn).
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16099>
Samuel Pitoiset [Fri, 22 Apr 2022 08:45:26 +0000 (10:45 +0200)]
radv/ci: update the flakes list for GFX9 chips
Fixed since "ac/surface: fix an addrlib race condition on gfx9".
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16093>
Mike Blumenkrantz [Fri, 22 Apr 2022 13:05:26 +0000 (09:05 -0400)]
glsl/nir: set new_style_shadow for sparse tex ops as necessary
this needs the sparse result type, which is not the ir type
Fixes:
f4a972b7483 ("glsl/nir: convert sparse ir_texture to nir")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16097>
Mike Blumenkrantz [Thu, 21 Apr 2022 16:37:44 +0000 (12:37 -0400)]
aux/trace: make get_sparse_texture_virtual_page_size useful
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16097>
Mike Blumenkrantz [Thu, 21 Apr 2022 17:11:18 +0000 (13:11 -0400)]
mesa/st: clamp GL_RENDERBUFFER to GL_TEXTURE_2D for sparse queries
this is a legal query that cts uses, so don't just abort
Fixes:
b1c32a6c8c2 ("mesa: add ARB_sparse_texture query in glGetInternalformativ")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16097>
Konstantin Seurer [Sat, 2 Apr 2022 12:47:37 +0000 (14:47 +0200)]
radv: Clean up the accel-struct build shaders
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15648>
Konstantin Seurer [Wed, 30 Mar 2022 12:09:36 +0000 (14:09 +0200)]
radv: Build accaleration structures using LBVH
This sorts the leaf nodes along a morton curve before
creating the internal nodes. For reference:
https://developer.nvidia.com/blog/thinking-parallel-part-iii-tree-construction-gpu/
Ray query cts:
Test run totals:
Passed: 22418/23426 (95.7%)
Failed: 0/23426 (0.0%)
Not supported: 1008/23426 (4.3%)
Warnings: 0/23426 (0.0%)
Waived: 0/23426 (0.0%)
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15648>
Konstantin Seurer [Thu, 7 Apr 2022 13:39:52 +0000 (15:39 +0200)]
radv: Add the fuchsia radix sort
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15648>
Konstantin Seurer [Wed, 30 Mar 2022 12:01:38 +0000 (14:01 +0200)]
radv: Format radv_acceleration_structure.c
This is the result of running clang-format on the entire file.
Although this is not related to this MR, I decided to include
the formatting changes so I do not have to deal with them if
I work on this file in the future.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15648>
Konstantin Seurer [Sun, 10 Apr 2022 14:19:34 +0000 (16:19 +0200)]
radv: Make fill_buffer_shader non-static
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15648>
Konstantin Seurer [Sun, 10 Apr 2022 14:20:32 +0000 (16:20 +0200)]
radv: Use VAs in radv_meta_buffer.c
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15648>
Konstantin Seurer [Sun, 24 Apr 2022 13:11:37 +0000 (15:11 +0200)]
ci: Always install glslangValidator for build jobs
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15648>
Alyssa Rosenzweig [Tue, 19 Apr 2022 17:02:30 +0000 (13:02 -0400)]
pan/bi: Simplify bi_propagate_pass_flags
Worklist-based dataflow analysis is overkill, we can just do DFS.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16045>
Alyssa Rosenzweig [Sat, 23 Apr 2022 17:31:54 +0000 (13:31 -0400)]
meson: Ignore unused variables in release builds
Variables that are only used for assertions are considered unused in release
builds. Don't treat this as an error, since we build with -Werror even for
release in CI. This causes reasonable code to build and pass tests locally (and
therefore to be queued for merge by reasonable developers), but later fail in CI
due to a variable used only as an assertion. This pattern is common enough we
have an ASSERTED macro to workaround the behaviour, but failing a CI run to
have the author go back and add in the ASSERTED and re-queue later is a recipe
for frustration, wasted time, and wasted CI bandwidth.
Disable this behaviour to reduce CI friction.
In my view, sprinkling in ASSERTED clutters the code, rather than helps; I find
CI's insistence on doing so actively counterproductive. Developers are free to
continue doing so after this change. But this way CI won't fail merge requests
over it. After all, CI enforces policy, and we shouldn't have "mark variables
only used for assertions as ASSERTED" as policy. Let's pick our battles wisely
and improve CI's signal-to-noise ratio.
As an added benefit, this eliminates a class of defects where ASSERTED is used
incorrectly, e.g:
c91e3c6a428 ("util: Should not use ASSERTED in util_thread_get_time_nano")
3e22fc27af9 ("zink: remove incorrect ASSERTED macro")
0d08ce287bf ("pan/bi: Remove dated ASSERTED properties")
Note that actual unused variables will be caught by debug builds. It is expected
that developers do debug builds locally before ramming code through CI, so that
should be caught.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15582>
Marek Olšák [Tue, 19 Apr 2022 18:43:56 +0000 (14:43 -0400)]
ac/gpu_info: remove old and unused fields from radeon_info
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Sat, 2 Apr 2022 04:45:24 +0000 (00:45 -0400)]
ac,radeonsi: rework how scratch_waves is used and move it to ac_gpu_info.c
The addition of the "compute" parameter is for a future change.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Fri, 15 Apr 2022 06:16:07 +0000 (02:16 -0400)]
ac/llvm: rename tbuffer -> buffer where tbuffer instructions are not generated
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Fri, 15 Apr 2022 06:00:55 +0000 (02:00 -0400)]
ac/llvm: don't use tbuffer_store as a fallback for swizzled stores
This depends on the offset computation fix from:
"ac/llvm: remove inst_offset parameter from ac_build_buffer_store_dword"
v2: The instruction type is changed to MUBUF, which requires us to clear
DATA_FORMAT with ADD_TID_ENABLE.
Reviewed-by: Mihai Preda <mhpreda@gmail.com> (v1)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Fri, 15 Apr 2022 05:31:53 +0000 (01:31 -0400)]
ac/llvm: remove unused code from ac_llvm_build.c/h
One forward declaration didn't have an implementation.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Fri, 15 Apr 2022 05:30:15 +0000 (01:30 -0400)]
ac/llvm: remove immoffset parameter from ac_build_tbuffer_load_byte/short
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Fri, 15 Apr 2022 05:25:32 +0000 (01:25 -0400)]
ac/llvm: remove inst_offset parameter from ac_build_buffer_load
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Fri, 15 Apr 2022 05:18:44 +0000 (01:18 -0400)]
ac/llvm: use soffset correctly in ac_build_buffer_load
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Fri, 15 Apr 2022 05:08:16 +0000 (01:08 -0400)]
ac/llvm: remove inst_offset parameter from ac_build_buffer_store_dword
There was a bug that inst_offset was added to soffset in one codepath and
to voffset in all other codepaths. The correct behavior is to add it
to voffset.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Fri, 15 Apr 2022 04:11:10 +0000 (00:11 -0400)]
ac/llvm: remove immoffset parameter from ac_build_tbuffer_load
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Fri, 15 Apr 2022 04:05:33 +0000 (00:05 -0400)]
ac/llvm: remove immoffset parameter from ac_build_tbuffer_store
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Tue, 22 Mar 2022 13:02:14 +0000 (09:02 -0400)]
ac/llvm: add AC_WAIT_EXP for ac_build_waitcnt
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Tue, 22 Mar 2022 13:07:20 +0000 (09:07 -0400)]
ac: add more non-shadowed registers to the lists
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Tue, 22 Mar 2022 13:17:03 +0000 (09:17 -0400)]
ac/surface/tests: generalize and extend gfx10 tests
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Thu, 10 Mar 2022 22:43:04 +0000 (17:43 -0500)]
amd: document chips
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15966>
Marek Olšák [Mon, 27 Dec 2021 00:12:17 +0000 (19:12 -0500)]
ac/llvm: remove LLVM pass ac_optimize_vs_outputs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
Marek Olšák [Mon, 13 Dec 2021 01:50:58 +0000 (20:50 -0500)]
radeonsi: assign param export indices before compilation
This moves the logic out of LLVM-specific codepaths.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
Marek Olšák [Mon, 13 Dec 2021 02:20:09 +0000 (21:20 -0500)]
ac: add ac_nir_optimize_outputs, a NIR version of ac_optimize_vs_outputs
ac_optimize_vs_outputs is an LLVM IR pass, and it will be replaced by this.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
Marek Olšák [Tue, 4 Jan 2022 19:41:46 +0000 (14:41 -0500)]
radeonsi: move si_shader_info::stage into si_shader_selector
This will help me see all places where we use "info", which will
be moved from si_shader_selector to shader variants.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
Marek Olšák [Tue, 4 Jan 2022 18:34:16 +0000 (13:34 -0500)]
radeonsi: move most "info" fields from si_shader_selector into si_shader_info
It's where they should be, and future commits might require this.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
Marek Olšák [Mon, 20 Dec 2021 01:10:03 +0000 (20:10 -0500)]
radeonsi: gather pipe_stream_output_info from NIR intrinsics
This stops pipe_stream_output_info from create_*s_state context functions
because NIR contains everything and can do more advanced shader linking
this way.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
Marek Olšák [Mon, 13 Dec 2021 04:38:21 +0000 (23:38 -0500)]
radeonsi: apply key.ge.opt.kill_{outputs,pointsize,clipdistance} in NIR
This may be needed by ACO, but it doesn't do anything for LLVM yet other
than making the initial LLVM IR smaller.
It will be needed by a future commit, which rewrites ac_optimize_vs_outputs
in NIR, which relies on NIR matching the shader key.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
Marek Olšák [Tue, 4 Jan 2022 14:03:04 +0000 (09:03 -0500)]
radeonsi: use nir_shader_get_entrypoint in si_nir_scan_shader
The typecast is needed because nir is const.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
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