platform/upstream/Vulkan-LoaderAndValidationLayers.git
10 years agoAdd function to set an icd's dispatch table for subsequently created objects.
Jon Ashburn [Thu, 16 Oct 2014 21:48:50 +0000 (15:48 -0600)]
Add function to set an icd's dispatch table for subsequently created objects.

With layers the loaders dispatch table is used instead of the drivers dispatch
table.  The gpu objects were reflecting this change but not subsequent objects.
Tell the icd driver about the loader's dispatch table so it will use it on
object creation rather than the default  driver dispatch table.

10 years agoAdd xglEnumerateLayers function including support in layers.
Jon Ashburn [Wed, 15 Oct 2014 21:30:23 +0000 (15:30 -0600)]
Add xglEnumerateLayers function including support in layers.

Also add this call to xglbase (init.cpp) test.

10 years agoFixes to Basic and Generic layers to work singly with LD_PRELOAD
Jon Ashburn [Wed, 15 Oct 2014 18:08:33 +0000 (12:08 -0600)]
Fixes to Basic and Generic layers to work singly with LD_PRELOAD

10 years agoLayers initial prototype.
Jon Ashburn [Wed, 15 Oct 2014 01:15:22 +0000 (19:15 -0600)]
Layers initial prototype.

Includes  an auto generated layer (GenericLayer) that wraps  all api calls.
Includes a basic handwritten layer (basicLayer)  that wraps a few apis.
Adds xglGetProcAddr as a new api, which is used to chain layers together.
All layers and loader implement  a dispatch table.

10 years agoloader: initialize memory
Courtney Goeltzenleuchter [Tue, 28 Oct 2014 16:29:27 +0000 (10:29 -0600)]
loader: initialize memory

uninitialized use from by valgrind

10 years agointel: add INTEL_DEBUG=nocache
Chia-I Wu [Tue, 28 Oct 2014 03:19:36 +0000 (11:19 +0800)]
intel: add INTEL_DEBUG=nocache

INTEL_DEBUG=nocache flushes all caches after each draw call.  We may start
running into render corruptions as we feed more test cases to the driver.
This option allows us to know if the corruption is cache-related quickly.

10 years agointel: always emit DEPTH_STENCIL_STATE for meta
Chia-I Wu [Tue, 28 Oct 2014 03:40:29 +0000 (11:40 +0800)]
intel: always emit DEPTH_STENCIL_STATE for meta

DEPTH_STENCIL_STATE is always referenced by the hardware.

10 years agointel: add a missing WA in the meta path
Chia-I Wu [Tue, 28 Oct 2014 03:19:14 +0000 (11:19 +0800)]
intel: add a missing WA in the meta path

A scoreboard stall needs to be emitted prior to any change to "Maximum Number
of Threads" of 3DSTATE_PS.  If the normal draw path and the meta path
programmed the same value for the field, we probably could skip this WA.  But
let's play safe.

10 years agointel: fix clears with mipLevels > 1
Chia-I Wu [Tue, 28 Oct 2014 06:17:43 +0000 (14:17 +0800)]
intel: fix clears with mipLevels > 1

meta->dst.layer should be reset to range->baseArraySlice for each mip level.
Otherwise, we may render out-of-bound and cause screen corruptions.

10 years agointel: improve blob decoding
Chia-I Wu [Sat, 25 Oct 2014 05:59:45 +0000 (13:59 +0800)]
intel: improve blob decoding

The last few dwords were skipped if the total number of dwords was not a
multiple of 4.  Change the formatting for better readability.

10 years agointel: disable PS for depth/stencil clears
Chia-I Wu [Fri, 24 Oct 2014 07:34:07 +0000 (15:34 +0800)]
intel: disable PS for depth/stencil clears

We can set the Z coordinate of the clear rectangle to depth clear value and
set stencil reference value to stencil clear value.  Neither requires PS to be
enabled.

10 years agointel: create intel_ds_state for depth/stencil clears
Chia-I Wu [Fri, 24 Oct 2014 03:57:51 +0000 (11:57 +0800)]
intel: create intel_ds_state for depth/stencil clears

It controls whether depth, stencil, or both are cleared.

10 years agointel: use helper funtions in gen6_meta_depth_buffer()
Chia-I Wu [Fri, 24 Oct 2014 01:49:50 +0000 (09:49 +0800)]
intel: use helper funtions in gen6_meta_depth_buffer()

There are helper functions to emit depth-related hardware states.  Use them.

10 years agointel: allow depthWriteEnable to be independently enabled
Chia-I Wu [Fri, 24 Oct 2014 04:31:29 +0000 (12:31 +0800)]
intel: allow depthWriteEnable to be independently enabled

When depthTestEnable is false, the hardware works as if the depth test always
passes and depthWriteEnable can still be honored.  It is unclear what the API
intends to do, but let's follow the hardware for now.

10 years agointel: fix an assertion in create info copying
Chia-I Wu [Wed, 22 Oct 2014 17:38:26 +0000 (01:38 +0800)]
intel: fix an assertion in create info copying

XGL_VIEWPORT_STATE_CREATE_INFO has no header and we should not assert
info.header->next to be NULL.

10 years agointel: implement cmd_draw_meta()
Chia-I Wu [Fri, 17 Oct 2014 06:47:18 +0000 (14:47 +0800)]
intel: implement cmd_draw_meta()

It emits the necessary hardware states for a meta op.  Copying with
depth/stencil or multisample source is not supported yet.  Clearing
depth/stencil destination is also unsupported.

10 years agointel: convert resource operations to meta ops
Chia-I Wu [Fri, 17 Oct 2014 01:49:22 +0000 (09:49 +0800)]
intel: convert resource operations to meta ops

Convert xgl{Copy,Clear,Resolve}* to meta ops, and call cmd_draw_meta() to
execute them.

cmd_draw_meta() is no-op and will be fixed by the following commit.

10 years agointel: define meta ops
Chia-I Wu [Fri, 17 Oct 2014 01:49:16 +0000 (09:49 +0800)]
intel: define meta ops

Meta ops include copy, clear, and resolve.  We need a meta shader for each of
the meta ops, and the shaders should be created with intel_dev to avoid
recompilation and locking.

This commit creates only dummy meta shaders.  They should be replaced by real
ones when the compiler or assembler is ready.

10 years agointel: allow a writer to be a reloc target
Chia-I Wu [Sat, 18 Oct 2014 05:25:10 +0000 (13:25 +0800)]
intel: allow a writer to be a reloc target

This allows us to handle STATE_BASE_ADDRESS more elegantly while making reloc
processing slower because of a libdrm_intel limitation.  It is justified
though because

 - we have to move away from libdrm_intel at some point and
 - in xglCmdUpdateMemory, we want to stream the data to the dynamic state
   writer and make the dynamic state writer a reloc target.

10 years agoicd: add icd_format_is_equal()
Chia-I Wu [Mon, 20 Oct 2014 05:50:43 +0000 (13:50 +0800)]
icd: add icd_format_is_equal()

It returns true when the formats are equal.

10 years agointel: clean up cmd shader cache
Chia-I Wu [Tue, 14 Oct 2014 06:27:44 +0000 (14:27 +0800)]
intel: clean up cmd shader cache

Mainly to remove intel_cmd_shader.  There were intel_shader,
intel_pipeline_shader, and intel_cmd_shader.  When we saw a variable named,
say, fs, we could not relate it to its type immediately.  Getting rid of
intel_cmd_shader makes that easier.

This also gives us a nicer API.  The cache is now transparent and never fails
cmd building.

10 years agointel: emit everything at draw time
Chia-I Wu [Tue, 14 Oct 2014 05:22:31 +0000 (13:22 +0800)]
intel: emit everything at draw time

We do not perform any optimization on the command buffer yet.  Emit everything
at draw time makes things easier when we add meta ops (such as image copy).
Once we are more feature complete, we will revisit how command buffer
optimization should be done.

10 years agointel: fix color/depth attachments size mismatch
Chia-I Wu [Tue, 14 Oct 2014 05:37:21 +0000 (13:37 +0800)]
intel: fix color/depth attachments size mismatch

The drawing rectangle should be the intersection of all color attachments and
the depth attachment.  Merge cmd_bind_rt() and cmd_bind_ds() into
cmd_bind_attachments() so that we can do that.

Move state emission to emit_rt() and emit_ds().

10 years agointel: handle XGL_LAST_MIP_OR_SLICE
Chia-I Wu [Sat, 18 Oct 2014 04:47:35 +0000 (12:47 +0800)]
intel: handle XGL_LAST_MIP_OR_SLICE

The miplevel or slice count of XGL_IMAGE_SUBRESOURCE_RANGE can have the
special value XGL_LAST_MIP_OR_SLICE.

10 years agointel: fix 8x sample pattern
Chia-I Wu [Mon, 20 Oct 2014 06:55:20 +0000 (14:55 +0800)]
intel: fix 8x sample pattern

Use sample patterns defined by the spec and convert them to hardware patterns.
This fixes 8x sample pattern.

10 years agointel: Clear pointer after unmapping buffer
Courtney Goeltzenleuchter [Mon, 13 Oct 2014 23:03:12 +0000 (17:03 -0600)]
intel: Clear pointer after unmapping buffer

10 years agotests: Fix issue in tests where descriptor set mapping array not initialized
Jon Ashburn [Mon, 20 Oct 2014 19:37:31 +0000 (13:37 -0600)]
tests: Fix issue in tests where descriptor set mapping array not initialized

10 years agointel: Only check string if length > 0
Courtney Goeltzenleuchter [Mon, 13 Oct 2014 18:58:25 +0000 (12:58 -0600)]
intel: Only check string if length > 0

strncmp will return 0 (match) when given two different strings
and a length of 0. Changed code to only do the compare if
length > 0. Now properly handles empty environment variable or
one that has multiple commas in a row.

10 years agointel: Need to save copy of create_info
Courtney Goeltzenleuchter [Fri, 17 Oct 2014 22:21:35 +0000 (16:21 -0600)]
intel: Need to save copy of create_info

Valgrind found that base_dbg_copy_create_info was leaking
the copy of the create_info structure.

10 years agointel: Fix memory leak found by valgrind
Courtney Goeltzenleuchter [Fri, 26 Sep 2014 00:15:33 +0000 (18:15 -0600)]
intel: Fix memory leak found by valgrind

10 years agointel: Reset pointer after freeing memory
Courtney Goeltzenleuchter [Fri, 26 Sep 2014 00:14:53 +0000 (18:14 -0600)]
intel: Reset pointer after freeing memory

10 years agointel: fix memory leak spotted by valgrind
Courtney Goeltzenleuchter [Fri, 26 Sep 2014 00:13:21 +0000 (18:13 -0600)]
intel: fix memory leak spotted by valgrind

10 years agoicd: Fix incorrect return type
Courtney Goeltzenleuchter [Wed, 15 Oct 2014 00:14:31 +0000 (18:14 -0600)]
icd: Fix incorrect return type

10 years agointel: fix devid override
Chia-I Wu [Mon, 13 Oct 2014 08:21:39 +0000 (16:21 +0800)]
intel: fix devid override

10 years agointel: emit BINDING_TABLE_STATE for all stages
Chia-I Wu [Mon, 13 Oct 2014 07:44:06 +0000 (15:44 +0800)]
intel: emit BINDING_TABLE_STATE for all stages

We had emit_ps_binding_table() for PS.  It turned out it was generic enough to
do all stages.

10 years agointel: emit SAMPLER_STATE for all stages
Chia-I Wu [Mon, 13 Oct 2014 07:35:29 +0000 (15:35 +0800)]
intel: emit SAMPLER_STATE for all stages

We had emit_ps_samplers() for PS.  It turned out it was generic enough to do
all stages.

10 years agointel: fix for a semantic change in libdrm 2.4.57 and later
Chia-I Wu [Mon, 13 Oct 2014 05:32:37 +0000 (13:32 +0800)]
intel: fix for a semantic change in libdrm 2.4.57 and later

When a client does

  xglInitAndEnumerateGpus();
  xglCreateDevice();
  // do something

  // reinitialize without xglDestroyDevice() first!
  xglInitAndEnumerateGpus();
  xglCreateDevice();
  // do something else

the driver will

  open()
  close()
  open()
  close()

on the DRM device.  The problem is that the two open()s may return the same
value and confuse libdrm since 2.4.57 (specifically, commit 743af59669).
Making intel_winsys intel_gpu-owned allows the driver to do this instead

  open()
  intel_winsys_create_for_fd()
  intel_winsys_destroy()
  close()
  open()
  intel_winsys_create_for_fd()
  intel_winsys_destroy()
  close()

10 years agokmd: fix intel_bo_wait() on kernel 3.17
Chia-I Wu [Mon, 13 Oct 2014 05:20:11 +0000 (13:20 +0800)]
kmd: fix intel_bo_wait() on kernel 3.17

Kernel 3.17 (commit 5ed0bdf21a specifically) introduced an ABI breakage.

10 years agoFix loader icd_scan to Null terminate strings
Jon Ashburn [Fri, 3 Oct 2014 22:31:35 +0000 (16:31 -0600)]
Fix loader icd_scan to Null terminate strings

10 years agoRefactor test code to pull common section into functions
Tobin Ehlis [Tue, 7 Oct 2014 20:41:29 +0000 (14:41 -0600)]
Refactor test code to pull common section into functions

10 years agointel: add support for FF vertex fetch
Chia-I Wu [Wed, 8 Oct 2014 00:49:38 +0000 (08:49 +0800)]
intel: add support for FF vertex fetch

shaderEntityIndex is used to index pVertexBindingDescriptions instead of
pVertexAttributeDescriptions.  Not really sure how that works.

https://cvs.khronos.org/bugzilla/show_bug.cgi?id=12774#c26

10 years agoinclude: update xgl.h with FF vertex fetch
Chia-I Wu [Mon, 6 Oct 2014 07:07:25 +0000 (15:07 +0800)]
include: update xgl.h with FF vertex fetch

https://cvs.khronos.org/svn/repos/oglc/trunk/nextgen/proposals/IMG/xgl_vertex_input_description2_img.h

10 years agointel: fix untyped memory views on GEN6
Chia-I Wu [Wed, 8 Oct 2014 04:24:37 +0000 (12:24 +0800)]
intel: fix untyped memory views on GEN6

10 years agoicd: add icd_format_get_channel_count
Chia-I Wu [Wed, 8 Oct 2014 01:12:58 +0000 (09:12 +0800)]
icd: add icd_format_get_channel_count

10 years agointel: disable PCB
Chia-I Wu [Tue, 7 Oct 2014 07:40:38 +0000 (15:40 +0800)]
intel: disable PCB

XGL_LINK_CONST_BUFFER should be consumed by the compiler rather than blindly
pushed.

10 years agointel: disable HiZ
Chia-I Wu [Tue, 7 Oct 2014 06:45:05 +0000 (14:45 +0800)]
intel: disable HiZ

We are not quite there yet.

10 years agointel: emit samplers and image/memory views
Chia-I Wu [Mon, 6 Oct 2014 16:34:13 +0000 (00:34 +0800)]
intel: emit samplers and image/memory views

Emit SAMPLER_STATE and SURFACE_STATE for texturing.

10 years agoAdded graphiviz dot and png files to visualize some API details
Tobin Ehlis [Mon, 6 Oct 2014 15:07:53 +0000 (09:07 -0600)]
Added graphiviz dot and png files to visualize some API details

10 years agoFix size as input/output parameter for various xglGet calls.
Jon Ashburn [Thu, 25 Sep 2014 20:36:58 +0000 (14:36 -0600)]
Fix size as input/output parameter for various xglGet calls.

10 years agoFix size parameter for xglGetFormatInfo test utilities.
Jon Ashburn [Wed, 24 Sep 2014 20:17:04 +0000 (14:17 -0600)]
Fix size parameter for xglGetFormatInfo test utilities.

10 years agoFix size as input parameter to xglGetGpuInfo() for test utilities
Jon Ashburn [Wed, 24 Sep 2014 19:15:44 +0000 (13:15 -0600)]
Fix size as input parameter to xglGetGpuInfo() for test utilities

10 years agointel: check for xcb too
Chia-I Wu [Tue, 23 Sep 2014 07:36:53 +0000 (15:36 +0800)]
intel: check for xcb too

10 years agointel: do not require render node
Chia-I Wu [Thu, 18 Sep 2014 08:39:06 +0000 (16:39 +0800)]
intel: do not require render node

We can use the primary node for GPUs with an X display associated.

10 years agointel: add support for XGL_WSI_X11
Chia-I Wu [Mon, 15 Sep 2014 06:21:14 +0000 (14:21 +0800)]
intel: add support for XGL_WSI_X11

10 years agoadd stubs for XGL_WSI_X11
Chia-I Wu [Tue, 23 Sep 2014 02:37:23 +0000 (10:37 +0800)]
add stubs for XGL_WSI_X11

10 years agoinclude: add preliminary XGL_WSI_X11 proposal
Chia-I Wu [Tue, 23 Sep 2014 02:37:08 +0000 (10:37 +0800)]
include: add preliminary XGL_WSI_X11 proposal

It is built around DRI3 and Present.

10 years agointel: remove intel_fence_get_status()
Chia-I Wu [Tue, 23 Sep 2014 07:02:01 +0000 (15:02 +0800)]
intel: remove intel_fence_get_status()

It is equivalent to intel_fence_wait() with timeout set to 0.

10 years agotidy up the build system a bit
Chia-I Wu [Thu, 18 Sep 2014 09:05:09 +0000 (17:05 +0800)]
tidy up the build system a bit

10 years agodelete GitSHA1.c generation
Chia-I Wu [Thu, 18 Sep 2014 08:58:27 +0000 (16:58 +0800)]
delete GitSHA1.c generation

It is unused.  Could be revived anytime if found useful.

10 years agointel: set tiling before exporting
Chia-I Wu [Thu, 18 Sep 2014 08:11:36 +0000 (16:11 +0800)]
intel: set tiling before exporting

The remote gets the tiling of the bo from DRM_IOCTL_I915_GEM_GET_TILING.

10 years agointel: add intel_obj_bind_mem()
Chia-I Wu [Mon, 15 Sep 2014 07:12:06 +0000 (15:12 +0800)]
intel: add intel_obj_bind_mem()

Make intelBindObjectMemory() a wrapper to it.

10 years agointel: teach layout about scanout
Chia-I Wu [Mon, 15 Sep 2014 06:55:25 +0000 (14:55 +0800)]
intel: teach layout about scanout

10 years agointel: prepare for primary node support
Chia-I Wu [Mon, 15 Sep 2014 05:52:21 +0000 (13:52 +0800)]
intel: prepare for primary node support

We will be able to support primary nodes once we know how to talk to an X
server.

10 years agointel: use the common DRM subsystem scanner
Chia-I Wu [Mon, 15 Sep 2014 03:06:50 +0000 (11:06 +0800)]
intel: use the common DRM subsystem scanner

10 years agoicd: add an API to scan Linux DRM subsystem
Chia-I Wu [Mon, 15 Sep 2014 05:08:49 +0000 (13:08 +0800)]
icd: add an API to scan Linux DRM subsystem

It differs from the scanner in intel ICD in that both legacy (primary) nodes
and render nodes are supported.  And it does not open() any of them.

10 years agoxgl-generate: do not hardcode #include's
Chia-I Wu [Sat, 13 Sep 2014 05:36:06 +0000 (13:36 +0800)]
xgl-generate: do not hardcode #include's

Add core_headers to xgl.py and use it to generate #include's

10 years agoremove XGLConfig.h.in
Chia-I Wu [Sat, 13 Sep 2014 05:18:47 +0000 (13:18 +0800)]
remove XGLConfig.h.in

Unused.

10 years agoxgl: Remove mantle headers
Courtney Goeltzenleuchter [Thu, 11 Sep 2014 18:51:27 +0000 (12:51 -0600)]
xgl: Remove mantle headers

10 years agotests: Update render_test to use XglTestFramework class
Courtney Goeltzenleuchter [Thu, 4 Sep 2014 22:26:02 +0000 (16:26 -0600)]
tests: Update render_test to use XglTestFramework class

10 years agotests: Make test framework class useful for XGL testing
Courtney Goeltzenleuchter [Thu, 4 Sep 2014 22:24:19 +0000 (16:24 -0600)]
tests: Make test framework class useful for XGL testing

Add the class XglTestClass that is intended to be used by
XGL test programs and knows how to capture interesting
test events such as images.
This includes the ability to parse two command line options
--show-images: bring up a simple image window that will show any
images of note (those that an application says to record). Results
are saved so that the operator can scroll through the images
at the completion of the test.
--save-images: Output the image as a ppm file using the test name
as the file base name.

10 years agotests: Add map and unmap methods to the XglImage class
Courtney Goeltzenleuchter [Thu, 4 Sep 2014 22:23:35 +0000 (16:23 -0600)]
tests: Add map and unmap methods to the XglImage class

10 years agointel: upload viewport states separately
Chia-I Wu [Tue, 9 Sep 2014 05:48:03 +0000 (13:48 +0800)]
intel: upload viewport states separately

So that the item types are correctly set and enable the decoder to decode
them.

10 years agointel: improve command decoding
Chia-I Wu [Tue, 9 Sep 2014 04:07:37 +0000 (12:07 +0800)]
intel: improve command decoding

Decode both batch and state buffers.  Decoding is enabled with
INTEL_DEBUG=batch for now.  The functionality should be moved to the debug
layer in the future.

10 years agoicd: add u_uif
Chia-I Wu [Mon, 8 Sep 2014 16:23:07 +0000 (00:23 +0800)]
icd: add u_uif

For bit-preserving uint32_t to float type casting.

10 years agointel: rework cmd helpers
Chia-I Wu [Tue, 9 Sep 2014 02:48:33 +0000 (10:48 +0800)]
intel: rework cmd helpers

In the hope that the new helpers are easier to use.

An important change is that the units used for a writer are changed from
dwords to bytes.  Helpers may still use dwords when it is more natural.

10 years agointel: rework cmd buffer management
Chia-I Wu [Tue, 9 Sep 2014 02:32:59 +0000 (10:32 +0800)]
intel: rework cmd buffer management

Hopefully the new code is easier to follow and more robust.

10 years agointel: rename ptr_opaque to ptr
Chia-I Wu [Tue, 9 Sep 2014 02:25:46 +0000 (10:25 +0800)]
intel: rename ptr_opaque to ptr

It is void * and is opqaue already.

10 years agointel: make cmd writers an array
Chia-I Wu [Tue, 9 Sep 2014 01:43:21 +0000 (09:43 +0800)]
intel: make cmd writers an array

Replace batch, state, and kernel writers by an array of writers.

10 years agointel: improve XGL_PIPELINE_IA_STATE_CREATE_INFO handling
Chia-I Wu [Tue, 2 Sep 2014 05:20:59 +0000 (13:20 +0800)]
intel: improve XGL_PIPELINE_IA_STATE_CREATE_INFO handling

Make intel_pipeline smaller, and handle disableVertexReuse and
XGL_TOPOLOGY_PATCH.

10 years agointel: remove urb_read_length and max_*_threads
Chia-I Wu [Tue, 2 Sep 2014 05:27:48 +0000 (13:27 +0800)]
intel: remove urb_read_length and max_*_threads

Effectively revert 39e0021034175dd982ddce3764280b44e4545968 and
073e83cebec17d1774675960306be4022b2a4136, and redo
3d72e8ca3660ab372a27a7662db7d47b48fb6817

10 years agointel: really rename pipeline_rmap.c to pipeline_shader.c
Chia-I Wu [Tue, 2 Sep 2014 05:11:32 +0000 (13:11 +0800)]
intel: really rename pipeline_rmap.c to pipeline_shader.c

This commit was lost when I switched from an internal repo to github.

10 years agointel: rename rmap to pipeline rmap
Chia-I Wu [Tue, 2 Sep 2014 04:07:28 +0000 (12:07 +0800)]
intel: rename rmap to pipeline rmap

For consistency.

10 years agointel: shorten shader stage names
Chia-I Wu [Tue, 2 Sep 2014 03:01:03 +0000 (11:01 +0800)]
intel: shorten shader stage names

Use tcs, tes, and cs for tess control, tess eval, and compute.

10 years agointel: rename intel_pipe_shader to intel_pipeline_shader
Chia-I Wu [Tue, 2 Sep 2014 00:52:27 +0000 (08:52 +0800)]
intel: rename intel_pipe_shader to intel_pipeline_shader

It is initialized from XGL_PIPELINE_SHADER, and we already use intel_pipeline
for XGL_PIPELINE.

10 years agointel: intel_pipeline should not have XGL_PIPELINE_SHADER
Chia-I Wu [Tue, 2 Sep 2014 02:53:20 +0000 (10:53 +0800)]
intel: intel_pipeline should not have XGL_PIPELINE_SHADER

They may have a shorter lifespan.

10 years agointel: clean up pipeline shader building a bit
Chia-I Wu [Tue, 2 Sep 2014 02:03:19 +0000 (10:03 +0800)]
intel: clean up pipeline shader building a bit

10 years agointel: make all rmap functions static
Chia-I Wu [Tue, 2 Sep 2014 02:21:34 +0000 (10:21 +0800)]
intel: make all rmap functions static

10 years agointel: move shader building/tearing to pipeline_shader.c
Chia-I Wu [Tue, 2 Sep 2014 01:42:46 +0000 (09:42 +0800)]
intel: move shader building/tearing to pipeline_shader.c

10 years agointel: cs is a part of XGL_COMPUTE_PIPELINE_CREATE_INFO
Chia-I Wu [Tue, 2 Sep 2014 02:06:12 +0000 (10:06 +0800)]
intel: cs is a part of XGL_COMPUTE_PIPELINE_CREATE_INFO

We probably want to separate graphics and compute pipeline create info at some
point.

10 years agointel: remove gpu from intel_pipeline_create_info
Chia-I Wu [Tue, 2 Sep 2014 02:24:05 +0000 (10:24 +0800)]
intel: remove gpu from intel_pipeline_create_info

Make it flattened XGL_GRAPHICS_PIPELINE_CREATE_INFO proper.

10 years agointel: rename pipeline builder to pipeline create info
Chia-I Wu [Tue, 2 Sep 2014 01:32:46 +0000 (09:32 +0800)]
intel: rename pipeline builder to pipeline create info

It is flattened XGL_GRAPHICS_PIPELINE_CREATE_INFO after all.

10 years agoRevert "intel: rename intel_pipe_shader to intel_pipeline_shader"
Chia-I Wu [Tue, 2 Sep 2014 05:06:11 +0000 (13:06 +0800)]
Revert "intel: rename intel_pipe_shader to intel_pipeline_shader"

This reverts commit e47bf243b60c7195736ff86627a9f2a21d0e8104.  Wrong branch
pushed.

10 years agoRevert "intel: rename pipeline_rmap.c to pipeline_shader.c"
Chia-I Wu [Tue, 2 Sep 2014 05:05:27 +0000 (13:05 +0800)]
Revert "intel: rename pipeline_rmap.c to pipeline_shader.c"

This reverts commit 89de5d0c16558454f3f2f5f24fb096574845bb82.  Wrong branch
pushed.

10 years agointel: rename pipeline_rmap.c to pipeline_shader.c
Chia-I Wu [Tue, 2 Sep 2014 01:15:35 +0000 (09:15 +0800)]
intel: rename pipeline_rmap.c to pipeline_shader.c

10 years agointel: rename intel_pipe_shader to intel_pipeline_shader
Chia-I Wu [Tue, 2 Sep 2014 00:52:27 +0000 (08:52 +0800)]
intel: rename intel_pipe_shader to intel_pipeline_shader

It is initialized from XGL_PIPELINE_SHADER, and we already use intel_pipeline
for XGL_PIPELINE.

10 years agointel: remove unused pipeline defines
Chia-I Wu [Tue, 2 Sep 2014 00:50:14 +0000 (08:50 +0800)]
intel: remove unused pipeline defines

10 years agoupdate copyright information
Chia-I Wu [Tue, 2 Sep 2014 00:32:09 +0000 (08:32 +0800)]
update copyright information

To my best knowledge.

10 years agoxgl: Add build instructions
Courtney Goeltzenleuchter [Tue, 2 Sep 2014 00:05:45 +0000 (18:05 -0600)]
xgl: Add build instructions

10 years agoxgl: Add project readme
Courtney Goeltzenleuchter [Mon, 1 Sep 2014 23:18:57 +0000 (17:18 -0600)]
xgl: Add project readme

10 years agotests: clean up use of Image object to fix SEGV
Courtney Goeltzenleuchter [Mon, 1 Sep 2014 23:56:16 +0000 (17:56 -0600)]
tests: clean up use of Image object to fix SEGV