Martin Leung [Mon, 21 Feb 2022 02:44:26 +0000 (21:44 -0500)]
drm/amd/display: cleaning up smu_if to add future flexibility
This commit cleans up code that uses old variables and adds some SMU
interfaces for future flexibility.
Signed-off-by: Martin Leung <Martin.Leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Tue, 26 Apr 2022 18:29:15 +0000 (14:29 -0400)]
drm/amd/display: update disp pattern generator routine for DCN30
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Fri, 4 Mar 2022 14:34:58 +0000 (09:34 -0500)]
drm/amd/display: Updates for OTG and DCCG clocks
Use DTBCLK for valid pixel clock generation
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chaitanya Dhere [Mon, 11 Apr 2022 17:37:21 +0000 (13:37 -0400)]
drm/amd/display: FCLK P-state support updates
[Why]
Previously we used to send FCLK P-state enable messages upon each call
to update_clocks based on dml output. This resulted in increased message
transactions between DC and PMFW.
[How]
Update the code to check safe_to_lower status and send the message based
on dml input only on boot. This reduces message transactions. Also
remove other unwanted code based on current code status.
Signed-off-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Sun, 20 Feb 2022 19:33:56 +0000 (14:33 -0500)]
drm/amd/display: Introduce new update_clocks logic
[why]
DCN has sidebands to control some clocks, it is useful for clk_mgr to
always update the clocks it explicitly controls rather than skip them
because it enables more configurations to work without SMU
[how]
only skip handling clocks where SMU manages the frequency for clocks
with DENTIST sideband (DISP/DPP), only skip the voltage request when SMU
not available, but otherwise proceed normally
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jingwen Zhu [Tue, 15 Mar 2022 05:15:27 +0000 (13:15 +0800)]
drm/amd/display: set link fec status during init for DCN32
We can now enable FEC.
Signed-off-by: Jingwen Zhu <Jingwen.Zhu@github.amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Sun, 20 Feb 2022 18:58:51 +0000 (13:58 -0500)]
drm/amd/display: add new pixel rate programming
[why]
New dividers in DCCG need to be programmed depending
on encoder/stream type since pixels per clock in
OTG/DIO is different
DIO also needs additional programming depending on
pixels per clock
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Alvin Lee [Tue, 5 Apr 2022 18:46:30 +0000 (14:46 -0400)]
drm/amd/display: Remove W/A for ODM memory pins
[Description]
By default we can now set
ODM_MEM_VBLANK_PWR_MODE=1
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 24 May 2022 14:11:33 +0000 (10:11 -0400)]
drm/amdgpu: fix up comment in amdgpu_device_asic_has_dc_support()
LVDS support was implemented in DC a while ago. Just DAC
support is left to do.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Thu, 7 Apr 2022 16:04:42 +0000 (12:04 -0400)]
drm/amd/display: do not override CURSOR_REQ_MODE when SubVP is not enabled
[Why]
HUBP_UNBOUNDED_REQ_MODE and CURSOR_REQ_MODE are normally set together.
In hubp32_prepare_subvp_buffering() call, CURSOR_REQ_MODE is set based on
whether SubVP is enabled or not. For non MPO case, both REQ_MODE
registers are set to 1. But since SubVP is not enabled, then
CURSOR_REQ_MODE is set to 0, overriding the previous value.
[How]
Do not set CURSOR_REQ_MODE to 0 if SubVP is not enabled. This
will allow CURSOR_REQ_MODE to stay as 1 in the non MPO case.
Add note to follow up and check case for single pipe MPO and
SubVP enabled as this would cause both REQ_MODE registers to be
set to 0 but SubVP enabled would override CURSOR_REQ_MODE to 1.
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Mon, 30 May 2022 11:42:25 +0000 (14:42 +0300)]
drm/amdgpu: delete duplicate condition in gfx_v11_0_soft_reset()
We know that "grbm_soft_reset" is true because we're already inside an
if (grbm_soft_reset) condition. No need to test again.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 26 May 2022 16:04:38 +0000 (12:04 -0400)]
drm/amdgpu/swsmu: use new register offsets for smu_cmn.c
Use the per asic offsets so the we don't have to have
asic specific logic in the common code.
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Mon, 11 Apr 2022 14:29:57 +0000 (10:29 -0400)]
drm/amd/display: change dsc image width cap for dcn32 and dcn321
Set appropriate caps for DCN3.2.x.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 26 May 2022 15:55:36 +0000 (11:55 -0400)]
drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
So we can eventaully use them in the common smu code for
accessing the SMU mailboxes without needing a lot of
per asic logic in the common code.
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Wed, 13 Apr 2022 21:54:19 +0000 (17:54 -0400)]
drm/amd/display: Disable DTB Ref Clock Switching in dcn32
[How & Why]
To be enabled once PMFW supports it.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 26 May 2022 16:48:51 +0000 (12:48 -0400)]
drm/amdgpu/gmc11: enable AGP aperture
Enable the AGP aperture on chips with GMC v11.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 24 May 2022 14:27:33 +0000 (10:27 -0400)]
drm/amdgpu: convert nbio_v2_3_clear_doorbell_interrupt() to IP version
Check IP version rather than asic type.
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Mon, 18 Apr 2022 18:39:20 +0000 (14:39 -0400)]
drm/amd/display: set dram speed for all states
[WHY?]
If higher states have memory speed set to 0 MT/s currently they do not get set
to the highest value which can cause validation failures.
[HOW?]
Set unpopulated higher states to max value.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 24 May 2022 13:55:51 +0000 (09:55 -0400)]
drm/amdgpu: simplify the logic in amdgpu_device_parse_gpu_info_fw()
Drop all of the extra cases in the default case.
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 24 May 2022 14:02:16 +0000 (10:02 -0400)]
drm/amdgpu: convert sienna_cichlid_populate_umd_state_clk() to use IP version
Rather than asic type.
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fangzhi Zuo [Tue, 19 Apr 2022 19:49:48 +0000 (15:49 -0400)]
drm/amd/display: Halve DTB Clock Value for DCN32
VBIOS default clock value was halved, so the hardcoded dtb value should be
halved as well.
dtb clock should come from SMU eventually, but now dtb clock switching is not
fully supported yet in SMU.
Halve the dtb hardcoded value for now to have UHBR10 light up. Will rely on
SMU for dtb clock switching once available. The w/a is for DCN32 only, DCN321
should adopt the original value.
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Thu, 14 Apr 2022 21:03:28 +0000 (17:03 -0400)]
drm/amd/display: Add additional guard for FCLK pstate message for DCN321
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Fri, 20 May 2022 13:33:29 +0000 (21:33 +0800)]
drm/amdgpu: fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7
This patch will fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7.0.
NBIO v7.7.0 uses a new reg function -- Common SDMA to allow a common
doorbell range for all SDMA queues, this is different to the old
NBIO version. This patch will add configuration for CSDMA and enable
SDMA doorbell function.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Fri, 20 May 2022 14:27:57 +0000 (22:27 +0800)]
drm/amdgpu: add CSDMA reg offsets for NBIO v7.7.0
This patch will add CSDMA reg offsets for NBIO v7.7.0
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 18 May 2022 14:05:03 +0000 (22:05 +0800)]
drm/amdgpu: add apu sequence in the imu v11
APU required to issue the enable GFX IMU message after IMU reset.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 18 May 2022 13:19:32 +0000 (21:19 +0800)]
drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu function
GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 17 May 2022 06:58:41 +0000 (14:58 +0800)]
drm/amdgpu/pm: update MP v13_0_4 smu message register marco
Update MP v13_0_4 register macro for SMU message
v2: squash in missed case (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 12 May 2022 08:13:07 +0000 (16:13 +0800)]
drm/amdgpu: add mmhub v3_0_1 ip block
This adds mmhub v3_0_1 ip block support
v2: rebase (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 12 May 2022 08:03:34 +0000 (16:03 +0800)]
drm/amdgpu: add mmhub v3_0_1 headers
Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0.
v2: squash in updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 20 May 2022 03:04:05 +0000 (11:04 +0800)]
drm/amdgpu: use the callback function for reset status polling on IMU
Switch to use the callback function to poll the reset status on IMU.
Because it will have different sequency on other ASICs.
v2: drop unused variable (Alex)
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Thu, 14 Apr 2022 20:57:17 +0000 (16:57 -0400)]
drm/amd/display: Ensure that DMCUB fw in use is loaded by DC and not VBIOS
[Why?]
On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads
DMUB, and driver does not reload as it appears to be initialized already.
[How?]
Add a check for the DAL_FW bit to ensure that loaded FW is from driver and
not VBIOS.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Tue, 5 Apr 2022 20:13:45 +0000 (16:13 -0400)]
drm/amd/display: use updated clock source init routine
[why]
Use correct clock source initialization routine for DCN32/321
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Fri, 1 Apr 2022 20:45:40 +0000 (16:45 -0400)]
drm/amd/display: Select correct DTO source
[WHY&HOW]
Change criteria for setting DTO source value, and always set it regardless of
the signal type.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stanley.Yang [Fri, 20 May 2022 13:03:09 +0000 (21:03 +0800)]
drm/amdgpu: print umc correctable error address
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 24 Mar 2022 19:42:17 +0000 (15:42 -0400)]
drm/amd/display: disable idle optimizations
Disable idle optimizations until SMU can handle them to prevent DMUB
timeout and subsequent system freeze
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 24 Mar 2022 18:59:09 +0000 (14:59 -0400)]
drm/amd/display: add missing interrupt handlers for DCN32/DCN321
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Mon, 14 Mar 2022 23:54:53 +0000 (19:54 -0400)]
drm/amd/display: Implement WM table transfer for DCN32/DCN321
Add support for watermark table transfers.
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Tue, 8 Mar 2022 23:45:08 +0000 (18:45 -0500)]
drm/amd/display: Various DML fixes to enable higher timings
Fixes to enable higher rate timings for DCN3.2.x.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Tue, 8 Mar 2022 20:32:06 +0000 (15:32 -0500)]
drm/amd/display: Add guard for FCLK pstate message to PMFW for DCN321
[WHY?]
DCN321 does not support FCLK DPM, and thus it should not send messages to
PMFW regarding it.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 20 May 2022 03:04:04 +0000 (11:04 +0800)]
drm/amdgpu: introduce two work mode for imu
IMU has two work mode such as debug mode and mission mode. Current GC
v11_0_0 is using the debug mode.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Bernstein [Thu, 3 Mar 2022 19:11:46 +0000 (14:11 -0500)]
drm/amd/display: Use DTBCLK for valid pixel clock
Use DTBCLK for valid pixel clock generation
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Mon, 28 Feb 2022 22:24:00 +0000 (17:24 -0500)]
drm/amd/display: Add missing instance for clock source register
[Description]
Need to add inst 5 for clk_src_regs because
there are 5 PHY instances in DCN32 & DCN321.
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Tue, 1 Mar 2022 21:15:03 +0000 (16:15 -0500)]
drm/amd/display: Fix USBC link creation
[Description]
Add USBC connector ID to align with new VBIOS parsing.
Add seperate DCN321 link encoder due to different PHY version affecting
DP ALT related registers.
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Feb 2022 20:33:05 +0000 (15:33 -0500)]
drm/amd: Add GFX11 modifiers support to AMDGPU (v3)
GFX11 IP introduces new tiling mode. Various combinations of DCC
settings are possible and the most preferred settings must be exposed
for optimal use of the hardware.
add_gfx11_modifiers() is based on recommendation from Marek for the
preferred tiling modifier that are most efficient for the hardware.
v2: microtiling fix noticed by Marek
v3: keep Z tiling check
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Tue, 31 May 2022 01:51:40 +0000 (09:51 +0800)]
drm/amd/amdgpu: align the cg and pg settings
align the cg and pg settings between gc_v11_0 and gc_v11_2
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 25 Apr 2022 22:33:23 +0000 (18:33 -0400)]
drm/amd/display: add DCN32 to IP discovery table
[Why&How]
Add DCN32 to IP discovery to enable automatic initialization of AMDGPU
Display Manager
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 24 Feb 2022 00:05:09 +0000 (19:05 -0500)]
drm/amd/display: Add DM support for DCN32/DCN321
Add Display Manager specific changes for DCN3.2.x. DM
handles the interaction between the core DC modesetting
code and the drm modesetting infrastructure.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 18 May 2022 06:11:20 +0000 (14:11 +0800)]
drm/amdgpu/mes11: update mes11 api interface
fix mes11 api interface.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Wed, 23 Feb 2022 22:48:45 +0000 (17:48 -0500)]
drm/amd/display: Add dependant changes for DCN32/321
[Why&How]
This patch adds necessary changes needed in DC files outside DCN32/321
specific tree
v2: squash in updates (Alex)
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Wed, 23 Feb 2022 22:46:31 +0000 (17:46 -0500)]
drm/amd/display: add DCN32/321 specific files for Display Core
Add core DC support for DCN 3.2.x.
v2: squash in fixup (Alex)
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Feb 2022 22:01:06 +0000 (17:01 -0500)]
drm/amd/display: add CLKMGR changes for DCN32/321
Add support for managing DCN3.2.x clocks.
v2: squash in smu interface updates (Alex)
v3: Drop unused SMU header (Alex)
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Feb 2022 21:58:49 +0000 (16:58 -0500)]
drm/amd/display: DML changes for DCN32/321
DML is required for display configuration modelling for things like
bandwidth management and validation.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Feb 2022 21:55:55 +0000 (16:55 -0500)]
drm/amd/display: add GPIO changes for DCN32/321
Add support for the GPIO changes for DCN3.2.x.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Feb 2022 21:41:46 +0000 (16:41 -0500)]
drm/amd/display: add dcn32 IRQ changes
Add DCN3.2.x interrupt support.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Feb 2022 21:03:58 +0000 (16:03 -0500)]
drm/amd/display: Add DMCUB source files and changes for DCN32/321
DMCUB is the display engine microcontroller which aids in modesetting
and other display related features.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 14 Apr 2022 19:19:16 +0000 (15:19 -0400)]
drm/amd: add register headers for DCN32/321
Add register headers for DCN 3.2.0 and 3.2.1.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Feb 2022 20:49:20 +0000 (15:49 -0500)]
drm/amd/display: Add DCN32/321 version identifiers
Add DCN3.2 asic identifiers.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Feb 2022 20:34:41 +0000 (15:34 -0500)]
drm/amd: Add atomfirmware.h definitions needed for DCN32/321
Add new structures for DCN 3.2.x.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stanley.Yang [Fri, 20 May 2022 10:22:21 +0000 (18:22 +0800)]
drm/amdgpu/pm: support mca_ceumc_addr in ecctable
SMU add a new variable mca_ceumc_addr to record
umc correctable error address in EccInfo table,
driver side add EccInfo_V2_t to support this feature
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
pengfuyuan [Thu, 26 May 2022 09:29:09 +0000 (17:29 +0800)]
drm/amd: Fix spelling typo in comments
Fix spelling typo in comments.
Reported-by: k2ci <kernel-bot@kylinos.cn>
Signed-off-by: pengfuyuan <pengfuyuan@kylinos.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 18 May 2022 03:40:54 +0000 (11:40 +0800)]
drm/amd/pm: enable fclk ds feature for SMU 13.0.0
The feature is ready with latest 78.39.0 PMFW.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 16 May 2022 01:50:31 +0000 (09:50 +0800)]
drm/amd/pm: update SMU 13.0.0 driver_if header
To fit the latest 78.39.0 PMFW.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 10 May 2022 08:08:50 +0000 (16:08 +0800)]
drm/amd/pm: correct the way for retrieving current uclk frequency
There is some problem with average frequency reading. Thus, we
switch to the target frequency reading instead.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mitchell Augustin [Wed, 25 May 2022 19:09:14 +0000 (14:09 -0500)]
amdgpu: amdgpu_device.c: Removed trailing whitespace
Removed trailing whitespace from end of line in amdgpu_device.c
Signed-off-by: Mitchell Augustin <kernel@mitchellaugustin.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 24 May 2022 14:17:43 +0000 (10:17 -0400)]
drm/amdgpu: convert sienna_cichlid_get_default_config_table_settings() to IP version
Use IP version rather than asic type.
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 24 May 2022 14:10:18 +0000 (10:10 -0400)]
drm/amdgpu: simplify amdgpu_device_asic_has_dc_support()
Drop extra cases in the default case.
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leung, Martin [Fri, 13 May 2022 21:40:42 +0000 (17:40 -0400)]
drm/amdgpu/display: Prepare for new interfaces
why:
lut pipeline will be hooked up differently in some asics
need to add new interfaces
how:
add them
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Martin <martin.leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 30 May 2022 06:58:08 +0000 (14:58 +0800)]
drm/amdgpu: suppress the compile warning about 64 bit type
Suppress the compile warning below:
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:1292
gfx_v11_0_rlc_backdoor_autoload_copy_ucode() warn: should '1 << id' be a 64 bit type?
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 30 May 2022 03:37:07 +0000 (11:37 +0800)]
drm/amd/pm: suppress compile warnings about possible unaligned accesses
Suppress the following compile warnings:
>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v11_0_pptable.h:163:17:
warning: field smc_pptable within 'struct smu_11_0_powerplay_table' is
less aligned than 'PPTable_t' and is usually due to 'struct smu_11_0_powerplay_table'
being packed, which can lead to unaligned accesses [-Wunaligned-access]
PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
^
1 warning generated.
--
>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v11_0_7_pptable.h:193:17:
warning: field smc_pptable within 'struct smu_11_0_7_powerplay_table' is
less aligned than 'PPTable_t' and is usually due to 'struct smu_11_0_7_powerplay_table'
being packed, which can lead to unaligned accesses [-Wunaligned-access]
PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
^
1 warning generated.
--
>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0_pptable.h:161:12:
warning: field smc_pptable within 'struct smu_13_0_powerplay_table' is less aligned than
'PPTable_t' and is usually due to 'struct smu_13_0_powerplay_table' being packed, which
can lead to unaligned accesses [-Wunaligned-access]
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Fri, 3 Jun 2022 13:19:34 +0000 (09:19 -0400)]
drm/amdkfd: Fix partial migration bugs
Migration range from system memory to VRAM, if system page can not be
locked or unmapped, we do partial migration and leave some pages in
system memory. Several bugs found to copy pages and update GPU mapping
for this situation:
1. copy to vram should use migrate->npage which is total pages of range
as npages, not migrate->cpages which is number of pages can be migrated.
2. After partial copy, set VRAM res cursor as j + 1, j is number of
system pages copied plus 1 page to skip copy.
3. copy to ram, should collect all continuous VRAM pages and copy
together.
4. Call amdgpu_vm_update_range, should pass in offset as bytes, not
as number of pages.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Lang Yu [Tue, 31 May 2022 01:19:43 +0000 (09:19 +0800)]
drm/amdkfd: add pinned BOs to kfd_bo_list
The kfd_bo_list is used to restore process BOs after
evictions. As page tables could be destroyed during
evictions, we should also update pinned BOs' page tables
during restoring to make sure they are valid.
So for pinned BOs,
1, Validate them and update their page tables.
2, Don't add eviction fence for them.
v2:
- Don't handle pinned ones specially in BO validation.(Felix)
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Wed, 1 Jun 2022 23:02:45 +0000 (19:02 -0400)]
drm/amdgpu: Update PDEs flush TLB if PTB/PDB moved
Flush TLBs when existing PDEs are updated because a PTB or PDB moved,
but avoids unnecessary TLB flushes when new PDBs or PTBs are added to
the page table, which commonly happens when memory is mapped for the
first time.
Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sunil Khatri [Mon, 30 May 2022 17:54:09 +0000 (23:24 +0530)]
drm/amdgpu: enable tmz by default for GC 10.3.7
Add IP GC 10.3.7 in the list of target to have
tmz enabled by default.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.18.x
Mario Limonciello [Tue, 31 May 2022 23:56:41 +0000 (18:56 -0500)]
drm/amdkfd: Add GC 10.3.6 and 10.3.7 KFD definitions
Loading amdgpu on GC 10.3.7 shows an ERR level message:
`kfd kfd: amdgpu: GC IP 0a0307 not supported in kfd`
Add these targets to match yellow carp structures.
Reported-by: David Chang <david.chang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: Jesse(Jie) Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.18.x
Philip Yang [Thu, 26 May 2022 20:15:38 +0000 (16:15 -0400)]
drm/amdkfd: Use mmget_not_zero in MMU notifier
MMU notifier callback may pass in mm with mm->mm_users==0 when process
is exiting, use mmget_no_zero to avoid accessing invalid mm in deferred
list work after mm is gone.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Candice Li [Wed, 1 Jun 2022 09:10:44 +0000 (17:10 +0800)]
drm/amdgpu: Resolve RAS GFX error count issue after cold boot on Arcturus
Adjust the sequence for ras late init and separate ras reset error status
from query status.
v2: squash in fix from Candice
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stanley.Yang [Tue, 31 May 2022 10:57:06 +0000 (18:57 +0800)]
drm/amdgpu: fix ras supported check
Fix aldebaran ras supported check on SRIOV guest side,
the previous check conditicon block all ras feature
on baremetal
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 14 Apr 2022 19:48:30 +0000 (15:48 -0400)]
drm/amd/display: remove stale config guards
This code should be executed.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
sunliming [Sun, 29 May 2022 06:26:31 +0000 (14:26 +0800)]
drm/amdgpu: make gfx_v11_0_rlc_stop static
This symbol is not used outside of gfx_v11_0.c, so marks it static.
Fixes the following w1 warning:
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:1945:6: warning: no previous
prototype for function 'gfx_v11_0_rlc_stop' [-Wmissing-prototypes].
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: sunliming <sunliming@kylinos.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
sunliming [Sun, 29 May 2022 07:26:31 +0000 (15:26 +0800)]
drm/amdgpu: fix a missing break in gfx_v11_0_handle_priv_fault
Fixes the following w1 warning:
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:5873:2: warning: unannotated
fall-through between switch labels [-Wimplicit-fallthrough].
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: sunliming <sunliming@kylinos.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Wed, 25 May 2022 21:20:21 +0000 (17:20 -0400)]
drm/amdgpu: fix aper_base for APU
[Why]
Wrong fb offset results in dmub f/w errors and white screen.
[drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3
[How]
Read aper_base from mmhub because GC is off by default
v2: use BAR for passthrough (Alex)
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 26 May 2022 20:34:55 +0000 (16:34 -0400)]
drm/amdgpu: update VCN codec support for Yellow Carp
Supports AV1. Mesa already has support for this and
doesn't rely on the kernel caps for yellow carp, so
this was already working from an application perspective.
Fixes:
554398174d98 ("amdgpu/nv.c - Added video codec support for Yellow Carp")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2002
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Jiapeng Chong [Wed, 25 May 2022 09:37:02 +0000 (17:37 +0800)]
drm/amdgpu: make program_imu_rlc_ram static
This symbol is not used outside of imu_v11_0.c, so marks it
static.
Fixes the following w1 warning:
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c:302:6: warning: no previous
prototype for ‘program_imu_rlc_ram’ [-Wmissing-prototypes].
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 16 May 2022 01:52:38 +0000 (21:52 -0400)]
drm/amd/display: 3.2.187
This version brings along the following fixes:
* Changes to DP LT fallback behavior to more closely match the DP standard
* Added new interfaces for lut pipeline
* Restore ref_dtblck value when clk struct is cleared in init_clocks
* Fixes DMUB outbox trace in S4
* Fixes lingering DIO FIFO errors when DIO no longer enabled
* Reads Golden Settings Table from VBIOS
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ilya [Mon, 7 Feb 2022 22:39:10 +0000 (17:39 -0500)]
drm/amd/display: Fix possible infinite loop in DP LT fallback
[Why]
It's possible for some fallback scenarios to result in infinite looping
during link training.
[How]
This change modifies DP LT fallback behavior to more closely match the
DP standard. Keep track of the link rate during the EQ_FAIL fallback,
and use it as the maximum link rate for the CR sequence.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Ilya <Ilya.Bakoulin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin [Thu, 12 May 2022 20:49:16 +0000 (16:49 -0400)]
drm/amd/display: Don't clear ref_dtbclk value
[Description]
ref_dtbclk value is assigned in clk_mgr_construct,
but the clks struct is cleared in init_clocks.
Make sure to restore the value or we will get
0 value for ref_dtbclk in DCN31.
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hung, Cruise [Fri, 13 May 2022 01:16:42 +0000 (09:16 +0800)]
drm/amd/display: Fix DMUB outbox trace in S4 (#4465)
[Why]
DMUB Outbox0 read/write pointer not sync after resumed from S4.
And that caused old traces were sent to outbox.
[How]
Disable DMUB Outbox0 interrupt
and clear DMUB Outbox0 read/write pointer when resumes from S4.
And then enable Outbox0 interrupt before starts DMCUB.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hengzhou [Sat, 7 May 2022 01:43:08 +0000 (09:43 +0800)]
drm/amd/display: Wait DMCUB to idle state before reset.
[WHY]
Very low rate to cause memory access issue while resetting
DMCUB after the halt command was sent to it.
The process of stopping fw of DMCUB may be timeout, that means
it is not in idle state, such as the window frames may still be
kept in cache, so reset by force will cause MMHUB hang.
[HOW]
After the halt command was sent, keep checking the DMCUB state until
it is idle.
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: hengzhou <Hengyong.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 6 May 2022 16:56:38 +0000 (12:56 -0400)]
drm/amd/display: Pass the new context into disable OTG WA
[Why]
When enabling an HPO stream for the first time after having previously
enabled a DIO stream there may be lingering DIO FIFO errors even though
the DIO is no longer enabled.
These can cause display clock change to hang if we don't apply the
OTG disable workaround since the ramping logic is tied to OTG on.
[How]
The workaround wasn't being applied in the sequence of:
1 DIO stream
0 streams
1 HPO stream
because current_state has no stream or planes in its context - and
it's only swapped after optimize has finished.
We should be using the incoming context instead to determine whether
this logic is needed or not.
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leung, Martin [Tue, 10 May 2022 16:27:08 +0000 (12:27 -0400)]
drm/amd/display: revert Blank eDP on disable/enable drv
why and how:
Revert this change. It was causing a black screen with certain blocks
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Leung, Martin <Martin.Leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sherry Wang [Tue, 10 May 2022 10:42:18 +0000 (18:42 +0800)]
drm/amd/display: Read Golden Settings Table from VBIOS
[Why]
Dmub read AUX_DPHY_RX_CONTROL0 from Golden Setting Table,
but driver will set it to default value 0x103d1110, which
causes issue in some case
[How]
Remove the driver code, use the value set by dmub in
dp_aux_init
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Sherry Wang <YAO.WANG1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Wed, 1 Jun 2022 00:56:11 +0000 (10:56 +1000)]
Merge tag 'amd-drm-next-5.19-2022-05-26-2' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.19-2022-05-26-2:
amdgpu:
- Update fdinfo to the common drm format
UAPI:
- Add VM_NOALLOC GPUVM attribute to prevent buffers for going into the MALL
Add AMDGPU_GEM_CREATE_DISCARDABLE flag to create buffers that can be discarded on eviction
Mesa code which uses these: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220526202546.66860-1-alexander.deucher@amd.com
Dave Airlie [Wed, 1 Jun 2022 00:37:20 +0000 (10:37 +1000)]
Merge tag 'amd-drm-next-5.19-2022-05-26' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.19-2022-05-26:
amdgpu:
- Link training fixes
- DPIA fixes
- Misc code cleanups
- Aux fixes
- Hotplug fixes
- More FP clean up
- Misc GFX9/10 fixes
- Fix a possible memory leak in SMU shutdown
- SMU 13 updates
- RAS fixes
- TMZ fixes
- GC 11 updates
- SMU 11 metrics fixes
- Fix coverage blend mode for overlay plane
- Note DDR vs LPDDR memory
- Fuzz fix for CS IOCTL
- Add new PCI DID
amdkfd:
- Clean up hive setup
- Misc fixes
radeon:
- Fix a possible NULL pointer dereference
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220526200641.64097-1-alexander.deucher@amd.com
Christian König [Tue, 10 May 2022 16:29:35 +0000 (18:29 +0200)]
drm/amdgpu: add drm-client-id to fdinfo v2
This is enough to get gputop working :)
v2: rebase and some addition cleanup
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 11 May 2022 09:06:26 +0000 (11:06 +0200)]
drm/amdgpu: Convert to common fdinfo format v5
Convert fdinfo format to one documented in drm-usage-stats.rst.
It turned out that the existing implementation was actually completely
nonsense. The calculated percentages indeed represented the usage of the
engine, but with varying time slices.
So 10% usage for application A could mean something completely different
than 10% usage for application B.
Completely nuke that and just use the now standardized nanosecond
interface.
v2: drop the documentation change for now, nuke percentage calculation
v3: only account for each hw_ip, move the time_spend to the ctx mgr.
v4: move general ctx changes into separate patch, rework the fdinfo to
ctx_mgr interface so that all usages are calculated at once, drop
some unecessary and dangerous refcount dance.
v5: add one more comment how we calculate the time spend
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Shashank Sharma <shashank.sharma@amd.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 6 May 2022 11:21:28 +0000 (13:21 +0200)]
drm/amdgpu: bump minor version number
Increase the minor version number to indicate that the new flags are
available.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 6 May 2022 11:11:41 +0000 (13:11 +0200)]
drm/amdgpu: add AMDGPU_VM_NOALLOC v2
Add the AMDGPU_VM_NOALLOC flag to let userspace control MALL allocation.
v2: also add the flag to the allowed flags.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 6 May 2022 11:08:34 +0000 (13:08 +0200)]
drm/amdgpu: add AMDGPU_GEM_CREATE_DISCARDABLE
Add a AMDGPU_GEM_CREATE_DISCARDABLE flag to note that the content of a BO
doesn't needs to be preserved during eviction.
KFD was already using a similar functionality for SVM BOs so replace the
internal flag with the new UAPI.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 25 May 2022 03:23:59 +0000 (23:23 -0400)]
drm/amdgpu: add beige goby PCI ID
Add a beige goby PCI ID.
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Lijo Lazar [Tue, 24 May 2022 12:05:55 +0000 (17:35 +0530)]
drm/amd/pm: Return auto perf level, if unsupported
When powerplay is not enabled, return AUTO as default level.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>