Philipp Tomsich [Fri, 29 Sep 2017 17:27:57 +0000 (19:27 +0200)]
rockchip: spl: support a 'same-as-spl'-specifier in the spl-boot-order
It is often desirable to configure the spl-boot-order (i.e. the order
that SPL probes devices to find the FIT image containing a full U-Boot)
such that it contains 'the same device the SPL stage was booted from'
early on. To support this, we introduce the 'same-as-spl' specifier
for the spl-boot-order property.
This commit adds:
- documentation for the new board_spl_was_booted_from() function that
individual SoCs/boards should provide, if they can determine where
the SPL was booted from
- implements the new board_spl_was_booted_from() stub function
- adds support for handling the 'same-as-spl' specifier and calling
into the per-SoC/per-board support code.
This also updates the documentation for the 'u-boot,spl-boot-order'
property.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 29 Sep 2017 17:27:56 +0000 (19:27 +0200)]
rockchip: spl: add documentation for spl_node_to_boot_device()
In the expectation that the spl-boot-order code will eventually
gain use outside of mach-rockchip: let's add documentation on the
spl_node_to_boot_device() function, which is likely to become a
publicly exported function.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 29 Sep 2017 17:27:55 +0000 (19:27 +0200)]
rockchip: bootrom: add definitions to retrieve BROM boot-source
The Rockchip BROM allows reading where it booted from from SRAM.
This adds the necessary definitions (as received from Kever) for
the location of this information in the RK3399's SRAM and naming
for the constants used.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 29 Sep 2017 17:27:54 +0000 (19:27 +0200)]
rockchip: rk3399: make spl_board_init board-specific
The later-stage spl_board_init (as opposed to board_init_f) should set
up board-specific details: these differ between the EVB-RK3399 and the
RK3399-Q7 (Puma).
This moves spl_board_init back into the individual boards and removes
the unneeded functionality from Puma.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Heinrich Schuchardt [Wed, 27 Sep 2017 18:23:09 +0000 (20:23 +0200)]
evb-rk3399: avoid redefinition of CONFIG_ENV_OFFSET
CONFIG_ENV_OFFSET is already defined in
include/configs/rockchip-common.h
For CONFIG_ROCKCHIP_BACK_TO_BROM=y we redefine CONFIG_ENV_OFFSET
to an unsuitable value. We were lucky to get a compiler warning.
Remove the incorrect redefinition.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Tue, 22 Aug 2017 07:34:58 +0000 (15:34 +0800)]
rockchip: rk322x: update the sysreg number for boot mode
The boot mode for rk322x is stored in sysreg 0, update it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Elaine Zhang [Wed, 27 Sep 2017 07:23:38 +0000 (15:23 +0800)]
rockchip: dts: rk3328-evb: add i2c1 and rk805 nodes
add i2c1 and rk805 nodes to support rk805 init setting.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Elaine Zhang [Wed, 27 Sep 2017 07:23:37 +0000 (15:23 +0800)]
configs: rk3328: add support for pmic rk8xx and regulator and i2c driver
Add defconfig for rk8xx and regulator and i2c controller.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Elaine Zhang [Wed, 27 Sep 2017 07:23:34 +0000 (15:23 +0800)]
rockchip: i2c: rk3328: support i2c for rk3328 SoC
Add compatible to support rk3328 i2c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Heiko Schocher<hs@denx.de>
Philipp Tomsich [Tue, 19 Sep 2017 13:49:14 +0000 (15:49 +0200)]
rockchip: pinctrl: rk3368: add pinctrl for SDMMC0
Apparently, our earlier assumption that the BROM will always set up
the iomux for SDcard communication does not always hold true: when
booting U-Boot from the on-module (on the RK3368-uQ7) eMMC, the SDcard
pins are not set up and need to be configured by the pinctrl driver to
allow SD card access.
This change implements support for setting up the SDMMC pins in
pinctrl for the RK3368.
Reported-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 15 Sep 2017 13:57:15 +0000 (15:57 +0200)]
rockchip: board: lion-rk3368: avoid ATF overwriting active SPL stage
The RK3368-uQ7 ATF has been moved back to 0x100000 (1MB from the start
of DRAM) to avoid it overwriting the active SPL stage during FIT image
loading. This change adapts the .its to match up (again) with our ATF
repository for the RK3368-uQ7.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagan Teki [Wed, 27 Sep 2017 17:33:13 +0000 (23:03 +0530)]
rk3288: vyasa: Add falcon mode support
Add Falcon mode support in vyasa rk3288 board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Jagan Teki [Wed, 27 Sep 2017 17:33:12 +0000 (23:03 +0530)]
rk3288: vyasa: Add TPL support
Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.
So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Jagan Teki [Wed, 27 Sep 2017 17:33:11 +0000 (23:03 +0530)]
armv7: rk3288: Move configure_l2ctlr to common
configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Jagan Teki [Wed, 27 Sep 2017 17:33:10 +0000 (23:03 +0530)]
armv7: Move L2CTLR read/write to common
L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Backed out the change to arch/arm/mach-tegra/cache.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Thu, 28 Sep 2017 10:24:03 +0000 (18:24 +0800)]
rockchip: rk322x: fix pd_bus hclk/pclk
The pd_bus hclk/pclk source is pd_bus aclk, not the PLL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 09:57:28 +0000 (17:57 +0800)]
rockchip: mkimage: add support for rk3128 soc
Add support for rk3128 package header in mkimage tool.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 09:02:58 +0000 (17:02 +0800)]
rockchip: rk3036: fix grf macro define
Some of macros definition are not correct, fix them according to TRM.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:59:56 +0000 (16:59 +0800)]
rockchip: clk: fix typo in rk322x clock driver
Fix typo RK322X/RK3036 in rk322x clock driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 10:48:12 +0000 (12:48 +0200)]
rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROM
Instead of directly calling into the back-to-bootrom code, the RK3399
common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a
transfer back into the bootrom.
With this factored out, the spl_board_init function can not be
customised for each RK3399 board.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 27 Sep 2017 11:27:38 +0000 (13:27 +0200)]
rockchip: lion-rk3368: defconfig: remove duplicate CONFIG_ENV_IS_IN_MMC
Remove a duplicate CONFIG_ENV_IS_IN_MMC assignment for the lion-rk3368
defconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Mon, 25 Sep 2017 08:33:22 +0000 (16:33 +0800)]
rockchip: rk3188: ram: add support for 16bit row address
RK3188 using the same ddr_conf for both 15 bit and 16 bit row address.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed compile-error by declaring 'row':]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:38:23 +0000 (16:38 +0800)]
rockchip: dts: rk3229: remove dram channel info
The dram channel info will be auto detect by the driver,
we do not need it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 27 Sep 2017 08:38:22 +0000 (16:38 +0800)]
rockchip: rk322x: add sdram driver
Add driver for rk322x to support sdram initialize in SPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:11:33 +0000 (16:11 +0800)]
rockchip: rk3328: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:11:32 +0000 (16:11 +0800)]
rockchip: rk3288: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:11:31 +0000 (16:11 +0800)]
rockchip: rk3188: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 27 Sep 2017 08:11:30 +0000 (16:11 +0800)]
rockchip: rk3399: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Wed, 20 Sep 2017 11:50:13 +0000 (13:50 +0200)]
rockchip: imply ADC and SARADC_ROCKCHIP for Rockchip SOCs
Enable the Rockchip SARADC driver for all Rockchip SoCs.
Note that the SARADC peripheral is available on all SoCs except the
RK3036 and RK3228. However, as this is a DM-driver, enabling by
default will not cause any function problems (and can always be
changed from defconfig, if size is a concern).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
David Wu [Wed, 20 Sep 2017 06:47:19 +0000 (14:47 +0800)]
rockchip: dts: Enable SARADC for rk3399-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:46:19 +0000 (14:46 +0800)]
rockchip: dts: Enable SARADC for rk3368-sheep
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:45:21 +0000 (14:45 +0800)]
rockchip: dts: Enable SARADC for rk3368-px5-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:44:23 +0000 (14:44 +0800)]
rockchip: dts: Enable SARADC for rk3328-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:43:08 +0000 (14:43 +0800)]
rockchip: dts: Enable SARADC for rk3288-popmetal
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:41:38 +0000 (14:41 +0800)]
rockchip: dts: Enable SARADC for rv1108-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:40:11 +0000 (14:40 +0800)]
rockchip: dts: rv1108: Add SARADC node at dtsi level
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:38:58 +0000 (14:38 +0800)]
rockchip: clk: Add rk3399 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:37:50 +0000 (14:37 +0800)]
rockchip: clk: Add rk3368 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:35:44 +0000 (14:35 +0800)]
rockchip: clk: Add rk3328 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:28:19 +0000 (14:28 +0800)]
rockchip: clk: Add SARADC clock support for rk3288
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:28:18 +0000 (14:28 +0800)]
rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 20 Sep 2017 06:28:16 +0000 (14:28 +0800)]
dm: adc: Add driver for Rockchip SARADC
The ADC can support some channels signal-ended some bits Successive Approximation
Register (SAR) A/D Converter, like 6-channel and 10-bit. It converts the analog
input signal into some bits binary digital codes.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sam Protsenko [Thu, 21 Sep 2017 19:37:59 +0000 (22:37 +0300)]
env: ti: boot: Show boot status information
Add tracing printings to Linux/Android boot commands, so that we can see
what's going on. Helps to trace possible bugs on early stages and
improves the output for user (which is especially useful, because we
have a bunch of boot commands executing one by one).
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sam Protsenko [Thu, 21 Sep 2017 19:37:58 +0000 (22:37 +0300)]
env: ti: boot: Extract command for eMMC Linux boot
Extract commands for booting Linux from eMMC to separate command. It
seems more logical that way, and allows us to run the whole command set
from U-Boot shell with only one command.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sam Protsenko [Thu, 21 Sep 2017 19:37:57 +0000 (22:37 +0300)]
arm: dra7xx: Fix Linux boot from eMMC
Right now on OMAP5-based boards we have only one partition defined for
Linux boot, which is rootfs. That doesn't work with bootpart=1:2 (that
is defined in include/environment/ti/boot.h). To fix Linux boot we may
either:
1. Change bootpart to be 1:1
2. Or add preceding partition, so that rootfs is actually 1:2
Second choice seems more reasonable, as DFU is already using similar
partition table and can rely on bootpart to be 1:2.
This patch adds "bootloader" partition. So now eMMC layout for Linux
boot looks like this:
offset content size partition
(KiB) (KiB)
Reviewed-by: Tom Rini <trini@konsulko.com>
=======================================================================
0 +--------------------------------+
| MBR/GPT header | 128 -
128 +--------------------------------+
| MLO | 256 -
384 +--------------------------------+
| u-boot.img | 1792 bootloader
2176 +--------------------------------+
| //////////// hole //////////// | 256 -
2432 +--------------------------------+
| U-Boot environment | 128 -
2560 +--------------------------------+
| U-Boot environment (redundant) | 128 -
2688 +--------------------------------+
| rootfs | remaining rootfs
end +--------------------------------+
=======================================================================
Guard hole appears because U-Boot environment offset was calculated for
Android partition table, which has two additional partitions in place of
that hole ("environment" and "misc" partitions).
This patch also changes rootfs offset from 2 MiB further to 2688 KiB,
so that there won't be any collisions with U-Boot environment when we
flash rootfs.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Sam Protsenko [Thu, 21 Sep 2017 19:37:56 +0000 (22:37 +0300)]
arm: am57xx: Fix Linux boot from eMMC
Right now on OMAP5-based boards we have only one partition defined for
Linux boot, which is rootfs. That doesn't work with bootpart=1:2 (that
is defined in include/environment/ti/boot.h). To fix Linux boot we may
either:
1. Change bootpart to be 1:1
2. Or add preceding partition, so that rootfs is actually 1:2
Second choice seems more reasonable, as DFU is already using similar
partition table and can rely on bootpart to be 1:2.
This patch adds "bootloader" partition. So now eMMC layout for Linux
boot looks like this:
offset content size partition
(KiB) (KiB)
Reviewed-by: Tom Rini <trini@konsulko.com>
=======================================================================
0 +--------------------------------+
| MBR/GPT header | 128 -
128 +--------------------------------+
| MLO | 256 -
384 +--------------------------------+
| u-boot.img | 1792 bootloader
2176 +--------------------------------+
| //////////// hole //////////// | 256 -
2432 +--------------------------------+
| U-Boot environment | 128 -
2560 +--------------------------------+
| U-Boot environment (redundant) | 128 -
2688 +--------------------------------+
| rootfs | remaining rootfs
end +--------------------------------+
=======================================================================
Guard hole appears because U-Boot environment offset was calculated for
Android partition table, which has two additional partitions in place of
that hole ("environment" and "misc" partitions).
This patch also changes rootfs offset from 2 MiB further to 2688 KiB,
so that there won't be any collisions with U-Boot environment when we
flash rootfs.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Karthik Tummala [Thu, 21 Sep 2017 08:40:35 +0000 (14:10 +0530)]
arm: dts: omap3: sync DTS with Linux 4.14-rc1
This re-syncs omap3 DTS file with current file from
Linux v4.14-rc1 to ensure a consistent configuration. Upstream
Linux removed the redundant Interrupt-parent property from usbhsohci,
usbhsehci, ssi_port1 and ssi_port2 sub nodes.
Signed-off-by: Karthik Tummala <karthik@techveda.org>
Patrice Chotard [Thu, 21 Sep 2017 08:08:09 +0000 (10:08 +0200)]
dm: clk: add missing .priv_auto_alloc_size() for stm32f7
Add missing .priv_auto_alloc_size() callback.
Previously private struct stm32_clk was not allocate
which leads to unpredictable behaviour
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lokesh Vutla [Thu, 21 Sep 2017 02:52:35 +0000 (08:22 +0530)]
ARM: dts: OMAP5+: Enable all gpios in SPL
With DM enabled, gpio numbering is assigned based on the
probed order of gpios, irrespective of the gpio base. So enable
all necessary gpios in SPL.
Fixes:
edf25d94d55c (“ARM: dts: OMAP5+: Enable gpio in SPL”)
Reported-by: Gou, Hongmei <h-gou@ti.com>
Tested-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Thu, 21 Sep 2017 02:01:13 +0000 (07:31 +0530)]
configs: keystone2: env: Fix burn_uboot_spi command
Now the u-boot spi image is greater than 0x80000, increase the same
in env during spi erase.
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Wed, 20 Sep 2017 19:45:09 +0000 (14:45 -0500)]
configs: k2g_evm: Make findfdt command populate fdtfile variable
On all other platforms the command 'findfdt' populates the variable
'fdtfile', but on K2G we only populate 'name_fdt'. The generic boot
and automation scripts fail when 'findfdt' is not populated, fix
this for K2G.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Andrew F. Davis [Wed, 20 Sep 2017 19:38:50 +0000 (14:38 -0500)]
configs: am43xx_evm: Avoid relocation onto firewall at the end of DRAM
On secure devices the initial secure software may install a firewall at
the end of DRAM, define protected RAM to avoid space.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Madan Srinivas [Wed, 20 Sep 2017 19:37:36 +0000 (14:37 -0500)]
arm: am33xx: security: adds auth support for encrypted images
This patch adds support for authentication of both plain
text and encrypted binaries. A new SECDEV package is needed
to enable encryption of binaries by default for AM3x.
The ROM authentication API detects encrypted images at
runtime and automatically decrypts the image if the
signature verification passes.
Addition of encryption on AM3x results in a change in the
image format. On AM4x, AM5x and, on AM3x devices signing
clear test images, the signature is appended to the end of the
binary.
On AM3x, when the SECDEV package is used to create signed
and encrypted images, the signature is added as a header
to the start of the binary. So the binary size calculation
has been updated to reflect this change.
The signing tools and encrypted image format for AM3x
cannot be changed to behave like AM4x and AM5x to
maintain backward compatibility with older Sitara
M-Shield releases.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Andrew F. Davis [Wed, 20 Sep 2017 19:33:51 +0000 (14:33 -0500)]
defconfigs: Add a config for AM335x High Security EVM with UART Boot support
Add a new defconfig file for the AM335x High Security EVM. This config
is specific for the case of UART booting
Signed-off-by: Andrew F. Davis <afd@ti.com>
Adam Ford [Wed, 20 Sep 2017 01:32:11 +0000 (20:32 -0500)]
ARM: omap3: am3517-evm: Add device tree and DM support
With the device tree ported from Linux 4.13, this enables
Driver Model and Device Tree support for the am3517-evm
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
Adam Ford [Wed, 20 Sep 2017 01:32:10 +0000 (20:32 -0500)]
arm: dts: am3517_evm: Sync DTS files with Linux 4.13-RC5
To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.
There are some spacing issues in the patch, but they appear to be
present in the Linux source files. I'll try to get to fixing them there,
and do a future re-sync at a later date.
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
Ulf Magnusson [Tue, 19 Sep 2017 10:52:55 +0000 (12:52 +0200)]
kconfiglib: update with 'imply' support
Corresponds to 375506d (File writing nit) from upstream
(https://github.com/ulfalizer/Kconfiglib).
Adds proper 'imply' support and fixes a few minor issues, one of which
previously triggered the following weird warning:
configs/taurus_defconfig: /tmp/tmpisI45S:6: warning: assignment to SPL_LDSCRIPT changes mode of containing choice from "arch/$(ARCH)/cpu/u-boot-spl.lds" to "y"
The change in 8639f69 (genconfig.py: Print defconfig next to warnings)
was reapplied.
tools/moveconfig.py previously depended on a hack that merged 'select's
with 'imply's. It was modified to look at the union of
Symbol.get_selected_symbols() and Symbol.get_implied_symbols(), which
should give the same behavior.
tools/genboardscfg.py was verified to produce identical board.cfg's
before and after the change.
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
Heinrich Schuchardt [Tue, 19 Sep 2017 17:28:32 +0000 (19:28 +0200)]
scripts/checkpatch: add missing spelling.txt
Checkpatch can use two dictionaries for finding typos:
* scripts/spelling.txt
* /usr/share/codespell/dictionary.txt
which comes with package codespell and is selected by parameter
--codespell
If the file scripts/spelling.txt is missing, a warning is shown.
Add the spelling.txt file from the Linux kernel 4.13 source.
We can later add our own typo corrections.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Dan Murphy <dmurphy@ti.com>
Stephen Warren [Mon, 18 Sep 2017 17:50:47 +0000 (11:50 -0600)]
test/py: fix anchors in HTML status report
The current code wraps a pre tag inside an a tag. For some reason, this
causes at least Firefox to attempt to drag the pre section content when
using a mouse drag to select text. Re-order the tags so that the text can
be selected using the mouse, at least if you start the drag outside the
text (after the end of the line, for example).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Mon, 18 Sep 2017 17:11:49 +0000 (11:11 -0600)]
test/py: add skip marker for reliance on tools
Some tests use external tools (executables) during their operation. Add
a test.py mark to indicate this. This allows those tests to be skipped if
the required tool is not present.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Mon, 18 Sep 2017 17:11:48 +0000 (11:11 -0600)]
test/py: provide more information about test skip reason
When skipping tests, explicitly mention the board type or config option
that caused the skip. This will help people understand/fix any issues.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Mon, 18 Sep 2017 17:11:47 +0000 (11:11 -0600)]
test/py: Document required tools/packages
Some tests rely on external tools. Mention these in the test/py README.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tom Rini [Sun, 17 Sep 2017 15:44:49 +0000 (11:44 -0400)]
TI: ARCH_OMAP2PLUS: Enable SPL_STACK_R and provide default value
On ARCH_OMAP2PLUS platforms we know what the DDR layout is going to be,
and that it is safe to use SPL_STACK_R and provide a default value for
it. select this and re-sync the defconfigs.
Signed-off-by: Tom Rini <trini@konsulko.com>
Adam Ford [Mon, 18 Sep 2017 01:43:48 +0000 (20:43 -0500)]
ARM: da850-evm: Enable DM_I2C
With DM now enabled with the device tree pulled from Linux, we can
enable DM_I2C in U-Boot.
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add DM_I2C_COMPAT to da850_am18xxevm to fix warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
Adam Ford [Mon, 18 Sep 2017 01:43:47 +0000 (20:43 -0500)]
arm: da850-evm: Enable MTD Parts in SPI Flash
There is a discrepency between U-Boot and Linux on the partition map.
This enabes the MTD parts to pass MTD partition information from U-Boot to
Linux. Linux already has a pending patch to enable MTD PARTS in
davinci_all_defconfig
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Mon, 18 Sep 2017 01:43:46 +0000 (20:43 -0500)]
arm: da850-evm: Enable DM and device tree support for da850-evm
With the device tree ported and DM compatible drivers, enable:
OF_CONTROL, DM_SPI, DM_SPI_FLASH and DM_SERIAL
Note: DM_SERIAL is not enabled for da850evm_direct_nor_defconfig
yet.
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Mon, 18 Sep 2017 01:43:45 +0000 (20:43 -0500)]
spi: davinci_spi: Add da830-spi support for DM
The DM support is already in the driver, so add
da830-spi to the compatible list.
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Mon, 18 Sep 2017 01:43:44 +0000 (20:43 -0500)]
arm: dts: da850: Migrate da850-evm DTS files from Linux 4.13-RC5
A few small additional items are needed to support DM_SPI and
DM_SERIAL, so those were added to da850-evm-u-boot.dtsi
Signed-off-by: Adam Ford <aford173@gmail.com>
Tom Rini [Fri, 29 Sep 2017 03:31:11 +0000 (23:31 -0400)]
Merge git://git.denx.de/u-boot-mmc
Masahiro Yamada [Thu, 28 Sep 2017 12:13:10 +0000 (21:13 +0900)]
mmc: sdhci-cadence: set timing mode register depending on frequency
The MMC framework in U-Boot does not support a systematic API for
timing switch like mmc_set_timing() in Linux.
U-Boot just provides a hook to change the clock frequency via
mmc_set_clock(). It is up to drivers if additional register
settings are needed.
This driver needs to set a correct timing mode into a register when
it migrates to a different speed mode. Only increasing clock frequency
could result in setup/hold timing violation.
The timing mode should be decided by checking MMC_TIMING_* like
drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not
supported by U-Boot for now. Just use mmc->clock to decide the
timing mode.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Seung-Woo Kim [Tue, 19 Sep 2017 04:29:45 +0000 (13:29 +0900)]
spl: spl_mmc: add __maybe_unused to mmc_load_image_raw_sector()
If there are no CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR and CONFIG_SPL_OS_BOOT,
there is unused-function build warning. Add __maybe_unused macro
to remove the warning.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Marek Vasut [Fri, 15 Sep 2017 19:10:54 +0000 (21:10 +0200)]
mmc: uniphier-sd: Add vqmmc regulator support
Add initial support for setting the vqmmc regulator. Since we do not
support 1V8 modes, set the regulator to 3V3 and enable it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasut [Tue, 26 Sep 2017 18:05:34 +0000 (20:05 +0200)]
mmc: uniphier-sd: Update the file to match V3 patchset
Old version of the uniphier-sd 64bit IO support patchset V1 was
applied by the maintainer, update the uniphier-sd.c with the
changes from the V3 of the patchset.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Thu, 28 Sep 2017 13:03:05 +0000 (09:03 -0400)]
Merge git://git.denx.de/u-boot-nds32
Patrice Chotard [Mon, 4 Sep 2017 15:56:22 +0000 (17:56 +0200)]
mmc: Add MMC support for stm32h7 Socs
This patch adds SD/MMC support for STM32H7 SoCs.
Here is an extraction of SDMMC main features, embedded in
STM32H7 SoCs.
The SD/MMC block include the following:
_ Full compliance with MultiMediaCard System Specification
Version 4.51. Card support for three different databus modes:
1-bit (default), 4-bit and 8-bit.
_ Full compatibility with previous versions of MultiMediaCards
(backward compatibility).
_ Full compliance with SD memory card specifications version 4.1.
(SDR104 SDMMC_CK speed limited to maximum allowed IO speed,
SPI mode and UHS-II mode not supported).
_ Full compliance with SDIO card specification version 4.0.
Card support for two different databus modes: 1-bit (default)
and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO
speed, SPI mode and UHS-II mode not supported).
_ Data transfer up to 208 Mbyte/s for the 8 bit mode.
(depending maximum allowed IO speed).
_ Data and command output enable signals to control external
bidirectional drivers.
The current version of the SDMMC supports only one SD/SDIO/MMC card
at any one time and a stack of MMC Version 4.51 or previous.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
rick [Thu, 21 Sep 2017 02:14:56 +0000 (10:14 +0800)]
nds32: Fix io.h warning message about readb
It is caused from asm/io.h declare different input type.
Signed-off-by: rick <rick@andestech.com>
Tom Rini [Wed, 27 Sep 2017 13:39:48 +0000 (09:39 -0400)]
Merge git://git.denx.de/u-boot-usb
Seung-Woo Kim [Mon, 31 Jul 2017 09:08:10 +0000 (18:08 +0900)]
usb: dwc2: Align size of invalidating dcache before starting DMA
During using dwc2 usb gadget, if usb message size is too small,
following cache misaligned warning is shown:
CACHE: Misaligned operation at range [
bfdbcb00,
bfdbcb04]
Align size of invalidating dcache before starting DMA to remove the
warning.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Bin Meng [Wed, 13 Sep 2017 08:19:43 +0000 (01:19 -0700)]
usb: kbd: Set a default polling mechanism for USB keyboard
The choice of "USB keyboard polling" cannot be optional as without
one mechanism being set, it just doesn't work. Set the default one
to CONFIG_SYS_USB_EVENT_POLL.
Fixes:
ecad7051 ("configs: Migrate all of the existing USB symbols, except fastboot")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Philipp Tomsich [Tue, 12 Sep 2017 15:32:28 +0000 (17:32 +0200)]
usb: host: ehci-generic: convert to livetree
Update the generic EHCI driver to support a live tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Tue, 12 Sep 2017 15:32:27 +0000 (17:32 +0200)]
usb: dwc2: convert to livetree
Update the DWC2 USB driver to support a live tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Tue, 12 Sep 2017 15:32:25 +0000 (17:32 +0200)]
rockchip: xhci: Convert to livetree
Update the Rockchip xhci wrapper driver to support a live device tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Bin Meng [Thu, 7 Sep 2017 13:13:21 +0000 (06:13 -0700)]
dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled
When EHCD and xHCD are enabled at the same time, USB storage device
driver will fail to read/write from/to the storage device attached
to the xHCI interface, due to its transfer blocks exceeds the xHCD
driver limitation.
With driver model, we have an API to get the controller's maximum
transfer size and we can use that to determine the storage driver's
capability of read/write.
Note: the non-DM version driver is still broken with xHCD and the
intent here is not to fix the non-DM one, since the xHCD itself is
already broken in places like 3.0 hub support, etc.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 7 Sep 2017 13:13:20 +0000 (06:13 -0700)]
usb: storage: Refactor to use max_xfer_blk from struct us_data
This adds a new memeber max_xfer_blk in struct us_data to record
the maximum number of transfer blocks for the storage device.
It is set per HCD setting, and so far is to 65535 for EHCD and 20
for everything else.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 7 Sep 2017 13:13:19 +0000 (06:13 -0700)]
dm: usb: ehci: Implement get_max_xfer_size() operation
EHCD can handle any transfer length as long as there is enough free
heap space left, hence set the theoretical max number SIZE_MAX.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 7 Sep 2017 13:13:18 +0000 (06:13 -0700)]
dm: usb: xhci: Implement get_max_xfer_size() operation
xHCD allocates one segment which includes 64 TRBs for each endpoint
and the last TRB in this segment is configured as a link TRB to form
a TRB ring. Each TRB can transfer up to 64K bytes, however data
buffers referenced by transfer TRBs shall not span 64KB boundaries.
Hence the maximum number of TRBs we can use in one transfer is 62.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 7 Sep 2017 13:13:17 +0000 (06:13 -0700)]
dm: usb: Add a new USB controller operation 'get_max_xfer_size'
The HCD may have limitation on the maximum bytes to be transferred
in a USB transfer. USB class driver needs to be aware of this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Marek Vasut [Tue, 12 Sep 2017 21:02:08 +0000 (23:02 +0200)]
usb: xhci: Set number of event segments and entries to 1
The Linux kernel driver sets the number of event segments and entries
to 1 , while the initial import of the xhci code set that values to 3
for reasons unknown. While most controllers are fine with more event
segments with more entries, there are standard-conformant controllers
(ie. Renesas RCar xHCI) which only support 1 event segment.
Set the number of event segments and event entries back to 1 to allow
such controllers to work with U-Boot xHCI stack. Note that the Renesas
controller correctly indicates ERST Max = 1 in HCSPARAMS2[7:4] .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Tue, 26 Sep 2017 23:38:04 +0000 (19:38 -0400)]
Merge git://www.denx.de/git/u-boot-cfi-flash
Heinrich Schuchardt [Thu, 21 Sep 2017 17:03:06 +0000 (19:03 +0200)]
GPT: incomplete initialization in allocate_disk_part
memset(newpart, '\0', sizeof(newpart));
only initializes the firest 4 or 8 bytes of *newpart and not the whole
structure disk_part.
We should use sizeof(struct disk_part).
Instead of malloc and memset we can use calloc.
Identified by cppcheck.
Fixes:
09a49930e41 GPT: read partition table from device into a data structure
Reported-by: Coverity (CID: 167228)
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 26 Sep 2017 12:26:57 +0000 (08:26 -0400)]
Merge git://www.denx.de/git/u-boot-marvell
Marek Vasut [Tue, 12 Sep 2017 17:09:31 +0000 (19:09 +0200)]
mtd: cfi: Add support for status register polling
The status register is optional in the AMD command sets, but it's
presence can be checked by reading out CFI table entry 0xc bit 0.
If the register is present, prefer using it's bit 7 to determine
if the flash is busy over reading the flash ; this is needed ie.
on Hyperflash memories.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Vasut [Tue, 12 Sep 2017 17:09:08 +0000 (19:09 +0200)]
mtd: cfi: Zap cfi_flash_base in DM case
Embed the flash base into struct flash_info instead of having ad-hoc
static array in the code. This does not only remove static variable,
but also allows CFI-like controllers, ie. HyperFlash ones, to use most
of the CFI flash code by populating the flash_info with matching base
address.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Baruch Siach [Sun, 24 Sep 2017 12:50:18 +0000 (15:50 +0300)]
arm: mvebu: clearfog: document boot from UART
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
Baruch Siach [Sun, 24 Sep 2017 12:50:17 +0000 (15:50 +0300)]
arm: mvebu: fix boot from UART on ClearFog Base
The ClearFog Base boot from UART when setting the DIP switches to 01001.
Unfortunately, the SPL code sometimes fails to detect the UART boot
method at run-time. Add an alternative SAR UART boot value to fix this.
Note that this alternative value is not documented (Armada 38x Hardware
Specifications, Table 48). But experimentations showed it on the
ClearFog Base.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Fri, 22 Sep 2017 16:50:31 +0000 (04:50 +1200)]
ARM: mvebu: handle unused DRAM banks with ECC enabled
dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not
work because mvebu_sdram_bs() returns 0 and the code was subtracting 1
before checking the size. Remove the -1 from the bank size and the +1
from the total which will skip unused banks and still calculate the
correct size. Put the -1 where it is needed for scrubbing via the xor
engine.
Reported-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Tue, 5 Sep 2017 05:03:26 +0000 (17:03 +1200)]
ARM: mvebu: add SAR frequency values for 1.8/2.0GHz
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these
variants to the sar_freq_tab.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Joshua Scott [Mon, 4 Sep 2017 05:38:32 +0000 (17:38 +1200)]
ARM: mvebu: add additional information to board_add_ram_info()
Display more information about the current RAM configuration. With these
changes the output on a 88F6820 board is
SoC: MV88F6820-A0 at 1600 MHz
DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled)
Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Mon, 4 Sep 2017 05:38:31 +0000 (17:38 +1200)]
ARM: mvebu: Add SoC IDs for Marvell's integrated CPUs
These SoCs are network packet processors (switch chips) with integrated
ARMv7 cores. They share a great deal of commonality with the Armada-XP
CPUs.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Wed, 30 Aug 2017 07:55:01 +0000 (09:55 +0200)]
arm: mvebu: Remove theadorable_defconfig
Currently, we support 2 "theadorable" MVEBU build targets. One with a
stripped down configuration (theadorable) and one with a full blown
configuration (theadorable_debug), including PCI, ethernet etc. When
we introduced these configs, the plan was to remove the debug version
at some point. But now it seems better to keep the full-blown version
and remove the "non-debug" version instead.
At a later stage, I will rename the remaining "theadorable_debug"
target into a more fitting one.
Signed-off-by: Stefan Roese <sr@denx.de>