Iago Toral Quiroga [Mon, 22 Nov 2021 10:27:41 +0000 (11:27 +0100)]
broadcom/compiler: fix scoreboard locking checks
According to the spec the hardware locks the scoreboard on the first
or last thread switch (selected via shader state) and any TLB accesses
executed before this are not synchronized by hardware.
This change updates the logic to ensure we respect this requirement
and that we don't assume that the lock is acquired automatically
on the first TLB access, which is not valid at least since V3D 4.1+.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13910>
Iago Toral Quiroga [Mon, 22 Nov 2021 11:23:13 +0000 (12:23 +0100)]
broadcom/compiler: don't allow RF writes from signals after thrend
Writes to physical registers are not allowed after thread end. We
were checking this for ALU writes, but we need to check it for
signal writes too.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13910>
Danylo Piliaiev [Fri, 19 Nov 2021 12:00:54 +0000 (14:00 +0200)]
ir3: print half-dst/src for ldib.b/stib.b
So it would print:
ldib.b.untyped.1d.u16.1.imm.base0 hr0.z, r0.x, 0
instead of:
ldib.b.untyped.1d.u16.1.imm.base0 r0.z, r0.x, 0
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13876>
Lionel Landwerlin [Thu, 18 Nov 2021 11:37:18 +0000 (13:37 +0200)]
intel: move timestamp scaling helper to intel/perf
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Lionel Landwerlin [Wed, 17 Nov 2021 08:31:54 +0000 (10:31 +0200)]
intel/ds: remove verbose messages
At high frequency sampling, this generates a lot of messages.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Lionel Landwerlin [Tue, 16 Nov 2021 22:43:16 +0000 (00:43 +0200)]
intel/pps: tweak intel config some more
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Lionel Landwerlin [Mon, 8 Nov 2021 22:33:33 +0000 (00:33 +0200)]
intel/ds: isolate intel/perf from the pps-producer
Otherwise we need to include intel headers in generic code.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Lionel Landwerlin [Mon, 8 Nov 2021 22:32:41 +0000 (00:32 +0200)]
intel/ds: drop unused constructors
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Lionel Landwerlin [Sun, 7 Nov 2021 22:12:15 +0000 (00:12 +0200)]
intel/perf: track end timestamp of queries
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Lionel Landwerlin [Sun, 7 Nov 2021 22:09:08 +0000 (00:09 +0200)]
intel/ds: drop timestamp correlation code
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Lionel Landwerlin [Wed, 17 Nov 2021 08:34:23 +0000 (10:34 +0200)]
pps: fixup sporadic missing counters
The issue seems to be that without proper timestamps & clock_id, the
recording might discard some packets if they go backward in time.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Lionel Landwerlin [Sun, 7 Nov 2021 22:10:06 +0000 (00:10 +0200)]
intel/perf: add a helper to read timestamp from reports
On newer HW it will require more work than just reading a dword. It
could also vary depending on the report format.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Lionel Landwerlin [Sun, 7 Nov 2021 21:41:05 +0000 (23:41 +0200)]
pps: allow drivers to report timestamps in their own time domain
For this each driver must :
- report its clock_id (if no particular clock just default to cpu
boottime one)
- be able to sample its clock (gpu_timestamp())
The PPSDataSource will then emit timestamp correlation events in the
trace ensuring perfetto is able to display GPU & CPU events
appropriately on its timeline.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
Juan A. Suarez Romero [Fri, 19 Nov 2021 18:09:56 +0000 (19:09 +0100)]
broadcom/compiler: apply constant folding on early GS lowering
This solves a case where a NIR geometry shader was storing the output in
a non-constant:
vec4 32 ssa_1 = load_const (0xc0800000 /* -4.000000 */, 0xc1100000 /* -9.000000 */, 0x40400000 /* 3.000000 */, 0x40e00000 /* 7.000000 */)
vec1 32 ssa_7 = load_const (0x00000000 /* 0.000000 */)
vec1 32 ssa_8 = load_const (0x00000001 /* 0.000000 */)
vec1 32 ssa_9 = iadd ssa_7, ssa_8
vec1 32 ssa_19 = mov ssa_1.x
intrinsic store_output (ssa_19, ssa_9) (1, 1, 0, 160, 288) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=32 slots=2 gs_streams(x=0 y=0 z=0 w=0) */
When lowering the VPM output we check if the destination (ssa_9 in this
case) is a constant to add to the VPM offset. We run a constant folding
optimization in an earlier VS lowering, and we should do the same for
GS.
This fixes multiple dEQP-VK.pipeline.interface_matching.* failures.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13884>
Juan A. Suarez Romero [Fri, 19 Nov 2021 18:07:24 +0000 (19:07 +0100)]
broadcom/compiler: handle array of structs in GS/FS inputs
While fragment and geometry shader were handling structs as inputs, they
weren't doing for it arrays of structures.
This fixes multiple dEQP-VK.pipeline.interface_matching.* failures and
assertions.
v2:
- Fix style (Iago).
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13884>
Lionel Landwerlin [Tue, 29 Jun 2021 09:40:39 +0000 (12:40 +0300)]
intel/fs: fix shader call lowering pass
Now that we removed the intel intrinsic and just use the generic one,
we can skip it in the intel call lowering pass and just deal with it
in the intel rt intrinsic lowering.
v2: rewrite with nir_shader_instructions_pass() (Jason)
v3: handle everything in switch (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
423c47de991643 ("nir: drop the btd_resume_intel intrinsic")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12113>
Jesse Natalie [Sat, 20 Nov 2021 15:00:58 +0000 (07:00 -0800)]
CI/windows: Upload result.txt as an artifact
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13893>
Jesse Natalie [Sat, 20 Nov 2021 05:12:52 +0000 (21:12 -0800)]
CI/windows: Uprev piglit
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13893>
Alex Xu (Hello71) [Thu, 2 Sep 2021 16:19:53 +0000 (12:19 -0400)]
Auto-enable TLSDESC support
TLSDESC speeds up access to dynamic TLS. This is especially important
for non-glibc targets, but is also helpful for non-initial-exec TLS
variables.
The entry asm does not support TLSDESC, but it only accesses
initial-exec symbols, so it is not necessary to handle that separately.
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12722>
Alex Xu (Hello71) [Thu, 2 Sep 2021 15:58:32 +0000 (11:58 -0400)]
Use initial-exec TLS for glibc only, enable TLS elsewhere
It is not portable to use initial-exec TLS in dlopened libraries. glibc
and FreeBSD allocate extra memory for extra initial-exec variables
specifically for libGL, but other libcs including musl do not.
Keep initial-exec disabled on FreeBSD since it is apparently broken for
some reason:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/966#note_394512
https://github.com/jbeich/mesa/commit/
81dbdb15d55054242eded0eb2f32621d583c1aaf
Enable TLS on OpenBSD and Haiku based on the u_thread.h comment that
emutls is better than pthread_getspecific, which seems plausible given
that emutls has strictly more information to work with.
Fixes #966.
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12722>
Ilia Mirkin [Fri, 12 Nov 2021 03:07:17 +0000 (22:07 -0500)]
mesa: move around current texture object fetching
We have to validate the target before fetching the current texture
object. Move this so that it happens later.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13767>
Ilia Mirkin [Fri, 12 Nov 2021 02:47:15 +0000 (21:47 -0500)]
mesa: check target/format for Tex(ture)StorageMem*
Noticed while doing an audit around _mesa_get_current_tex usage.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13767>
Mauro Rossi [Fri, 19 Nov 2021 23:47:18 +0000 (00:47 +0100)]
android: define cpp_rtti=false because libLLVM is built w/o RTTI
libLLVM for Android is built without RTTI, but after commit ad86267
mesa inherits meson default RTTI enabled state
cpp_rtti=false is added to meson options in android/mesa3d_cross.mk
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13888>
Marek Olšák [Wed, 17 Nov 2021 06:08:12 +0000 (01:08 -0500)]
radeonsi: deduplicate min_esverts code in gfx10_ngg_calculate_subgroup_info
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
Marek Olšák [Wed, 17 Nov 2021 02:56:05 +0000 (21:56 -0500)]
radeonsi: implement shader culling in GS
It already does compaction, so we just need to load vertex positions
and cull. This was easier than expected.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
Marek Olšák [Wed, 17 Nov 2021 01:26:50 +0000 (20:26 -0500)]
radeonsi: don't use ctx.stage outside of si_llvm_translate_nir
si_llvm_translate_nir() changes ctx.stage, so the outside code shouldn't
use it. This hasn't caused any issues yet. Since ctx.stage starts as 0,
the first use in this commit was a tautology.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
Marek Olšák [Wed, 17 Nov 2021 00:52:16 +0000 (19:52 -0500)]
radeonsi: simplify si_get_vs_key_outputs for GS
ngg_culling is always 0 when GS is enabled. This will change in the future.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
Marek Olšák [Wed, 17 Nov 2021 00:45:20 +0000 (19:45 -0500)]
radeonsi: add is_gs parameter into si_vs_needs_prolog
and disable the VS prolog code for GS.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
Marek Olšák [Wed, 17 Nov 2021 00:42:07 +0000 (19:42 -0500)]
radeonsi: restructure code that declares merged VS-GS and TES-GS SGPRs
no change in the SGPR layout
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
Marek Olšák [Wed, 17 Nov 2021 00:38:41 +0000 (19:38 -0500)]
radeonsi: separate culling code from VS/TES (to be reused by GS)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
Nicholas Bishop [Thu, 18 Nov 2021 19:37:24 +0000 (14:37 -0500)]
mesa/get: allow NV_pixel_buffer_object constants in GLES2
The NV_pixel_buffer_object extension can be available in a GLES2
context, so the PIXEL_PACK_BUFFER_BINDING/PIXEL_UNPACK_BUFFER_BINDING
constants should also be available.
Tested on 8086:2e12, "Mesa DRI Intel(R) Q45/Q43 (ELK)".
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5655
Signed-off-by: Nicholas Bishop <nicholasbishop@google.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13862>
Jesse Natalie [Wed, 22 Sep 2021 21:47:50 +0000 (14:47 -0700)]
d3d12: Validate opened D3D12 resource matches pipe template
Unlike Linux dma-bufs, D3D12 resources are strongly typed, and
can't necessarily just reinterpret the memory arbitrarily.
Allow importing resources with no description coming from the frontend,
and populate the resource desc from the driver instead. If there was
a template, make sure that it matches the incoming resource.
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Wed, 17 Nov 2021 23:41:39 +0000 (15:41 -0800)]
d3d12: Generate a pipe format -> typeless mapping table too
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Wed, 17 Nov 2021 23:29:03 +0000 (15:29 -0800)]
d3d12: Generate format table using a macro list
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Wed, 17 Nov 2021 23:23:54 +0000 (15:23 -0800)]
d3d12: Make format list all use macros
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Sun, 8 Aug 2021 02:18:19 +0000 (19:18 -0700)]
d3d12: Handle import/export of fd shared handles
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Fri, 24 Sep 2021 15:41:53 +0000 (08:41 -0700)]
winsys/d3d12: Populate winsys handle format
All other winsys handle users do so, and a future commit will
start caring about it.
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Wed, 22 Sep 2021 19:06:58 +0000 (12:06 -0700)]
gallium, windows: Use HANDLE instead of FD for external objects
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Wed, 21 Jul 2021 18:44:48 +0000 (11:44 -0700)]
microsoft/compiler: Handle GLES external textures
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Wed, 11 Aug 2021 21:43:52 +0000 (14:43 -0700)]
d3d12: Support RGBX formats mapped to RGBA
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Sun, 26 Sep 2021 15:22:58 +0000 (08:22 -0700)]
d3d12: Support PIPE_CAP_MIXED_COLOR_DEPTH_BITS
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Sun, 26 Sep 2021 15:19:21 +0000 (08:19 -0700)]
d3d12: Support BGRA 555 and 565 formats
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
Jesse Natalie [Wed, 6 Oct 2021 19:32:05 +0000 (12:32 -0700)]
android: Allow forcing softpipe
When dealing with swrast, there's two possibilities: If you have LLVM, you get
llvmpipe, which is pretty fast. If you don't, you get softpipe, which is slow,
but does have a couple nice qualities, like being smaller and not needing
executable memory for JIT.
If you're building a driver that requires LLVM like radeonsi then you need the
LLVM stub for the build to find LLVM. But for swrast, since it can mean either
softpipe/llvmpipe, you don't strictly need LLVM. So this just makes the
Android build files flexible like the Meson build files (where you can specify
-Dllvm=disabled even if LLVM is findable).
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
Jesse Natalie [Thu, 5 Aug 2021 00:55:58 +0000 (17:55 -0700)]
android,d3d12: Support using DirectX-Headers dependency from AOSP
Note that the Android build system apparently lowercases stuff,
so add a lowercase "directx-headers" dependency which is searched first,
before falling back to the proper-cased "DirectX-Headers" dependency.
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
Jesse Natalie [Thu, 29 Jul 2021 17:09:32 +0000 (10:09 -0700)]
mesa/main, android: Log errors to logcat
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
Jesse Natalie [Thu, 18 Nov 2021 22:51:05 +0000 (14:51 -0800)]
android: Add a BOARD CFlags option so build can be customized
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13532>
Mike Blumenkrantz [Fri, 19 Nov 2021 18:41:22 +0000 (13:41 -0500)]
zink: be consistent about waiting on context queue on context destroy
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13885>
Mike Blumenkrantz [Fri, 19 Nov 2021 18:42:41 +0000 (13:42 -0500)]
zink: set batch state queue on creation
make this easier to find
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13885>
Emma Anholt [Thu, 18 Nov 2021 03:28:52 +0000 (19:28 -0800)]
freedreno/a5xx: Emit MSAA state for sysmem rendering, too.
This looked obviously wrong, we want to set the sample counts for sysmem
too just like we do on 6xx. Turns out it fixes some piglits.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
Emma Anholt [Thu, 18 Nov 2021 00:27:16 +0000 (16:27 -0800)]
freedreno/a5xx: Document the sRGB bit on RB_2D_SRC/DST info.
Noticed while looking through my set of traces for where the average bit
might be. Same spot as on a6xx.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
Emma Anholt [Thu, 18 Nov 2021 00:30:19 +0000 (16:30 -0800)]
freedreno/a5xx: Define a5xx_2d_surf_info like a6xx has.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
Emma Anholt [Thu, 18 Nov 2021 00:04:45 +0000 (16:04 -0800)]
freedreno/a6xx: Disable sample averaging on non-ubwc z24s8 MSAA blits.
The fallback path we averages unorm textures, but if we don't have ubwc on
either then we can just cast them to uint which then just takes sample 0.
The proper UBWC format I think ends up averaging, though.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
Emma Anholt [Wed, 17 Nov 2021 23:40:49 +0000 (15:40 -0800)]
freedreno/a6xx: Disable sample averaging on z/s or integer blits.
We can't generally force fd_blitter_blit() to not average in our fallback
blits, but this should at help some cases.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>
Connor Abbott [Tue, 16 Nov 2021 14:20:52 +0000 (15:20 +0100)]
ir3/lower_pcopy: Fix bug with "illegal" copies and swaps
If the source and destination were within the same full register, like
hr90.x and hr90.y (which both map to r45.x), then we'd perform the
swap/copy with the wrong register. This broke
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35 once BDA is enabled.
Fixes:
0ffcb19b9d9 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
Connor Abbott [Tue, 16 Nov 2021 14:32:58 +0000 (15:32 +0100)]
ir3/lower_pcopy: Fix shr.b illegal copy lowering
The immediate shouldn't be half-reg because the other source isn't.
Fixes an assertion failure with
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35.
Fixes:
0ffcb19b9d9 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
Connor Abbott [Tue, 16 Nov 2021 13:23:03 +0000 (14:23 +0100)]
ir3/spill: Support larger spill slot offset
This is required by
dEQP-VK.ssbo.phys.layout.random.all_shared_buffer.47, where we need to
spill a lot of pointers due to NIR CSE being a little too aggressive and
creating a large register pressure across basic blocks, too large to fit
within the boundaries of ldp/stp offsets.
Note that this will be a lot more difficult with support for "real
functions" because the base register will become unknown at compile
time. However this hack gets things working for the time being.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
Connor Abbott [Mon, 15 Nov 2021 11:53:01 +0000 (12:53 +0100)]
ir3/ra: Add missing asserts to ra_push_interval()
This would've caught the previous issue earlier. We checked that the
physreg made sense when inserting via ra_file_insert() but not
ra_push_interval() which is used for live-range splitting.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
Connor Abbott [Mon, 15 Nov 2021 11:11:07 +0000 (12:11 +0100)]
ir3/ra: Consider reg file size when swapping killed sources
Don't swap a 2-component vector of half-regs with a full reg if that
would result in the half regs going outside of the allowable half-reg
space.
Fixes:
d4b5d2a0204 ("ir3/ra: Use killed sources in register eviction")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
Jesse Natalie [Mon, 27 Sep 2021 14:24:16 +0000 (07:24 -0700)]
meson: Allow mismatching RTTI for MSVC
This might be safe to relax to all Windows compilers, but I didn't
test Clang or MinGW, so scoping to MSVC for now. For MSVC, this is
safe to mismatch, because the vftables are emitted into all objects
with "pick largest," and the definition with RTTI is larger than the
one without. This is different than the Itanium ABI, which only emits
one copy of the typeinfo in the object which defines the key method.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13064>
Jesse Natalie [Mon, 27 Sep 2021 14:23:54 +0000 (07:23 -0700)]
meson: Don't override built-in cpp_rtti option, error if it's invalid
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13064>
Lionel Landwerlin [Thu, 18 Nov 2021 21:53:48 +0000 (23:53 +0200)]
anv: initialize anv_bo_sync base fields
v2: zalloc
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
cbb13fae33a8b ("anv: Add a BO sync type")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13875>
Lionel Landwerlin [Fri, 19 Nov 2021 14:00:15 +0000 (16:00 +0200)]
anv: don't try to close fd = -1
CID: 1464334
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13879>
Samuel Pitoiset [Wed, 17 Nov 2021 19:32:44 +0000 (20:32 +0100)]
radv: ignore the descriptor set layout when creating descriptor template
From the Vulkan spec:
"This parameter is ignored if templateType is not
VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET."
This fixes an assertion about the base object type when running Yuzu
with Vulkan validation layers enabled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13846>
Samuel Pitoiset [Mon, 2 Aug 2021 16:34:08 +0000 (18:34 +0200)]
radv: allow TC-compat CMASK with storage images on GFX10+
Hardware seems to support it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12173>
Mike Blumenkrantz [Thu, 18 Nov 2021 21:27:36 +0000 (16:27 -0500)]
zink: add a compiler pass to scan for shader image use
other frontends and internal shaders won't set this
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13864>
Mike Blumenkrantz [Thu, 18 Nov 2021 14:53:58 +0000 (09:53 -0500)]
zink: explicitly init glsl
need this to be able to use other frontends
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13864>
Alejandro Piñeiro [Thu, 18 Nov 2021 11:16:43 +0000 (12:16 +0100)]
vulkan: move common format helpers to vk_format
v3dv, radv, and turnip are using several C&P format helpers (most of
them wrappers over util_format_description based helpers). methods.
This commit moves the common helpers to the already existing common
vk_format.h. For the case of v3dv we were able to remove the vk_format
header. For turnip and radv, a local vk_format.h header remains, with
methods that are only used for those drivers.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13858>
Samuel Pitoiset [Thu, 18 Nov 2021 15:58:42 +0000 (16:58 +0100)]
util/queue: fix a data race detected by TSAN when finishing the queue
Thread sanitizer complains if it detects that the pthread_barrier
is destroyed when a thread might still blocked on the barrier.
Fix this by destroying the barrier only if pthread_barrier_wait
returns PTHREAD_BARRIER_SERIAL_THREAD which is the value for success.
In practice this shouldn't fix anything serious given that this code
is only called when the disk cache is destroyed.
Original patch from Timothy Arceri.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4342
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13861>
Qiang Yu [Fri, 12 Nov 2021 06:42:54 +0000 (14:42 +0800)]
glx/dri3: fix glXQueryContext does not return GLX_RENDER_TYPE value
Cc: mesa-stable
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13772>
Emma Anholt [Wed, 17 Nov 2021 23:15:19 +0000 (15:15 -0800)]
freedreno: Stop exposing MSAA image load/store on desktop GL.
GLES doesn't support it, and blob VK doesn't support it. We could
theoretically lower it, but don't bother since it's not required. Fixes
various piglit image load/store tests.
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13852>
Alyssa Rosenzweig [Sat, 13 Nov 2021 19:52:52 +0000 (14:52 -0500)]
asahi: Fix BIND_PIPELINE sizing and alignment
Fix a bug in BIND_PIPELINE XML reported by Dougall, which cleans up
a bit of both decoder and driver.
Instead of...
* 17 bytes BIND_PIPELINE (17)
* An unused 8 byte record (25)
* A set of N 8 byte records (25 + 8 * N)
* Oops, 1 byte too many! One just disappeared (24 + 8 * N)
It seems to instead be
* 24 bytes BIND_PIPELINE (24)
* A set of N 8 byte records (24 + 8 * N)
without the sentinel record. These means the 8 byte records themselves
are shuffled, with the high byte of the pointers split from the low
word, but that's less gross than an off-by-one.
It's still not clear what the last 8 bytes of the BIND_VERTEX_PIPELINE
structure mean, or the last 4 byte of the BIND_FRAGMENT_PIPELINE
structure which seems to be a bit shorter.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sat, 13 Nov 2021 19:26:57 +0000 (14:26 -0500)]
asahi: Remove obnoxious workaround
Now that we're not hardcoded any magic BO IDs, there is no minimum
number of allocations needed. Remove the unneeded -- and obnoxious --
workaround of allocating unused BOs on startup.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sat, 13 Nov 2021 19:25:47 +0000 (14:25 -0500)]
asahi: Remove silly magic numbers
These are unnecessary now that the structure of agx_map_* is better
understood.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sat, 13 Nov 2021 19:24:01 +0000 (14:24 -0500)]
asahi: Fix agx_map_* structures
Dougall Johnson observed these structures make more sense with indices[]
first in the entries and indices[] absent from the header. Then the
sentinel entry disappears, nr_entries makes more sense, and a few magic
numbers pop out. Many thanks to Dougall's astute eyes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sat, 13 Nov 2021 18:53:43 +0000 (13:53 -0500)]
asahi: Allocate special scratch buffers
Seem to be used for preemption.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sat, 13 Nov 2021 18:53:34 +0000 (13:53 -0500)]
asahi: Deflake addresses
Reported by Dougall.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sun, 31 Oct 2021 15:13:58 +0000 (11:13 -0400)]
asahi: Rename PANDECODE->AGXDECODE
Fix remnant of the Panfrost decoder fork.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Mon, 8 Nov 2021 00:51:19 +0000 (19:51 -0500)]
pan/bi: Add XML for LD_BUFFER
Encoded like LOAD.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:15:42 +0000 (18:15 -0500)]
pan/bi: Suppress uniform validation for LD_BUFFER
Seems to be ok and used by the DDK...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 8 Nov 2021 00:50:51 +0000 (19:50 -0500)]
pan/bi: Confirm IDP unit on Valhall
Based on Anandtech which gives 8-bit dot product throughput on Valhall
under FMA and not consistent with SFU.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Thu, 4 Nov 2021 23:08:36 +0000 (19:08 -0400)]
pan/bi: Forbid unaligned staging registers on Valhall
Would've saved me some debugging with the computerator. I keep
forgetting about this nuance. Enforce it in the assembler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Thu, 4 Nov 2021 00:22:26 +0000 (20:22 -0400)]
pan/bi: Add XML for assembling Valhall image stores
Not complete yet but let's get some tests in early. Document the new
instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:19:57 +0000 (18:19 -0500)]
pan/bi: Add Valhall's special FMA_RSCALE instructions
Like Bifrost, but exposed as separate physical instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:19:08 +0000 (18:19 -0500)]
pan/bi: Add sqrt form of Valhall FREXPM
Like Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:18:55 +0000 (18:18 -0500)]
pan/bi: Add full form of Valhall MUX instruction
Like Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:18:23 +0000 (18:18 -0500)]
pan/bi: Annotate Valhall instructions with units
Based on analyzing the cycle counts reported by the Mali offline
compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Mike Blumenkrantz [Thu, 5 Aug 2021 15:32:52 +0000 (11:32 -0400)]
zink: enable PIPE_TEXTURE_TRANSFER_COMPUTE on non-cpu drivers
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13859>
Mike Blumenkrantz [Wed, 17 Nov 2021 21:45:20 +0000 (16:45 -0500)]
zink: use pb_slab_alloc_reclaimed(reclaim_all) for BAR heap sometimes
this forces a full slab reclaim any time the device is known to have a
too-small BAR in order to keep memory usage at a minimum when it might otherwise
balloon out and crash us
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13850>
Mike Blumenkrantz [Wed, 17 Nov 2021 21:43:55 +0000 (16:43 -0500)]
aux/pb: add a new slab alloc function for reclaiming all bo objects
sometimes a driver might want to always reclaim all bo objects in the course
of allocating a new bo. this is useful when it's known that a given memory
heap is very small and will likely need to keep its usage minimized
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13850>
Roland Scheidegger [Mon, 15 Nov 2021 17:27:44 +0000 (18:27 +0100)]
llvmpipe: adjust rounding for viewport scissoring
Some apps may try to use a viewport adjusted by 0.5 pixels (among other
things) to emulate d3d9 pixel center, and in this case we would end up
with incorrect "fake scissor" box (shifted by 1 pixel), hence pixels
being incorrectly scissored away when permit_linear_rasterizer is set
(this happens even if the linear rasterizer is not used in the end).
So adjust the offset so that the half-way points get rounded down instead
of up.
(This is all a bit iffy I think since we don't use fractional
boxes (with 8 subpixel bits) anywhere yet, but at least without msaa
it should work out.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13794>
Eric Engestrom [Wed, 17 Nov 2021 20:30:43 +0000 (20:30 +0000)]
docs: add 22.0 branchpoint date for perspective
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13848>
Eric Engestrom [Wed, 17 Nov 2021 20:28:17 +0000 (20:28 +0000)]
docs: add 21.3.x release schedule
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13848>
Eric Engestrom [Wed, 17 Nov 2021 20:22:05 +0000 (20:22 +0000)]
docs: update calendar and link releases notes for 21.3.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13848>
Eric Engestrom [Wed, 17 Nov 2021 20:10:19 +0000 (20:10 +0000)]
docs: add release notes for 21.3.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13848>
Samuel Pitoiset [Tue, 16 Nov 2021 10:08:15 +0000 (11:08 +0100)]
radv: disable HTILE for D32S8 format and mipmaps on GFX10
Stencil texturing with HTILE doesn't work with mipmapping on Navi10-14,
it's a hw bug. RadeonSI and PAL have a workaround too.
This fixes 35 piglit failures with Zink on Navi10.
Cc: 21.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13814>
Tomeu Vizoso [Fri, 29 Oct 2021 09:00:32 +0000 (11:00 +0200)]
ci: Uprev Crosvm
And use my fork while we upstream some improvements to Crosvm that make
it more appropriate for using in CI.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Tomeu Vizoso [Wed, 8 Sep 2021 05:52:58 +0000 (07:52 +0200)]
virgl/ci: Run each dEQP instance in its own VM
Currently we run deqp-runner inside a single VM, which makes very poor
use of the available CPUs because Virgl has a bottleneck in the VMM that
serializes everything.
With this change, we can run several Crosvm instances in a runner and
make full use of the CPUs. Getting the same coverage with 3 runners
instead of 6.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Tomeu Vizoso [Wed, 17 Nov 2021 07:33:46 +0000 (08:33 +0100)]
ci: Remove syslogd
Crosvm doesn't need it any more.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Tomeu Vizoso [Wed, 8 Sep 2021 05:42:49 +0000 (07:42 +0200)]
virgl/ci: Set GALLIVM_PERF=nopt,no_quad_lod
nopt will disable some shader optimizations that slow down test runs for
no gain.
no_quad_lod will disable some speed hacks that can cause inaccurate
results.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Tomeu Vizoso [Wed, 8 Sep 2021 05:40:23 +0000 (07:40 +0200)]
ci: Don't set GALLIVM_PERF in the scripts
Instead, let gitlab-ci.yml files define it.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>