Bin Meng [Tue, 23 Jun 2015 04:18:51 +0000 (12:18 +0800)]
x86: Add MultiProcessor (MP) table APIs
The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:50 +0000 (12:18 +0800)]
x86: Remove inline for lapic access routines
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:49 +0000 (12:18 +0800)]
x86: Add I/O APIC register access routines
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:48 +0000 (12:18 +0800)]
x86: Clean up ioapic header file
Remove all the dead/unused macros from asm/ioapic.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:47 +0000 (12:18 +0800)]
x86: Reduce PIRQ routing table size
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:46 +0000 (12:18 +0800)]
x86: Ignore function number when writing PIRQ routing table
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:45 +0000 (12:18 +0800)]
x86: Write correct bus number for the irq router
We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:44 +0000 (12:18 +0800)]
x86: queensbay: Correct Topcliff device irqs
There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.
This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:43 +0000 (12:18 +0800)]
x86: crownbay: Enable DM RTC support
Add a RTC node in the device tree to enable DM RTC support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:42 +0000 (12:18 +0800)]
cmd: date: Change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C
Currently CONFIG_DM_I2C is used in cmd_date.c for driver model,
but it should be actually CONFIG_DM_RTC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:41 +0000 (12:18 +0800)]
dm: rtc: Support mc146818 driver in driver model
Add driver model support to the mc146818 rtc driver. Also clean up
the driver a little bit for coding convention issues.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:39 +0000 (11:15 +0800)]
x86: crownbay: Add MP initialization
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(modified to remove error:
overriding the value of OF_CONTROL. Old value: "y", new value: "y")
Bin Meng [Wed, 17 Jun 2015 03:15:38 +0000 (11:15 +0800)]
x86: Clean up lapic codes
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
it is not apic related and only used by ivybridge
- Fix coding convention issues
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:37 +0000 (11:15 +0800)]
x86: Move lapic_setup() call into init_bsp()
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:36 +0000 (11:15 +0800)]
x86: Move MP initialization codes into a common place
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:35 +0000 (11:15 +0800)]
x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS
Ivybridge is not ready for U-Boot MP initialization yet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:34 +0000 (11:15 +0800)]
dm: cpu: Add a new get_count method to cpu uclass
Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the number of CPUs in the system.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Jun 2015 06:52:23 +0000 (14:52 +0800)]
x86: kconfig: Fix minor nits in MAX_CPUS
Move MAX_CPUS definition after SMP so that it shows below SMP in the
menuconfig. Also replace the leading spaces in the MAX_CPUS section
with tabs to conform coding standard.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Jun 2015 06:52:22 +0000 (14:52 +0800)]
x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP
MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Jun 2015 06:52:20 +0000 (14:52 +0800)]
x86: dm: Clean up cpu drivers
This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
cpu_x86_bind()
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Jun 2015 06:52:19 +0000 (14:52 +0800)]
dm: cpu: Test against cpu_ops->get_info in cpu_get_info()
In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
if it is NULL. It should test against cpu_ops->get_info.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Fri, 12 Jun 2015 06:52:18 +0000 (14:52 +0800)]
dm: cpu: Fix undefined ENOSYS build error
Include <errno.h> otherwise ENOSYS is undefined.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 7 Jun 2015 14:50:33 +0000 (08:50 -0600)]
dm: spi: Correct minor nits in ICH driver
Tidy up three minor problems in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Simon Glass [Sun, 7 Jun 2015 14:50:32 +0000 (08:50 -0600)]
spi: sf: Print the error code on failure
Rather than just 'ERROR', display the error code, which may be useful, at
least with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Bin Meng [Sun, 7 Jun 2015 03:33:14 +0000 (11:33 +0800)]
x86: fsp: Move FspInitEntry call to board_init_f()
The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at that time. Now we want to move it a little
bit later as part of init_sequence_f[] being called by board_init_f().
This way it looks and works better in the U-Boot initialization path.
Due to FSP's design, after calling FspInitEntry it will not return to
its caller, instead it jumps to a continuation function which is given
by bootloader with a new stack in system memory. The original stack in
the CAR is gone, but its content is perserved by FSP and described by
a bootloader temporary memory HOB. Technically we can recover anything
we had before in the previous stack, but that is way too complicated.
To make life much easier, in the FSP continuation routine we just
simply call fsp_init_done() and jump back to car_init_ret() to redo
the whole board_init_f() initialization, but this time with a non-zero
HOB list pointer saved in U-Boot's global data so that we can bypass
the FspInitEntry for the second time.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 7 Jun 2015 03:33:13 +0000 (11:33 +0800)]
x86: fsp: Load GDT before calling FspInitEntry
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP will fail to bring up the AP
due to #GP fault as AP's GDT is duplicated from BSP whose GDT is
now moved into CAR, and unfortunately FSP calls AP initialization
after it disables the CAR. So basically the BSP's GDT still refers
to the one in the CAR, whose content is no longer available, so
when AP starts up and loads its segment register, it blows up.
To resolve this, we load GDT before calling into FspInitEntry.
The GDT is the same one used in arch/x86/cpu/start16.S, which is
in the ROM and exists forever.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 7 Jun 2015 03:33:12 +0000 (11:33 +0800)]
x86: Add Kconfig options to be used by arch/x86/cpu/config.mk
Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options
and make arch/x86/cpu/config.mk use these options.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 27 Apr 2015 15:34:38 +0000 (11:34 -0400)]
builderthread.py: Keep 'SPL'
On i.MX platforms the SPL binary is called "SPL" so make sure we keep
that.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 28 Aug 2014 15:43:46 +0000 (09:43 -0600)]
RFC: Deprecate MAKEALL
Since buildman now includes most of the features of MAKEALL it is probably
time to talk about deprecating MAKEALL.
Comments welcome.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 14 Jul 2015 17:32:21 +0000 (13:32 -0400)]
Prepare v2015.07
Signed-off-by: Tom Rini <trini@konsulko.com>
Andre Przywara [Thu, 2 Jul 2015 00:04:23 +0000 (01:04 +0100)]
scsi: fix compiler warning with DEBUG and 48bit LBAs
Commit
2b42c9317db ("ahci: support LBA48 data reads for 2+TB drives")
introduced conditional code which triggers a warning when compiled
with DEBUG enabled:
In file included from common/cmd_scsi.c:12:0:
common/cmd_scsi.c: In function 'scsi_read':
include/common.h:109:4: warning: 'smallblks' may be used uninitialized in this function [-Wmaybe-uninitialized]
...
Since this is for debug only, take the easy way and initialize the
variable explicitly on declaration to avoid the warning.
(Fix a nearby whitespace error on the way.)
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
Tom Rini [Fri, 10 Jul 2015 13:40:59 +0000 (09:40 -0400)]
Merge git://git.denx.de/u-boot-samsung
Tom Rini [Fri, 10 Jul 2015 13:40:48 +0000 (09:40 -0400)]
Merge git://git.denx.de/u-boot-marvell
Masahiro Yamada [Wed, 1 Jul 2015 12:35:49 +0000 (21:35 +0900)]
mtd: fix false positive "Offset exceeds device limit" error
Since commit
09c3280754f8 (mtd, nand: Move common functions from
cmd_nand.c to common place), NAND commands would not work at all
on large devices.
=> nand read
80000000 10000 10000
NAND read: Offset exceeds device limit
=> nand erase 100000 100000
NAND erase: Offset exceeds device limit
The type of the "size" of "struct mtd_info" is uint64_t, while
mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
The chipsize is wrapped around if the argument is given with 2GB
or larger.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Stefan Roese [Mon, 29 Jun 2015 12:58:16 +0000 (14:58 +0200)]
arm: mvebu: db-88f6820-gp: Add USB/EHCI support
This patch enabled the USB/EHCI support for the Marvell
DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:15 +0000 (14:58 +0200)]
usb: Add EHCI support for Armada 38x (mvebu)
This patch adds USB EHCI host support for the common mvebu platform.
Including the Armada 38x.
Tested on DB-88F6280-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:14 +0000 (14:58 +0200)]
arm: mvebu: db-88f6820-gp.h: Add SATA/SCSI (AHCI) support
Configure and enable the SATA/SCSI (AHCI) support for the Marvell
DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:13 +0000 (14:58 +0200)]
arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38x
This patch adds support for the common AHCI controller on the Marvell
Armada 38x.
Tested on the Marvell DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:12 +0000 (14:58 +0200)]
block: ahci: Don't enable port interrupts
This patch changes the initialization of the AHCI controller to not
enable the default interrupts (DEF_PORT_IRQ). As interrupts are
not used in U-Boot in general, this should not break the common AHCI
driver operation.
This change is needed to support the Marvell Armada 38x AHCI
controller. With interrupts enabled, this results in timeouts in
ahci_device_data_io(). Not enabling these interrupts fixes this
problem and the common AHCI driver works fine.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:11 +0000 (14:58 +0200)]
arm: mvebu: db-88f6820-gp: Add MMC/SDIO support
This patch adds MMC/SDIO support to the Marvell DB-88F6820-GP board
configuration. Including support for the common partitions and
filesystems.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:10 +0000 (14:58 +0200)]
arm: mvebu: Add SDIO/SDHCI support for Armada A38x
Armada A38x implements an SDHCI compatible SDIO controller. This patch
enables the Marvell driver to support this SoC. And enables the
SDIO controller if selected by the board configuration.
Tested on Marvell DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:09 +0000 (14:58 +0200)]
mmc: sdhci.c: Add config option to use a fixed buffer for transfers
While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
following problem occured. The SPL runs in internal SRAM which is
the L2 cache locked to memory. When the MMC buffers now are located
on the stack (or bss), the SDIO controller (SDHCI) can't write into
this L2 cache memory.
This patch introduces a method to use a fixed buffer that will be
used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
This way, the board can use this buffer address located in SDRAM
for all transfers. This solves this SPL problem on the A38x and
should only be used in the SPL U-Boot version.
Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:08 +0000 (14:58 +0200)]
mmc: sdhci: Use timer based timeout detection in sdhci_send_command()
The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 15:38:05 +0000 (17:38 +0200)]
arm: mvebu: db-88f6820-gp: Add MAINTAINERS file
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Simon Glass [Fri, 3 Jul 2015 00:15:44 +0000 (18:15 -0600)]
exynos: i2c: Correct bug in pinmux selection
When driver model is not used the current code does not correctly select
the pinmux for the I2C bus. This bug was introduced by this commit:
8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Minkyu Kang [Thu, 2 Jul 2015 01:27:48 +0000 (10:27 +0900)]
arm: adds the status info for odroid-xu3
Adds the 'F:' entry for the board's defconfig
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Tang Yuantian [Thu, 9 Jul 2015 06:37:30 +0000 (14:37 +0800)]
ahci: Fix compiling warnings under 64bit platforms
When compling under 64bit platforms, there are lots of warnings,
like:
drivers/block/ahci.c:114:18: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
^
drivers/block/ahci.c: In function ?.hci_host_init?.
drivers/block/ahci.c:218:49: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
......
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Yegor Yefremov [Thu, 9 Jul 2015 11:34:24 +0000 (13:34 +0200)]
arm: baltos: change USB ports functions
Baltos has USB0 connected to a USB hub and thus is host-only. USB1
is connected to microUSB connector and thus should use OTG mode.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Michael Scherban [Fri, 26 Jun 2015 14:17:31 +0000 (09:17 -0500)]
keystone2: config: update default mtd
Because it is possible for the MTD number to change, causing a
filesystem mount failure, we should use the volume name instead
of the MTD number and let Linux resolve the correct one.
Signed-off-by: Mike Scherban <m-scherban@ti.com>
Antonio Borneo [Wed, 1 Jul 2015 08:04:14 +0000 (16:04 +0800)]
stm32f4: fix gpio description in comment
On STM32F429 gpio PC6/PC7 can be allocated for USART6, as
reported in the comment.
But current code in
drivers/serial/serial_stm32.c
uses a different gpio mapping (PG14/PG9) for USART6.
Fix the comment to match current code in the driver.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: u-boot@lists.denx.de
To: Kamil Lulko <rev13@wp.pl>
Cc: Tom Rini <trini@konsulko.com>
Antonio Borneo [Wed, 1 Jul 2015 06:15:03 +0000 (14:15 +0800)]
stm32f4: fix minor typo in comment
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: u-boot@lists.denx.de
To: Kamil Lulko <rev13@wp.pl>
Cc: Tom Rini <trini@konsulko.com>
Antonio Borneo [Wed, 1 Jul 2015 06:15:02 +0000 (14:15 +0800)]
stm32f4: fix MAINTAINERS file
When "scripts/get_maintainer.pl" parses "board/.../MAINTAINERS",
it uses the line containing board name as delimiter.
Without this line, the script happily mixes the lines from current
board MAINTAINERS file with lines from another file.
Fix it by adding a reasonable board name.
Tested by comparing output of:
cat board/st/stm32f429-discovery/MAINTAINERS
./scripts/get_maintainer.pl -f board/st/stm32f429-discovery
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: u-boot@lists.denx.de
To: Kamil Lulko <rev13@wp.pl>
Cc: Tom Rini <trini@konsulko.com>
Egli, Samuel [Wed, 1 Jul 2015 15:57:39 +0000 (17:57 +0200)]
siemens,am33x: adjust mtd partition
Use one mtd partition for rootfs and configuration by
means of ubi volumes and get rid of configuration partition.
We can use partition layout for both 256MB and 512MB flash.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
Yegor Yefremov [Mon, 6 Jul 2015 15:28:36 +0000 (17:28 +0200)]
arm: baltos: fix NAND boot
Specify proper U-Boot offset, enable prefetch mode,
increase bootm size and add FIT fallback, if board_name
is not present in kernel-fit.itb image.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Yegor Yefremov [Mon, 6 Jul 2015 15:28:35 +0000 (17:28 +0200)]
arm: baltos: drop I2C speed to 1000 Hz
This action is need to make I2C communication with PMIC
stable for low temperature. Print current I2C speed in
SPL for visual control.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Yegor Yefremov [Mon, 6 Jul 2015 15:28:34 +0000 (17:28 +0200)]
arm: baltos: enable CMD_NET and FIT support in defconfig
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Yegor Yefremov [Tue, 30 Jun 2015 07:59:47 +0000 (09:59 +0200)]
arm: convert am3517_crane and am3517_evm to generic boards
Add CONFIG_SYS_GENERIC_BOARD to board's config header.
Boot-tested on am3517_evm board.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Roger Quadros [Thu, 25 Jun 2015 07:25:50 +0000 (10:25 +0300)]
ARM: beagle_x15: prevent DCAN1 _wait_target_disable failure in kernel
If board is booted with transitions happening on DCAN1 pins then
the following warning is seen in the kernel at boot when the
hwmod layer initializes.
"omap_hwmod: dcan1: _wait_target_disable failed"
This is because DCAN1 module's SWAKEUP mechanism is broken
and it fails to correctly turn OFF if it sees a transition on the
DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode
while enabling/disabling DCAN1 module.
The hwmod layer enables and disables all modules at boot
and we have no opportunity to put the DCAN1 pins in safe mode
at that point.
DCAN1 is not used by u-boot so it doesn't matter to it if these
pins are in safe mode. The kernel driver correctly configures
the right mode when DCAN1 is active.
Signed-off-by: Roger Quadros <rogerq@ti.com>
[trini: s/PULLUP/PULL_UP/ based on DRA7xx EVM version of this patch]
Signed-off-by: Tom Rini <trini@konsulko.com>
Roger Quadros [Wed, 24 Jun 2015 14:00:11 +0000 (17:00 +0300)]
ARM: DRA7-evm: prevent DCAN1 _wait_target_disable failure in kernel
If board is booted with transitions happening on DCAN1 pins then
the following warning is seen in the kernel at boot when the
hwmod layer initializes.
"omap_hwmod: dcan1: _wait_target_disable failed"
This is because DCAN1 module's SWAKEUP mechanism is broken
and it fails to correctly turn OFF if it sees a transition on the
DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode
while enabling/disabling DCAN1 module.
The hwmod layer enables and disables all modules at boot
and we have no opportunity to put the DCAN1 pins in safe mode
at that point.
DCAN1 is not used by u-boot so it doesn't matter to it if these
pins are in safe mode. The kernel driver correctly configures
the right mode when DCAN1 is active.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Prabhakar Kushwaha [Thu, 2 Jul 2015 06:30:17 +0000 (12:00 +0530)]
Makefile:Add GCC flag -fno-delete-null-pointer-checks
-fdelete-null-pointer-checks flag controls global dataflow analyses and
eliminate useless checks for null pointers; It assume that if a pointer is
checked after it has already been dereferenced, it cannot be null.
This flag is enabled by default.
gcc v4.9 has more optimizations added to this option. Hence it is very
aggressive with GCC v4.9 series. Add -fno-delete-null-pointer-checks to
disable the optimization
Signed-off-by: Rohit Dharmakan <rohitarulraj@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Simon Glass [Tue, 30 Jun 2015 22:03:02 +0000 (16:03 -0600)]
ti: Add SPDX license identifier to omap.h
This also came from Linux - according to this thread it has a GPL v2
license like arch/arm/mach-omap2/mux.h:
http://lists.denx.de/pipermail/u-boot/2015-June/217827.html
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Ingrid Viitanen <ingrid.viitanen@nokia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Masahiro Yamada [Tue, 7 Jul 2015 09:47:17 +0000 (18:47 +0900)]
README.distro: fix typos
The word "partition" is doubled. Keep decent forms for the
following lines.
Also, fix some other typos while we are here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Joe Hershberger [Mon, 22 Jun 2015 22:57:37 +0000 (17:57 -0500)]
blackfin: Fix build regression due to image size
bf533-stamp, bf538f-ezkit, and cm-bf548 are very space limited.
This was introduced by:
6e0d26c0502e (net: Handle ethaddr changes as an env callback)
by enabling CONFIG_REGEX, which is too big for these boards.
This patch disables CONFIG_REGEX at the expense of working with more
than the first ethaddr.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Joe Hershberger [Mon, 22 Jun 2015 22:57:36 +0000 (17:57 -0500)]
Allow CONFIG_REGEX to be disabled when CONFIG_NET
Instead of selecting REGEX when NET is enabled, make it the default, but
allow boards that are tiny to disable it and lose functionality on all
but the first Ethernet adapter.
cm-bf548, bf538f-ezkit, and bf533-stamp need this. None appear to have
more than one Ethernet interface.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Wed, 8 Jul 2015 21:14:02 +0000 (17:14 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips
Bin Meng [Mon, 15 Jun 2015 10:40:19 +0000 (18:40 +0800)]
net: designware: Program MAC address to hardware after soft reset
commit f566c99 "net: Update hardware MAC address if it changes in env"
removes writing MAC address to designware controller after soft reset.
This makes designware ethernet port fail to work. Actually the MAC
address should always be programmed after soft reset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Hans de Goede [Wed, 8 Jul 2015 14:18:39 +0000 (16:18 +0200)]
sunxi: Adjust Ippo_q8h_v1_2_a33_1024x600 dts filename to match the upstream kernel
sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts has been merged into the upstream
Linux kernel as sun8i-a33-ippo-q8h-v1.2.dts, adjust u-boot to follow.
Note we've never shipped a final u-boot version with the old name, so this
is safe todo.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Mugunthan V N [Mon, 22 Jun 2015 09:13:10 +0000 (14:43 +0530)]
ARM: DRA72x: fix io delay calibration for ethernet
we currently use in-development IODelay values for DRA72x which are
proposed in the data sheet, however, DRA72x EVM uses DP83865 ethernet
Phy over RGMII. The PHY characteristics and routing choices made on
the EVM, make the current iodelay values fail ethernet communication.
Instead, we need to choose custom values for DRA72x-evm specifically
designed for the PHY and routing on the platform for ethernet to
function.
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Tom Rini [Tue, 7 Jul 2015 12:42:35 +0000 (08:42 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm
Yegor Yefremov [Wed, 1 Jul 2015 20:17:34 +0000 (22:17 +0200)]
board: baltos - add maintainer information
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Masahiro Yamada [Fri, 3 Jul 2015 07:13:09 +0000 (16:13 +0900)]
ARM: disable HAVE_PRIVATE_LIBGCC for ARM64
We have not supported the private library for ARM 64bit.
Prohibit ARM64 boards from enabling it until we make things ready.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Lokesh Vutla [Thu, 2 Jul 2015 04:07:59 +0000 (09:37 +0530)]
board: am43xx: Add maintainer information
am43xx_evm_ethboot/usbhost_boot_defconfig entries are
missing in MAINTAINER file. Adding entries for them.
Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Albert ARIBAUD \(3ADEV\) [Wed, 1 Jul 2015 13:28:39 +0000 (15:28 +0200)]
cairo: add missing MAINTAINERS file
This removes the following two warnings from buildman:
WARNING: no status info for 'cairo'
WARNING: no maintainers for 'cairo'
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Siva Durga Prasad Paladugu [Fri, 29 May 2015 07:54:37 +0000 (09:54 +0200)]
arm: dcc: Add uart dcc support for armv8
Added UART DCC support for armv8
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Tue, 2 Jun 2015 17:08:21 +0000 (11:08 -0600)]
Revert "break build if it would produce broken binary"
The root cause of this problem should now be fixed.
This reverts commit
a6a4c542d316b3401f0840ac5378743191bca851.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Pavel Machek <pavel@denx.de>
Tested-by: Pavel Machek <pavel@denx.de>
Simon Glass [Tue, 2 Jun 2015 17:08:20 +0000 (11:08 -0600)]
arm: Add ENTRY/ENDPROC to private libgcc functions
When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from
Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is
used to call these ARM functions, instead of plain BL, which will fail.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Pavel Machek <pavel@denx.de>
Albert ARIBAUD [Tue, 7 Jul 2015 09:38:44 +0000 (11:38 +0200)]
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Pavel Machek [Wed, 8 Apr 2015 12:15:54 +0000 (14:15 +0200)]
armv7: better comment in start.S
Fix big/small letters in comment.
Signed-off-by: Pavel Machek <pavel@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
Axel Lin [Tue, 14 Apr 2015 06:55:24 +0000 (14:55 +0800)]
gpio: lpc32xx: Use priv_data instead of platdata
The LPC32XX GPIO driver platdata currently contains GPIO state information,
which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
Tom Rini [Mon, 6 Jul 2015 01:22:22 +0000 (21:22 -0400)]
Merge branch 'master' of git.denx.de/u-boot-sunxi
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:27 +0000 (19:57 +0800)]
sunxi: Add Sinlinx SinA33 defconfig
Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has
the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO
and GPIO headers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:26 +0000 (19:57 +0800)]
sunxi: Sync sun8i dts files with the linux kernel
Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2.
This adds a dts file for Sinlinx SinA33 dev board, and the required
changes in the .dtsi files.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:25 +0000 (19:57 +0800)]
sunxi: Add support for UART0 in PB pin group on A33
The A33 adds a pinmux function for UART0 in the PB pin group.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:24 +0000 (19:57 +0800)]
sunxi: rsb: Enable R_PIO clock before configuring external pins
The original code was configuring the external pins after enabling
the R_PIO clock, which meant the configuration never made it to
the pin controller the first time in SPL.
Why this was working before is uncertain. Maybe the state was left
from a previous boot sequence, or RSB just happened to be the default
configuration. However with some A33 chips, SPL failed to configure
the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev
board.
Reordering the calls fixed this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:23 +0000 (19:57 +0800)]
sunxi: hardware-feature-specific function index defines for PORT F UART0
Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function
index defines") renamed all GPIO index defines, but missed the PORT F
UART0 setup functions.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Tom Rini [Fri, 3 Jul 2015 12:36:29 +0000 (08:36 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Conflicts:
configs/tbs2910_defconfig
configs/tqma6q_mba6_mmc_defconfig
configs/tqma6q_mba6_spi_defconfig
configs/tqma6s_mba6_mmc_defconfig
configs/tqma6s_mba6_spi_defconfig
include/configs/mx6_common.h
Signed-off-by: Tom Rini <trini@konsulko.com>
Sanchayan Maity [Mon, 8 Jun 2015 07:10:41 +0000 (12:40 +0530)]
colibri_vf: Increase console IO buffer size to 1024
Increase console IO buffer size to 1024 from the previous value of 256.
The previous value was too short for editing environment variables like
ubiboot from the console.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Daniel Schwierzeck [Wed, 1 Jul 2015 14:36:43 +0000 (16:36 +0200)]
MIPS: change 'extern inline' to 'static inline'
The kernel changed it a long time ago. Also this is now broken
on gcc-5.x.
Reported-by: Andy Kennedy <andy.kennedy@adtran.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tony Wu [Sat, 30 May 2015 07:02:39 +0000 (15:02 +0800)]
MIPS: fix missing semicolon in cacheops.h
Fix missing semicolon in cacheops.h introduced in commit
2b8bcc5a2 (MIPS: avoid .set ISA for cache operations)
Signed-off-by: Tony Wu <tung7970@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Tom Rini [Wed, 1 Jul 2015 19:38:12 +0000 (15:38 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Wed, 1 Jul 2015 19:37:56 +0000 (15:37 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
Angelo Dureghello [Sun, 21 Jun 2015 21:40:46 +0000 (23:40 +0200)]
spi: cf_qspi: fix clamp macro type check compilation warnings
Fix compilation warnings for redefined 'clamp' macro and non-uniform
clamp macro types.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Jagan Teki [Mon, 29 Jun 2015 18:18:31 +0000 (23:48 +0530)]
README: Remove CONFIG_SPI_FLASH_DATAFLASH help text
Since the help text is added in drivers/mtd/spi/Kconfig
Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 29 Jun 2015 18:17:40 +0000 (23:47 +0530)]
README: Remove CONFIG_SPI_FLASH_BAR help text
Since the help text is added in drivers/mtd/spi/Kconfig
Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 29 Jun 2015 18:02:17 +0000 (23:32 +0530)]
sf: Kconfig: Add SPI_FLASH_BAR entry
Added SPI_FLASH_BAR entry on Kconfig with help description
Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 29 Jun 2015 17:06:18 +0000 (22:36 +0530)]
defconfig: Move CONFIG_SPI_FLASH_BAR from configs
This commit moves:
- CONFIG_SPI_FLASH_BAR
from include/configs/*.h into configs/*_defconfigs
Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 29 Jun 2015 18:16:00 +0000 (23:46 +0530)]
README: Remove CONFIG_SPI_FLASH_MTD help text
Since the help text is added in drivers/mtd/spi/Kconfig
Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Sat, 27 Jun 2015 10:37:54 +0000 (16:07 +0530)]
spi: Kconfig: Add TEGRA20_SLINK entry
Added TEGRA20_SLINK entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Jagan Teki [Sat, 27 Jun 2015 10:34:05 +0000 (16:04 +0530)]
spi: Kconfig: Add TEGRA20_SFLASH entry
Added TEGRA20_SFLASH entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Jagan Teki [Sat, 27 Jun 2015 10:27:53 +0000 (15:57 +0530)]
spi: Kconfig: Add TEGRA114_SPI entry
Added TEGRA114_SPI entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>