Andy Yan [Thu, 14 Nov 2019 03:23:17 +0000 (11:23 +0800)]
doc: rockchip: Add documentation for rk3308 based boards
Add build documentation for rk3308 based boards.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:23:02 +0000 (11:23 +0800)]
rockchip: rk3308: Add support for ROC-RK3308-CC board
ROC-RK3308-CC is a rk3308 based board designed by
Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi
on board.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:22:47 +0000 (11:22 +0800)]
rockchip: rk3308: Add dts for ROC-RK3308-CC
Add dts file for ROC-RK3308-CC from firefly.
Sync form linux rockchip for v5.5-armsoc/dts64:
"arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc"
(sha1:
4403e1237be3af0977aa23ef399e3496316317a0)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:22:34 +0000 (11:22 +0800)]
rockchip: mkimage: add support for RK3308
Usage:
(1) tools/mkimage -n rk3308 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
(2) cat spl/u-boot-spl.bin >> idbloader.img
(3) upgrade_tool wl 0x40 idbloader.img
Note:
When use ddr binary from rkbin as tpl, use it replace u-boot-tpl.bin in(1)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:22:18 +0000 (11:22 +0800)]
rockchip: rk3308: Add sdram driver
A dm based dram driver for rk3308 u-boot
to get capacity.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:21:15 +0000 (11:21 +0800)]
board: rockchip: Add rk3308 evb support
Add support for rk3308 evaluation board.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:21:14 +0000 (11:21 +0800)]
arm: dts: rockchip: Add dts for rk3308 evb
Add dts for rk3308 evb, sync from the linux kernel
upstream list [0].
[0]https://patchwork.kernel.org/patch/
11201555/
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Finley Xiao [Thu, 14 Nov 2019 03:21:13 +0000 (11:21 +0800)]
rockchip: clk: Add clk driver for rk3308
Add clk controller driver for RK3308 SOC.
This patch depends on Elaine's pll patch[0].
[0]http://patchwork.ozlabs.org/patch/1183718/
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:21:12 +0000 (11:21 +0800)]
arm: rockchip: Add RK3308 SOC support
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Elaine Zhang [Fri, 25 Oct 2019 01:42:17 +0000 (09:42 +0800)]
rockchip: clk: pll: add common pll setting funcs
Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 13 Nov 2019 03:14:12 +0000 (11:14 +0800)]
rockchip: rk3399: orangepi: Add init value for vdd_log
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 13 Nov 2019 03:14:11 +0000 (11:14 +0800)]
rockchip: rk3399: khadas-edge: Add init value for vdd_log
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 13 Nov 2019 03:14:10 +0000 (11:14 +0800)]
rockchip: rk3399: rock-pi4: Add init value for vdd_log
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 13 Nov 2019 03:14:09 +0000 (11:14 +0800)]
arm64: dts: rk3399-rock960: add vdd_log and its init value
Add vdd_log node according to rock960 schematic V13.
This patch affect two boards:
- Rock960 Model A
- Ficus
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Peter Robinson [Sat, 9 Nov 2019 20:30:07 +0000 (20:30 +0000)]
rockchip: dts: rk3399-firefly: move u-boot, spl-boot-order to to the u-boot.dtsi
The u-boot specific device tree directives should be in u-boot.dtsi
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Sat, 9 Nov 2019 20:30:06 +0000 (20:30 +0000)]
rockchip: dts: rk3399-evb: move u-boot, spl-boot-order to to the u-boot.dtsi
The u-boot specific device tree directives should be in u-boot.dtsi
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Sat, 9 Nov 2019 20:30:05 +0000 (20:30 +0000)]
rockchip: dts: rk3399: move the u-boot, dm-pre-reloc to the u-boot.dtsi
The u-boot specific pieces in the dts files should be in u-boot.dtsi
not the main files, this allows easier sync with upstream. The
rk3399.dtsi has a mix of both so move them all for consistency.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix with missing pmugrf)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Vasily Khoruzhick [Sat, 9 Nov 2019 19:24:50 +0000 (11:24 -0800)]
rockchip: rk3399: split rockpro64 out of evb_rk3399
rockpro64 needs to setup I/O domains in order for USB to work in u-boot.
Since we currently don't have a driver to do that, split it into its own
board file and initialize I/O domains here.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Fri, 8 Nov 2019 23:06:30 +0000 (00:06 +0100)]
rockchip: clk: fix wrong CONFIG_IS_ENABLED handling
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so
without the leading CONFIG_. The clock drivers all wrongly check for
CONFIG_RESET_ROCKCHIP, fix that
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Fri, 8 Nov 2019 23:06:29 +0000 (00:06 +0100)]
rockchip: clk: rv1108: remove duplicate reset init
rockchip_reset_bind() already does the needed init for the reset
registers, only referenced the wrong cru structure.
So we can get rid of the open-coded reset init and just fix
the correct cru reference.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Soeren Moch [Thu, 7 Nov 2019 11:11:22 +0000 (12:11 +0100)]
arm: dts: rk3399-rockpro64: slightly increase center voltage
The rk3399 VD_CENTER voltage domain is not subject to dynamic voltage
scaling. So the regulator reset voltage of 0.9V is used on this board.
Let u-boot initialize the center voltage to 0.95V as it is done for the
VD_LOGIC domain. This avoids instability and occasional linux kernel
Opses on this board.
Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Soeren Moch [Thu, 7 Nov 2019 11:11:21 +0000 (12:11 +0100)]
arm: dts: rk3399-rockpro64: sync dts from linux kernel
The most important change for u-boot is the fix for the vdd-log pwm
voltage regulator to avoid overvoltage for the VD_LOGIC power domain.
Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Wed, 6 Nov 2019 11:43:05 +0000 (11:43 +0000)]
rockchip: rk3399: rock960: Update config for TPL
Enable TPL for rock960 like other rk3399 boards.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sat, 2 Nov 2019 04:49:02 +0000 (10:19 +0530)]
configs: Rename roc-rk3399-pc -> roc-pc-rk3399 defconfig
roc-rk3399-pc_defconfig is committed in below
commit <
8a681f4c5aa15db51ad0209734859c9fe7c29cfd> ("rockchip: rk3399:
Add ROC-RK3399-PC support")
which doesn't follow the existing defconfigs on rk3399.
So, rename as followed with other rk3399 defconfigs.
Cc: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Wed, 16 Oct 2019 15:19:40 +0000 (20:49 +0530)]
arm: dts: rk3399-roc-pc: Sync latest dts changes from Linux
Few important regulator power rails fixes are available in
linux-next, so sync them same.
Here is the last commit details:
commit <
9f7f9b610e1b7d2dc86c543ab0dfcf781bd42326> ("arm64: dts:
rockchip: Fix roc-rk3399-pc regulator input rails")
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 16 Oct 2019 09:13:32 +0000 (17:13 +0800)]
rockchip: Init driver otg_data for rk3288 usb phy
RK3288 needs to init the otg_data in board level to make the phy driver
work.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 16 Oct 2019 09:13:31 +0000 (17:13 +0800)]
rockchip: usb: Migrate to use ofnode
Migrate to use ofnode_* instead of fdt_* so that we may able to use live
dt for usb udc driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 20:19:43 +0000 (22:19 +0200)]
rockchip: add px30-evb board
The px30 evb is an evaluation board for the px30 together with a dsi-
connected display. This adds board and config files for it.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 20:18:21 +0000 (22:18 +0200)]
rockchip: add px30 architecture core
Add core architecture code to support the px30 soc.
This includes a separate tpl board file due to very limited
sram size as well as a non-dm sdram driver, as this also has
to fit into the tiny sram.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 20:12:07 +0000 (22:12 +0200)]
rockchip: add px30 devicetrees
Add px30 related devicetrees synced from the Linux kernel.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Wed, 25 Sep 2019 18:21:21 +0000 (20:21 +0200)]
rockchip: misc: read cpuid either from efuse or otp
Newer Rockchip socs use a different ip block to handle one-time-
programmable memory, so depending on what got enabled get the cpuid
from either source.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Finley Xiao [Wed, 25 Sep 2019 15:57:49 +0000 (17:57 +0200)]
misc: add driver for the Rockchip otp controller
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 12 Jul 2019 09:43:34 +0000 (11:43 +0200)]
rockchip: mkimage: add support for px30
Add the table entry for px30 socs.
The px30 has 10K of sram available.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 23 Jul 2019 23:20:29 +0000 (01:20 +0200)]
net: gmac_rockchip: add support for px30
Add the glue code to allow the px30 variant of the Rockchip gmac
to provide network functionality.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Thu, 11 Jul 2019 08:42:16 +0000 (10:42 +0200)]
rockchip: clk: add px30 clock driver
The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
David Wu [Thu, 11 Jul 2019 08:37:14 +0000 (10:37 +0200)]
pinctrl: rockchip: add px30 pinctrl driver
Add the necessary glue code to allow pinctrl setting on px30 socs.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 20:17:13 +0000 (22:17 +0200)]
rockchip: add core px30 headers
Add headers needed by the upcoming px30 support, including two
new dt-binding headers taken from the Linux kernel.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 08:12:02 +0000 (10:12 +0200)]
spl: separate SPL_FRAMEWORK config for spl and tpl
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all
cases, making the TPL bigger. There may be cases where the TPL is really
size constrained due to its underlying ram size.
Therefore introduce a new TPL_FRAMEWORK option and make the relevant
conditionals check for both. The default is set to "y if SPL_FRAMEWORK"
to mimic the previous behaviour where the TPL would always get the
SPL framework if it was enabled in SPL.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:53 +0000 (11:04 +0800)]
ram: rk3399: Fix dram setting to make dram more stable
There are some code different with rockchip vendor code which may lead
to different bugs, including:
1) Fix setting error about LPDDR3 dram size ODT.
2) Set phy io speed to 0x2.
3) Fix setting error about phy_pad_fdbk_drive.
4) Fix setting error about PI_WDQLVL_VREF_EN
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:52 +0000 (11:04 +0800)]
ram: rk3399: update calculate_stride
Update the calculation of the stride to support all the DRAM case.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:51 +0000 (11:04 +0800)]
ram: rk3399: Sync the io setting from Rockchip vendor code
The io setting are updated after some bugfix in different rk3399 boards,
sync the code from vendor.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:50 +0000 (11:04 +0800)]
ram: rockchip: update lpddr4 timing for rk3399
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip
vendor code;
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:49 +0000 (11:04 +0800)]
ram: rk3399: add support detect capacity
Add capacity detect for rk3399 so that the driver able to detect the
capacity automatically.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:48 +0000 (11:04 +0800)]
ram: rk3399: update the function of sdram_init
Clean up the sdram_init to keep sync with rockchip source code.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:47 +0000 (11:04 +0800)]
ram: rk3399: fix error about get_ddrc0_con reg addr
Correct the register to its correct name.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:46 +0000 (11:04 +0800)]
ram: rk3399: Clean up code
Clean up rk3399 dram driver source code for more readable.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:45 +0000 (11:04 +0800)]
ram: rk3399: migrate to use common code
For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:44 +0000 (11:04 +0800)]
ram: rk3328: use common sdram driver
RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:43 +0000 (11:04 +0800)]
ram: px30: add sdram driver
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.
For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:42 +0000 (11:04 +0800)]
ram: rockchip: add common msch reg definition
The noc register bit definition may be the same for different SoC while
the offset of the register may be different, add the struction
definition as common code.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:41 +0000 (11:04 +0800)]
ram: rockchip: add phy driver code for PX30
This sdram_phy_px30.c is based on PX30 SoC, the functions are common
for phy, other SoCs with similar hardware could re-use it.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:40 +0000 (11:04 +0800)]
ram: rockchip: add controller code for PX30
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common
for controller, other SoCs with similar hardware could re-use it.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:39 +0000 (11:04 +0800)]
ram: rockchip: Default enable DRAM debug info
The debug info for dram is main about the capacity related info which is
very important the board init, so set this default enable.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:38 +0000 (11:04 +0800)]
ram: rockchip: move sdram_debug function into sdram_common
The functions for dram info print are part of common code.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:37 +0000 (11:04 +0800)]
ram: rockchip: add common code for sdram driver
There are some function like os_reg setting, capacity detect functions,
can be used as common code for different Rockchip SoCs, add a
sdram_common.c for all these functions.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:36 +0000 (11:04 +0800)]
rockchip: sdram: update the sys_reg to sys_reg2
We are using sys_reg2 and sys_reg3 as ddr cap info, sync the variable
name to what we real use to avoid confuse people.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:35 +0000 (11:04 +0800)]
rockchip: sdram: extend to use sys_reg3 for capacity info
Since we have new DRAM type and to support different DRAM size in different
CS, we need more bits, so introduce sys_reg3 to record the info.
Note that the info in sys_reg3 is extension to sys_reg2 and the info in
sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as
VERSION2.
All the ENC macro are moved to sdram_common.h since the sdram.c only
need to do the info decode.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:34 +0000 (11:04 +0800)]
rockchip: sdram: move cap structure and debug function to sdram_common.h
The sdram.h suppose to be helper file for sdram.c which including dram
size decode and some u-boot related dram init interface, and all
structure and function for dram driver move to sdram_common.h
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:33 +0000 (11:04 +0800)]
ram: rockchip: rename sdram_common.c/h to sdram.c
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
so that we can use the file name sdram_common.c in dram driver for
better understand the code;
clean the related file who has use the header file at the same time.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:32 +0000 (11:04 +0800)]
ram: rockchip: rename sdram.h to sdram_rk3288.h
The header file sdram.h is used for rk3288 and similar SoCs, rename it
to make it more understandable.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Tue, 12 Nov 2019 18:40:58 +0000 (13:40 -0500)]
Merge branch '2019-11-12-migrate-SYS_REDUNDAND_ENVIRONMENT'
- Migrate the symbol CONFIG_SYS_REDUNDAND_ENVIRONMENT to Kconfig. This
is size neutral outside of two platforms with latent bugs being fixed
now and they no longer have "ENV_IS_NOWHERE" set along with their
intended location.
Tom Rini [Sun, 10 Nov 2019 16:28:03 +0000 (11:28 -0500)]
defconfigs: Migrate CONFIG_SYS_REDUNDAND_ENVIRONMENT
Move this symbol to Kconfig. As part of this we can drop a UBI-specific
symbol that was a stop-gap for not having this particular symbol in
Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 9 Nov 2019 22:49:20 +0000 (17:49 -0500)]
pfla02: Migrate CONFIG_ENV_IS_IN_SPI_FLASH to defconfig
This board is setting CONFIG_ENV_IS_IN_SPI_FLASH in the header rather
than defconfig, fix.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 9 Nov 2019 22:33:49 +0000 (17:33 -0500)]
evb-rk3128: Migrate CONFIG_ENV_IS_IN_MMC to defconfig
This board is setting CONFIG_ENV_IS_IN_MMC in the header rather than
defconfig, fix.
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 12 Nov 2019 12:18:23 +0000 (07:18 -0500)]
Merge tag 'u-boot-imx-
20191105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-
20191105
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
Tom Rini [Tue, 12 Nov 2019 02:01:10 +0000 (21:01 -0500)]
Prepare v2020.01-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 12 Nov 2019 01:04:24 +0000 (20:04 -0500)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Vignesh Rajendran [Fri, 8 Nov 2019 15:32:55 +0000 (16:32 +0100)]
gitattributes: dont treat non-text files as text
With recent update in u-boot gitattributes all files are treated as regular
text files. This creates problems with special files and repo always
shows uncommitted files like below.
Your branch is up-to-date with 'origin/master'.
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git checkout -- <file>..." to discard changes in working directory)
modified: tools/logos/compulab.bmp
modified: tools/logos/denx-comp.bmp
modified: tools/logos/toradex.bmp
To fix above problem special files bmp/ttf files are treated as binary
files in the gitattributes.
Signed-off-by: Vignesh Rajendran <vignesh.rajendran@in.bosch.com>
Signed-off-by: Veeraiyan Chidambaram <veeraiyan.chidambaram@in.bosch.com>
Michael Trimarchi [Sat, 9 Nov 2019 19:13:57 +0000 (20:13 +0100)]
.gitignore: Ignore .img files
The generated idbloader.img file that rockchip uses should
be not included in git status report
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Simon Glass [Thu, 7 Nov 2019 00:22:44 +0000 (17:22 -0700)]
binman: tegra: Adjust symbol calculation depending on end-at-4gb
A recent change adjusted the symbol calculation to work on x86 but broke
it for Tegra. In fact this is because they have different needs.
On x86 devices the code is linked to a ROM address and the end-at-4gb
property is used for the image. In this case there is no need to add the
base address of the image, since the base address is already built into
the offset and image-pos properties.
On other devices we must add the base address since the offsets start at
zero.
In addition the base address is currently added to the 'offset' and 'size'
values. It should in fact only be added to 'image-pos', since 'offset' is
relative to its parent and 'size' is not actually an address. This code
should have been adjusted when support for 'image-pos' and 'size' was
added, but it was not.
To correct these problems:
- move the code that handles adding the base address to section.py, which
can check the end-at-4gb property and which property
(offset/size/image-pos) is being read
- add the base address only when needed (only for image-pos and not if the
image uses end-at-4gb)
- add a note to the documentation
- add a separate test to cover x86 behaviour
Fixes:
15c981cc (binman: Correct symbol calculation with non-zero image base)
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tom Rini [Mon, 11 Nov 2019 19:19:32 +0000 (14:19 -0500)]
Merge tag 'u-boot-rockchip-
20191110' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
Tom Rini [Mon, 11 Nov 2019 19:19:04 +0000 (14:19 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
fsl-layerscape, pci, icid, PSCI
Kever Yang [Wed, 16 Oct 2019 08:50:03 +0000 (16:50 +0800)]
rockchip: firefly-rk3288: Enable TPL support
This patch enable TPL support for firefly-rk3288 board, which works ths
same way with other RK3288 board like Tinker, evb.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Levin Du [Thu, 17 Oct 2019 07:22:38 +0000 (15:22 +0800)]
rockchip: adding the missing "/" in entries of boot_devices
Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work
as expected. When board_boot_order() `spl-boot-order.c` meets
"same-as-spl", it gets the conf by looking the boot_devices table by boot
source, and parse the node by the conf with:
node = fdt_path_offset(blob, conf);
which will failed without the "/" indicating the path.
Currently only entries of boot_devices in rk3399 have the "/" prefix.
Therefore add the missing ones in other boards.
Signed-off-by: Levin Du <djw@t-chip.com.cn>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 18 Oct 2019 07:54:16 +0000 (15:54 +0800)]
rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to
limit the SPL size in 0x40000(start from 0) so that we don't need to do
the relocate for ATF loading.
Note that there will be separate BSS, STACK and MALLOC heap, so the size
0x40000(256KB) should be enough for SPL text.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 18 Oct 2019 07:54:15 +0000 (15:54 +0800)]
rockchip: rk3399: update SPL_STACK_R_ADDR
Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config;
default to 0x4000000(64MB) instead of 0x80000(512KB) for this address
can support all the SoCs including those may have only 64MB memory, and
also reserve enough space for atf, kernel(in falcon mode) loading.
After the ATF entry move to 0x40000, the stack from 0x80000 may be override
when loading ATF bl31.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 23 Oct 2019 03:10:36 +0000 (11:10 +0800)]
rockchip: evb-px5: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 23 Oct 2019 02:08:53 +0000 (10:08 +0800)]
rockchip: rk3328: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 18 Oct 2019 07:54:14 +0000 (15:54 +0800)]
rockchip: rk3399: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Joseph Chen [Sun, 6 Oct 2019 18:10:22 +0000 (20:10 +0200)]
common: spl: atf: support booting bl32 image
Trusted-Firmware can also initialize a secure payload to use as a trusted
execution environment. In general for the arm64 case this is provided as
separate image and uboot is supposed to also place it in a predetermined
location in memory and add the necessary parameters to the ATF boot params.
So add the possibility to get this tee payload from the provided FIT image
and setup things as necessary.
Tested on a Rockchip PX30 with mainline TF-A, mainline OP-Tee (with pending
PX30 support) and mainline 5.4-rc1 Linux kernel.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Sun, 6 Oct 2019 18:10:21 +0000 (20:10 +0200)]
rockchip: make_fit_atf.py: allow inclusion of a tee binary
A trusted execution environment should also get loaded as loadable from
a fit image, so add the possibility to present a tee.elf to make_fit_atf.py
that then gets included as additional loadable into the generated its.
For ease of integration the additional loadable is created as atf_(x+1)
after all others to re-use core generation loops.
Tested against the combinations of 1-part-atf and multi-part-atf each
time with and without a tee binary present.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Simon South [Sun, 6 Oct 2019 16:28:14 +0000 (12:28 -0400)]
ram: rk3328: Fix loading of skew values
Fix a typo that caused incorrect values to be loaded into the DRAM
controller's deskew registers.
Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Simon South [Sun, 6 Oct 2019 16:28:13 +0000 (12:28 -0400)]
ram: rk3328: Use correct frequency units in function
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units
for the DDR frequency, causing the DRAM controller to be misconfigured
in most cases.
Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Emmanuel Vadot [Tue, 8 Oct 2019 17:59:50 +0000 (19:59 +0200)]
rockchip: dts: rk3328: rock64: Add same-as-spl order
rk3328 can use same-as-spl option so next loaders are loaded from the same
medium.
Add the boot order in the rock64 dts otherwise booting from sdcard
will result in u-boot looking into the eMMC.
Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Simon South [Thu, 10 Oct 2019 19:28:36 +0000 (15:28 -0400)]
clk: rockchip: rk3328: Configure CPU clock
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.
Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Sun, 22 Sep 2019 10:06:56 +0000 (18:06 +0800)]
rockchip: rk3399: Add Leez P710 support
Specification
- Rockchip RK3399
- LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1
- TYPE-C Power supply
Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1:
"arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC"
(sha1:
fc702ed49a8668a17343811ee28214d845bfc5e6)
Signed-off-by: Andy Yan <andyshrk@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Joseph Chen [Thu, 26 Sep 2019 07:45:07 +0000 (15:45 +0800)]
power: pmic: rk809: support rk809 pmic
The RK809 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(5*BUCKs, 9*LDOs, 2*SWITCHes)
- RTC
- Clocking
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Joseph Chen [Thu, 26 Sep 2019 07:44:55 +0000 (15:44 +0800)]
power: pmic: rk817: support rk817 pmic
The RK817 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(4*BUCKs, 1* BOOST, 9*LDOs, 1*SWITCH)
- RTC
- Clocking
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Elaine Zhang [Thu, 26 Sep 2019 07:43:55 +0000 (15:43 +0800)]
power: pmic: rk805: support rk805 pmic
The RK805 are a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(4*BUCKs, 3*LDOs)
- RTC
- Clocking
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Elaine Zhang [Thu, 26 Sep 2019 07:43:54 +0000 (15:43 +0800)]
power: pmic: rk816: support rk816 pmic
The RK816 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators(4*BUCKs, 1*BOOST, 6*LDOs, 1*SWITCH)
- RTC
- Clocking
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Elaine Zhang [Thu, 26 Sep 2019 07:43:53 +0000 (15:43 +0800)]
power: regulator: rk8xx: update the driver for rk808 and rk818
In order to adapt the following pmics, make the interface more compatible.
Support buck and ldo suspend voltage setting and getting.
Supprot buck and ldo suspend enable/disable setting and getting.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Joseph Chen [Thu, 26 Sep 2019 07:43:52 +0000 (15:43 +0800)]
dm: regulator: support regulator more state
support parse regulator standard property:
regulator-off-in-suspend;
regulator-init-microvolt;
regulator-suspend-microvolt:
regulator_get_suspend_enable
regulator_set_suspend_enable
regulator_get_suspend_value
regulator_set_suspend_value
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Fri, 8 Nov 2019 19:05:07 +0000 (14:05 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb
- Assorted fixes
Tom Rini [Fri, 8 Nov 2019 14:26:18 +0000 (09:26 -0500)]
tools/img2brec.sh: Delete unused tool
This script was only used on the MX1ADS board (and possibly other MX1
platforms) to program the flash. As we no longer have any boards for
that SoC, remove this tool.
Fixes:
e570aca9474b ("mx1ads: remove board support")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 8 Nov 2019 12:27:45 +0000 (07:27 -0500)]
Merge branch '2019-11-07-master-imports'
- Add Phytium Durian Board
- Assorted bugfixes
- Allow for make ERR_PTR/PTR_ERR architecture specific
Tom Rini [Fri, 8 Nov 2019 12:26:51 +0000 (07:26 -0500)]
Merge branch '2019-11-07-ti-imports'
- LogicPD platform fixes
- Adaptive Voltage Scaling (AVS) support
- Minor bugfixes
AKASHI Takahiro [Fri, 8 Nov 2019 01:32:15 +0000 (10:32 +0900)]
cmd: move down CONFIG_CMD_BOOTEFI after CONFIG_BOOTM_VXWORKS
Due to the commit
4b0bcfa7c4ec ("Kconfig: Migrate CONFIG_BOOTM_* options")
BOOTEFI and BOOTEFI_HELLO_COMPILE (and other BOOTEFI configs) are
displayed in a long distance. This will make it difficult for us to
understand that those configurations are closely related.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Udit Agarwal [Thu, 7 Nov 2019 16:11:39 +0000 (16:11 +0000)]
freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name
Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid
conflicts with UEFI secure boot.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Udit Agarwal [Thu, 7 Nov 2019 16:11:32 +0000 (16:11 +0000)]
freescale/layerscape: Rename the config CONFIG_SECURE_BOOT name
Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict
with UEFI secure boot.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 31 Oct 2019 06:34:40 +0000 (14:34 +0800)]
configs: spi: Add the SPI_FLASH_BAR for ESPI
Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry
is missed by
commit
6d8251783641 ("configs: Don't use SPI_FLASH_BAR as default")
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>