Haojian Wu [Mon, 5 Oct 2020 10:52:03 +0000 (12:52 +0200)]
[AST][RecoveryExpr] Fix a crash on undeduced type.
We should not capture the type if the function return type is undeduced.
Reviewed By: adamcz
Differential Revision: https://reviews.llvm.org/D87350
David Spickett [Thu, 24 Sep 2020 13:50:41 +0000 (14:50 +0100)]
Reland "[lldb] Don't send invalid region addresses to lldb server"
This reverts commit
c65627a1fe3be7521fc232d633bb6df577f55269.
The test immediately after the new invalid symbol test was
failing on Windows. This was because when we called
VirtualQueryEx to get the region info for 0x0,
even if it succeeded we would call GetLastError.
Which must have picked up the last error that was set while
trying to lookup "not_an_address". Which happened to be 2.
("The system cannot find the file specified.")
To fix this only call GetLastError when we know VirtualQueryEx
has failed. (when it returns 0, which we were also checking for anyway)
Also convert memory region to an early return style
to make the logic clearer.
Reviewed By: labath, stella.stamenova
Differential Revision: https://reviews.llvm.org/D88229
Sebastian Neubauer [Wed, 30 Sep 2020 12:15:24 +0000 (14:15 +0200)]
[AMDGPU] Use tablegen for argument indices
Use tablegen generic tables to get the index of image intrinsic
arguments.
Before, the computation of which image intrinsic argument is at which
index was scattered in a few places, tablegen, the SDag instruction
selection and GlobalISel. This patch changes that, so only tablegen
contains code to compute indices and the ImageDimIntrinsicInfo table
provides these information.
Differential Revision: https://reviews.llvm.org/D86270
Nicolas Vasilache [Mon, 5 Oct 2020 09:44:27 +0000 (05:44 -0400)]
[mlir] Fix SubViewOp doc in .td
Kazushi (Jam) Marukawa [Mon, 21 Sep 2020 08:17:29 +0000 (17:17 +0900)]
[VE] Support register and frame-index pair correctly
Support register and frame-index pair correctly as operands of
generic load/store instrucitons, e.g. LD1BZXrri, STLrri, and etc.
Add regression tests also.
Differential Revision: https://reviews.llvm.org/D88779
Benjamin Kramer [Wed, 30 Sep 2020 17:19:04 +0000 (19:19 +0200)]
Promote transpose from linalg to standard dialect
While affine maps are part of the builtin memref type, there is very
limited support for manipulating them in the standard dialect. Add
transpose to the set of ops to complement the existing view/subview ops.
This is a metadata transformation that encodes the transpose into the
strides of a memref.
I'm planning to use this when lowering operations on strided memrefs,
using the transpose to remove the stride without adding a dependency on
linalg dialect.
Differential Revision: https://reviews.llvm.org/D88651
Jay Foad [Fri, 25 Sep 2020 15:07:27 +0000 (16:07 +0100)]
[AMDGPU] Make bfe patterns divergence-aware
This tends to increase code size but more importantly it reduces vgpr
usage, and could avoid costly readfirstlanes if the result needs to be
in an sgpr.
Differential Revision: https://reviews.llvm.org/D88580
Jay Foad [Fri, 25 Sep 2020 14:55:02 +0000 (15:55 +0100)]
[AMDGPU] Split R600 and GCN bfe patterns
This is in preparation for making the GCN patterns divergence-aware.
NFC.
Differential Revision: https://reviews.llvm.org/D88579
Gabriel Hjort Åkerlund [Mon, 5 Oct 2020 08:28:50 +0000 (10:28 +0200)]
[TableGen][GlobalISel] add handling of nested *_SUBREG
When nesting INSERT_SUBREG and EXTRACT_SUBREG, GlobalISelEmitter would
fail to find the register class of the nested node. This patch fixes
that for registers with subregs.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D88487
Haojian Wu [Mon, 5 Oct 2020 08:35:29 +0000 (10:35 +0200)]
[AST][RecoveryExpr] Popagate the error-bit from a VarDecl's initializer to DeclRefExpr.
The error-bit was missing, if a DeclRefExpr (which refers to a VarDecl
with a contains-errors initializer).
It could cause different violations in clang -- the DeclRefExpr is value-dependent,
but not contains-errors, `ABC<DeclRefExpr>` could produce a non-error
and non-dependent type in non-template context, which will lead to
crashes in constexpr evaluation.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D86048
Markus Lavin [Mon, 5 Oct 2020 07:27:30 +0000 (09:27 +0200)]
[DebugInfo] Improve dbg preservation in LSR.
Use SCEV to salvage additional @llvm.dbg.value that have turned into
referencing undef after transformation (and traditional
salvageDebugInfo). Before transformation compute SCEV for each
@llvm.dbg.value in the loop body and store it (along side its current
DIExpression). After transformation update those @llvm.dbg.value now
referencing undef by comparing its stored SCEV to the SCEV of the
current loop-header PHI-nodes. Allow match with offset by inserting
compensation code in the DIExpression.
Fixes : PR38815
Differential Revision: https://reviews.llvm.org/D87494
Alexey Baturo [Sun, 4 Oct 2020 13:51:04 +0000 (16:51 +0300)]
[RISCV][ASAN] mark asan as supported for RISCV64 and enable tests
[11/11] patch series to port ASAN for riscv64
These changes allow using ASAN on RISCV64 architecture.
The majority of existing tests are passing. With few exceptions (see below).
Tests we run on qemu and on "HiFive Unleashed" board.
Tests run:
```
Asan-riscv64-inline-Test - pass
Asan-riscv64-inline-Noinst-Test - pass
Asan-riscv64-calls-Noinst-Test - pass
Asan-riscv64-calls-Test - pass
```
Lit tests:
```
RISCV64LinuxConfig (282 supported, few failures)
RISCV64LinuxDynamicConfig (289 supported, few failures)
```
Lit failures:
```
TestCases/malloc_context_size.cpp - asan works, but backtrace misses some calls
TestCases/Linux/malloc_delete_mismatch.cpp - asan works, but backtrace misses some calls
TestCases/Linux/static_tls.cpp - "Can't guess glibc version" (under debugging)
TestCases/asan_and_llvm_coverage_test.cpp - missing libclang_rt.profile-riscv64.a
```
These failures are under debugging currently and shall be addressed in a
subsequent commits.
Depends On D87581
Reviewed By: eugenis, vitalybuka
Differential Revision: https://reviews.llvm.org/D87582
Jonas Devlieghere [Mon, 5 Oct 2020 06:46:26 +0000 (23:46 -0700)]
[llvm] Rename DwarfFile to DWARFFile to fix ODR violation (NFC)
Rename the DwarfFile class in DWARFLinker to DWARFFile. This is
consistent with the other DWARF classes and avoids a ODR violation with
the DwarfFile class in AsmPrinter.
Michał Górny [Mon, 5 Oct 2020 06:03:46 +0000 (23:03 -0700)]
[lldb] [test/Register] Attempt to fix x86-fp-read.test on Darwin
Darwin seems to use stmmN instead of stN. Use a regex to accept both.
Also try to actually clear st(7).
Differential revision: https://reviews.llvm.org/D88795
Craig Topper [Mon, 5 Oct 2020 03:34:31 +0000 (20:34 -0700)]
[X86] MWAITX_SAVE_RBX should not have EBX as an implicit use.
RBX was copied to a virtual register before this instruction
was created. And the EBX input for the final MWAITX is still
in a virtual register. So EBX isn't read by this pseudo.
David Blaikie [Mon, 5 Oct 2020 02:06:28 +0000 (19:06 -0700)]
llvm-dwarfdump: Don't try to parse rnglist tables when dumping CUs
It's not possible to do this in complete generality - a CU using a
sec_offset DW_AT_ranges has no way of knowing where its rnglists
contribution starts, so should not attempt to parse any full rnglist
table/header to do so. And even using FORM_rnglistx there's no need to
parse the header - the offset can be computed using the CU's DWARF
format (32 or 64) to compute offset entry sizes, and then the list
parsed at that offset without ever trying to find a rnglist contribution
header immediately prior to the rnglists_base.
Yaxun (Sam) Liu [Wed, 30 Sep 2020 03:52:03 +0000 (23:52 -0400)]
[HIP] Fix -fgpu-allow-device-init option
The option needs to be passed to both host and device compilation.
Differential Revision: https://reviews.llvm.org/D88550
Yaxun (Sam) Liu [Fri, 2 Oct 2020 12:08:26 +0000 (08:08 -0400)]
[HIP] Fix default output file for -E
By convention the default output file for -E is "-" (stdout).
This is expected by tools like ccache, which uses output
of -E to determine if a file and its dependence has changed.
Currently clang does not use stdout as default output file for -E
for HIP, which causes ccache not working.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D88730
Yaxun (Sam) Liu [Mon, 5 Oct 2020 01:32:35 +0000 (21:32 -0400)]
Recommit "[HIP] Add option --gpu-instrument-lib="
recommit
64f7790e7d2309b5d38949921a256acf8068e659 after
fixing hip-device-libs.hip.
Yaxun (Sam) Liu [Mon, 5 Oct 2020 01:27:29 +0000 (21:27 -0400)]
Revert "[HIP] Add option --gpu-instrument-lib="
This reverts commit
64f7790e7d2309b5d38949921a256acf8068e659 due
to regression in hip-device-libs.hip.
Yaxun (Sam) Liu [Wed, 30 Sep 2020 12:01:02 +0000 (08:01 -0400)]
[HIP] Add option --gpu-instrument-lib=
Add an option --gpu-instrument-lib= to allow users to specify
an instrument device library. This is for supporting -finstrument
in device code for debugging/profiling tools.
Differential Revision: https://reviews.llvm.org/D88557
David Blaikie [Mon, 5 Oct 2020 00:50:24 +0000 (17:50 -0700)]
llvm-dwarfdump: Add support for DW_RLE_startx_endx
Craig Topper [Sun, 4 Oct 2020 23:25:35 +0000 (16:25 -0700)]
[X86] Remove MWAITX_SAVE_EBX pseudo instruction. Always save/restore the full %rbx register even in gnux32.
ebx/rbx only needs to be saved when 64-bit registers are supported
anyway. It should be fine to save/restore the whole rbx register
even in gnux32 where the base is technically just ebx.
This matches what we do for cmpxchg16b where rbx is saved/restored
regardless of gnux32.
David Blaikie [Sun, 4 Oct 2020 23:01:05 +0000 (16:01 -0700)]
llvm-dwarfdump: Print addresses in debug_line to the parsed address size
Yuanfang Chen [Sat, 3 Oct 2020 00:16:22 +0000 (17:16 -0700)]
[NewPM] collapsing nested pass mangers of the same type
This is one of the reason for extra invalidations in D84959. In
practice, I don't think we have use cases needing this. This simplifies
the pipeline a bit and prune corner cases when considering
invalidations.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D85676
Yuanfang Chen [Sat, 3 Oct 2020 00:13:27 +0000 (17:13 -0700)]
[NFCI] Remove unnecessary trailing undef in RuntimeLibcalls.def
All uses of the file undef the macro already.
David Blaikie [Sun, 4 Oct 2020 22:42:03 +0000 (15:42 -0700)]
llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits
Few places did this already - refactor them all into a common helper.
Fangrui Song [Sun, 4 Oct 2020 22:34:41 +0000 (15:34 -0700)]
[DomTree] findNearestCommonDominator: assert the nodes are in tree
i.e. they cannot be unreachable from the entry (which usually indicate usage errors).
This change allows the removal of some nullptr checks.
Reviewed By: kuhar
Differential Revision: https://reviews.llvm.org/D88758
Craig Topper [Sun, 4 Oct 2020 20:53:13 +0000 (13:53 -0700)]
[X86] Correct the implicit defs/uses for the MWAITX pseudo instructions.
MWAITX doesn't touch EFLAGS so no pseudos should def EFLAGS.
The SAVE_EBX/RBX pseudos only needs to def the EBX register that
the expansion overwrites. The EAX and ECX registers are only read.
The pseudo emitted during isel that is used by the custom inserter
shouldn't have any implicit defs or uses since everything is in
vregs.
Craig Topper [Sun, 4 Oct 2020 19:17:54 +0000 (12:17 -0700)]
[X86] Remove usesCustomInserter from MWAITX_SAVE_EBX and MWAITX_SAVE_RBX. NFC
These are now emitted by a CustomInserter rather than using a custom
inserter themselves.
Stephen Neuendorffer [Sun, 4 Oct 2020 22:17:34 +0000 (15:17 -0700)]
Revert "[RFC] Factor out repetitive cmake patterns for llvm-style projects"
This reverts commit
e9b87f43bde8b5f0d8a79c5884fdce639b12e0ca.
There are issues with macros generating macros without an obvious simple fix
so I'm going to revert this and try something different.
Arthur Eubanks [Mon, 14 Sep 2020 18:22:17 +0000 (11:22 -0700)]
[Coroutines][NewPM] Fix coroutine tests under new pass manager
Some new function parameter attributes are derived under NPM.
Reviewed By: rjmccall
Differential Revision: https://reviews.llvm.org/D88760
Roman Lebedev [Sun, 4 Oct 2020 19:06:57 +0000 (22:06 +0300)]
[NFC][SCEV] Add a test with some patterns where we could treat inttoptr/ptrtoint as semi-transparent
David Blaikie [Sun, 4 Oct 2020 19:28:37 +0000 (12:28 -0700)]
llvm-dwarfdump: Skip tombstoned address ranges
Make the dumper & API a bit more informative by using the new tombstone
addresses to filter out or otherwise render more explicitly dead code
ranges.
Nikita Popov [Sun, 4 Oct 2020 20:25:28 +0000 (22:25 +0200)]
[MemCpyOpt] Add tests for call slot optimization with GEPs (NFC)
Mehdi Amini [Sat, 3 Oct 2020 03:30:21 +0000 (03:30 +0000)]
Implement callee/caller type checking for llvm.call
This aligns the behavior with the standard call as well as the LLVM verifier.
Reviewed By: ftynse, dcaballe
Differential Revision: https://reviews.llvm.org/D88362
Nikita Popov [Sun, 4 Oct 2020 19:46:50 +0000 (21:46 +0200)]
[MemCpyOpt] Don't use array allocas in tests (NFC)
Apparently querying dereferenceability of array allocations is
being intentionally penalized (https://reviews.llvm.org/D41398),
so avoid using them in tests.
Martin Storsjö [Sun, 4 Oct 2020 19:30:55 +0000 (22:30 +0300)]
[X86] Remove an accidentally added file. NFC.
This file seems to have been accidentally added as part of commit
413577a8790407d75ba834fa5668c2632fe1851e.
Fangrui Song [Sun, 4 Oct 2020 19:06:06 +0000 (12:06 -0700)]
[SDA] Fix -Wunused-function in -DLLVM_ENABLE_ASSERTIONS=off builds
LLVM GN Syncbot [Sun, 4 Oct 2020 19:10:39 +0000 (19:10 +0000)]
[gn build] Port
6c6cd5f8a97
Craig Topper [Sun, 4 Oct 2020 19:09:41 +0000 (12:09 -0700)]
[X86] Sync AESENC/DEC Key Locker builtins with gcc.
For the wide builtins, pass a single input and output pointer to
the builtins. Emit the GEPs and input loads from CGBuiltin.
Craig Topper [Sun, 4 Oct 2020 19:09:35 +0000 (12:09 -0700)]
[X86] Synchronize the encodekey builtins with gcc. Don't assume void* is 16 byte aligned.
We were taking multiple pointer arguments in the builtin.
gcc accepts a single void*.
The cast from void* to _m128i* caused the IR generation to assume
the pointer was aligned.
Instead make the builtin take a single void*, emit i8* GEPs to
adjust then cast to <2 x i64>* and perform a store with align of 1.
Craig Topper [Sun, 4 Oct 2020 19:09:29 +0000 (12:09 -0700)]
[X86] Synchronize the loadiwkey builtin operand order with gcc version.
Craig Topper [Sun, 4 Oct 2020 19:09:21 +0000 (12:09 -0700)]
[X86] Consolidate wide Key Locker intrinsics into the same header as the other Key Locker intrinsics.
Florian Hahn [Fri, 2 Oct 2020 18:01:49 +0000 (19:01 +0100)]
[VPlan] Add VPRecipeBase::toVPUser helper (NFC).
This adds a helper to convert a VPRecipeBase pointer to a VPUser, for
recipes that inherit from VPUser. Once VPRecipeBase directly inherits
from VPUser this helper can be removed.
Florian Hahn [Sat, 3 Oct 2020 16:39:35 +0000 (17:39 +0100)]
[VPlan] Account for removed users in replaceAllUsesWith.
Make sure we do not iterate using an invalid iterator.
Another small fix/step towards traversing the def-use chains in VPlan.
Roman Lebedev [Sun, 4 Oct 2020 16:50:30 +0000 (19:50 +0300)]
[NFC][clang][codegen] Autogenerate a few ARM SVE tests that are being affected by an upcoming patch
Esme-Yi [Sun, 4 Oct 2020 16:24:20 +0000 (16:24 +0000)]
[PowerPC] Add builtins for xvtdiv(dp|sp) and xvtsqrt(dp|sp).
Summary: This patch implements the builtins for xvtdivdp, xvtdivsp, xvtsqrtdp, xvtsqrtsp.
The instructions correspond to the following builtins:
int vec_test_swdiv(vector double v1, vector double v2);
int vec_test_swdivs(vector float v1, vector float v2);
int vec_test_swsqrt(vector double v1);
int vec_test_swsqrts(vector float v1);
This patch depends on D88274, which fixes the bug in copying from CRRC to GPRC/G8RC.
Reviewed By: steven.zhang, amyk
Differential Revision: https://reviews.llvm.org/D88278
Sanjay Patel [Sun, 4 Oct 2020 15:07:27 +0000 (11:07 -0400)]
[SDAG] fold x * 0.0 at node creation time
In the motivating case from https://llvm.org/PR47517
we create a node that does not get constant folded
before getNegatedExpression is attempted from some
other node, and we crash.
By moving the fold into SelectionDAG::simplifyFPBinop(),
we get the constant fold sooner and avoid the problem.
Nikita Popov [Sun, 4 Oct 2020 14:59:43 +0000 (16:59 +0200)]
[MemCpyOpt] Add additional call slot tests (NFC)
The case of a destination read between call and memcpy was not
covered anywhere (but is handled correctly).
However, a potentially throwing call between the call and the
memcpy appears to be miscompiled.
Simon Pilgrim [Sun, 4 Oct 2020 14:32:05 +0000 (15:32 +0100)]
[X86][SSE] isTargetShuffleEquivalent - ensure shuffle inputs are the correct size.
Preliminary patch for the next stage of PR45974 - we don't want to be creating 'padded' vectors on-the-fly at all in combineX86ShufflesRecursively, and only pad the source inputs if we have a definite match inside combineX86ShuffleChain.
This means that the inputs to combineX86ShuffleChain might soon be smaller than the final root value type, so we should ensure that isTargetShuffleEquivalent only matches with the inputs if they are the correct size.
Anatoly Parshintsev [Sun, 4 Oct 2020 12:26:50 +0000 (15:26 +0300)]
[RISCV][ASAN] instrumentation pass now uses proper shadow offset
[10/11] patch series to port ASAN for riscv64
Depends On D87580
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D87581
Mark de Wever [Sun, 4 Oct 2020 12:21:00 +0000 (14:21 +0200)]
[CodeGen] Improve likelihood branch weights
Bruno De Fraine discovered some issues with D85091. The branch weights
generated for `logical not` and `ternary conditional` were wrong. The
`logical and` and `logical or` differed from the code generated of
`__builtin_predict`.
Adjusted the generated code for the likelihood to match
`__builtin_predict`. The patch is based on Bruno's suggestions.
Differential Revision: https://reviews.llvm.org/D88363
Alexey Baturo [Sun, 4 Oct 2020 09:38:06 +0000 (12:38 +0300)]
[RISCV][ASAN] support code for architecture-specific parts of asan
[9/11] patch series to port ASAN for riscv64
Depends On D87579
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D87580
Roman Lebedev [Sun, 4 Oct 2020 08:27:07 +0000 (11:27 +0300)]
[OldPM] Pass manager: run SROA after (simple) loop unrolling
I have stumbled into this pretty accidentally, when rewriting
some spaghetti-like code into something more structured,
which involved using some `std::array<>`s. And to my surprise,
the `alloca`s remained, causing about `+160%` perf regression.
https://llvm-compile-time-tracker.com/compare.php?from=
bb6f4d32aac3eecb51909f4facc625219307ee68&to=
d563e66f40f9d4d145cb2050e41cb961e2b37785&stat=instructions
suggests that this has geomean compile-time cost of `+0.08%`.
Note that D68593 /
cecc0d27ad58c0aed8ef9ed99bbf691e137a0f26
already did this chage for NewPM, but left OldPM in a pessimized state.
This fixes [[ https://bugs.llvm.org/show_bug.cgi?id=40011 | PR40011 ]], [[ https://bugs.llvm.org/show_bug.cgi?id=42794 | PR42794 ]] and probably some other reports.
Reviewed By: nikic, xbolva00
Differential Revision: https://reviews.llvm.org/D87972
Alexey Baturo [Sun, 4 Oct 2020 07:31:30 +0000 (10:31 +0300)]
[RISCV][ASAN] unwind fixup
[8/11] patch series to port ASAN for riscv64
Depends On D87577
Reviewed By: eugenis, vitalybuka
Differential Revision: https://reviews.llvm.org/D87579
Jonas Devlieghere [Sun, 4 Oct 2020 05:36:28 +0000 (22:36 -0700)]
[lldb] [test/Register] Mark new FP reg tests XFAIL on Darwin
This is failing on GreenDragon:
http://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/24066/
Craig Topper [Sun, 4 Oct 2020 04:54:59 +0000 (21:54 -0700)]
[X86] LOADIWKEY, ENCODEKEY128 and ENCODEKEY256 clobber EFLAGS.
Craig Topper [Sun, 4 Oct 2020 04:42:06 +0000 (21:42 -0700)]
[X86] Add memory operand to AESENC/AESDEC Key Locker instructions.
This removes FIXMEs from selectAddr.
Craig Topper [Sun, 4 Oct 2020 00:47:52 +0000 (17:47 -0700)]
[X86] Move ENCODEKEY128/256 handling from lowering to selection.
We should avoid emitting MachineSDNodes from lowering.
We can use the the implicit def handling in InstrEmitter to avoid
manually copying from each xmm result register. We only need to
manually emit the copies for the implicit uses.
Craig Topper [Sun, 4 Oct 2020 00:12:23 +0000 (17:12 -0700)]
[X86] Remove X86ISD::MWAITX_DAG. Just match the intrinsic to the custom inserter pseudo instruction during isel.
Stephen Neuendorffer [Mon, 3 Aug 2020 18:24:15 +0000 (11:24 -0700)]
[RFC] Factor out repetitive cmake patterns for llvm-style projects
New projects (particularly out of tree) have a tendency to hijack the existing
llvm configuration options and build targets (add_llvm_library,
add_llvm_tool). This can lead to some confusion.
1) When querying a configuration variable, do we care about how LLVM was
configured, or how these options were configured for the out of tree project?
2) LLVM has lots of defaults, which are easy to miss
(e.g. LLVM_BUILD_TOOLS=ON). These options all need to be duplicated in the
CMakeLists.txt for the project.
In addition, with LLVM Incubators coming online, we need better ways for these
incubators to do things the "LLVM way" without alot of futzing. Ideally, this
would happen in a way that eases importing into the LLVM monorepo when
projects mature.
This patch creates some generic infrastructure in llvm/cmake/modules and
refactors MLIR to use this infrastructure. This should expand to include
add_xxx_library, which is by far the most complicated bit of building a
project correctly, since it has to deal with lots of shared library
configuration bits. (MLIR currently hijacks the LLVM infrastructure for
building libMLIR.so, so this needs to get refactored anyway.)
Differential Revision: https://reviews.llvm.org/D85140
Craig Topper [Sat, 3 Oct 2020 23:55:18 +0000 (16:55 -0700)]
[X86] Add X86ISD opcodes for the Key Locker AESENC*KL and AESDEC*KL instructions
Instead of emitting MachineSDNodes during lowering, emit X86ISD
opcodes. These opcodes will either be selected by tablegen
patterns or custom selection code.
Emitting MachineSDNodes during lowering is uncommon so this makes
things more consistent. It also allows selectAddr to be called to
perform address matching during instruction selection.
I had trouble getting tablegen to accept XMM0-XMM7 as results in
an isel pattern for the WIDE instructions so I had to use custom
instruction selection.
Jacques Pienaar [Sat, 3 Oct 2020 22:17:38 +0000 (15:17 -0700)]
Add indented raw_ostream class
Class simplifies keeping track of the indentation while emitting. For every new line the current indentation is simply prefixed (if not at start of line, then it just emits as normal). Add a simple Region helper that makes it easy to have the C++ scope match the emitted scope.
Use this in op doc generator and rewrite generator.
This reverts revert commit
be185b6a7355fdfeb1c31df2e1272366fe58b01f addresses shared lib failure by fixing up cmake files.
Differential Revision: https://reviews.llvm.org/D84107
Alexander Shaposhnikov [Sat, 3 Oct 2020 21:18:38 +0000 (14:18 -0700)]
[Object][MachO] Refactor MachOUniversalWriter
This diff refactors writeUniversalBinary and adds writeUniversalBinaryToBuffer.
This is a preparation for adding support for universal binaries to llvm-objcopy.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D88372
Mircea Trofin [Thu, 1 Oct 2020 21:35:11 +0000 (14:35 -0700)]
[MC] Assert that MCRegUnitIterator operates over MCRegisters
The signature of the ctor expects a MCRegister, but currently any
unsigned value can be converted to a MCRegister.
This patch checks that indeed the provided value is a physical register
only. We want to eventually stop implicitly converting unsigned or
Register to MCRegister (which is incorrect). The next step after this
patch is changing uses of MCRegUnitIterator to explicitly cast Register
or unsigned values to MCRegister. To that end, this patch also
introduces 2 APIs that make that conversion checked and explicit.
Differential Revision: https://reviews.llvm.org/D88705
Michał Górny [Sat, 3 Oct 2020 20:16:29 +0000 (22:16 +0200)]
[lldb] [test/Register] Mark new FP reg tests XFAIL on Windows
Florian Hahn [Sat, 3 Oct 2020 15:31:49 +0000 (16:31 +0100)]
[VPlan] Properly update users when updating operands.
When updating operands of a VPUser, we also have to adjust the list of
users for the new and old VPValues. This is required once we start
transitioning recipes to become VPValues.
Roman Lebedev [Sat, 3 Oct 2020 19:46:50 +0000 (22:46 +0300)]
[NFC][InstCombine] Autogenerate a few tests being affected by an upcoming patch
Roman Lebedev [Sat, 3 Oct 2020 19:32:46 +0000 (22:32 +0300)]
[NFC][PhaseOrdering] Add a test showing new inttoptr casts after SROA due to InstCombine (PR47592)
We could either try to make SROA more picky to the new type
and/or prevent InstCombine from creating the original problem (converting load-stores to operate on ints),
and/or make InstCombine recover the situation by cleaning up all that cruft.
Florian Hahn [Sat, 3 Oct 2020 19:41:41 +0000 (20:41 +0100)]
[LV] Add another test case with unsinkable first-order recurrences.
Martin Storsjö [Wed, 23 Sep 2020 12:00:53 +0000 (15:00 +0300)]
[AArch64] Prefer prologues with sp adjustments merged into stp/ldp for WinCFI, if optimizing for size
This makes the prologue match the windows canonical layout, for
cases without a frame pointer.
This can potentially be a slower (a longer dependency chain of the
sp register, and potentially one arithmetic operation more on some
cores), but gives notable size improvements.
The previous two commits shrinks a 166 KB xdata section by 49 KB,
and if the change from this commit is enabled, it shrinks the xdata
section by another 25 KB.
In total, since the start of the recent arm64 unwind info cleanups
and optimizations (since before commit
37ef743cbf3), the xdata+pdata
sections of the same test DLL has shrunk from 407 KB in total
originally, to 163 KB now.
Differential Revision: https://reviews.llvm.org/D88701
Martin Storsjö [Wed, 23 Sep 2020 11:26:45 +0000 (14:26 +0300)]
[AArch64] Allow pairing lr with other GPRs for WinCFI
This saves one instruction per prologue/epilogue for any function with
an odd number of callee-saved GPRs, but more importantly, allows such
functions to match the packed unwind format.
Differential Revision: https://reviews.llvm.org/D88699
Martin Storsjö [Wed, 23 Sep 2020 11:14:05 +0000 (14:14 +0300)]
[AArch64] Match the windows canonical callee saved register order
On windows, the callee saved registers in a canonical prologue are
ordered starting from a lower register number at a lower stack
address (with the possible gap for aligning the stack at the top);
this is the opposite order that llvm normally produces.
To achieve this, reverse the order of the registers in the
assignCalleeSavedSpillSlots callback, to get the stack objects
laid out by PrologEpilogInserter in the right order, and adjust
computeCalleeSaveRegisterPairs to lay them out from the bottom up.
This allows generated prologs more often to match the format that
allows the unwind info to be written as packed info.
Differential Revision: https://reviews.llvm.org/D88677
Nico Weber [Sat, 3 Oct 2020 18:22:53 +0000 (14:22 -0400)]
Revert "[Driver] Move detectLibcxxIncludePath to ToolChain"
This reverts commit
e25bf2592060e7751f8b14522c97081ce2047175.
Breaks tests on Windows, see comments on https://reviews.llvm.org/D88452
Nathan Lanza [Sat, 3 Oct 2020 17:38:00 +0000 (13:38 -0400)]
[clang][NFC] Change a mention of `objc_static_protocol` to `non_runtime`
Michał Górny [Wed, 30 Sep 2020 13:33:01 +0000 (15:33 +0200)]
[lldb] [test/Register] Add read/write tests for x87 regs
Add a partial read/write tests for x87 FPU registers. This includes
reading and writing ST registers, control registers and floating-point
exception data registers (fop, fip, fdp).
The tests assume the current (roughly incorrect) behavior of reporting
the 'abridged' 8-bit ftag state as 16-bit ftag. They also assume Linux
plugin behavior of reporting fip/fdp split into halves as (fiseg, fioff)
and (foseg, fooff).
Differential Revision: https://reviews.llvm.org/D88583
Michał Górny [Thu, 1 Oct 2020 17:38:49 +0000 (19:38 +0200)]
[lldb] [Process/NetBSD] Fix crash on unsupported i386 regs
Multiple fixes related to bugs discovered while debugging a crash
when reading all registers on i386.
The underlying problem was that GetSetForNativeRegNum() did not account
for MPX registers on i386, and since it only compared against upper
bounds of each known register set, the MPX registers were classified
into the wrong set and therefore considered supported. However, they
were not expected in RegNumX86ToX86_64() and caused the assertion
to fail.
This includes:
- adding (unused) i386 → x86_64 translations for MPX registers
- fixing GetSetForNativeRegNum() to check both lower and upper bound
for register sets, to avoid wrongly classifying unhandled register
sets
- adding missing range check for MPX registers on i386
- renaming k_last_mpxr to k_last_mpxr_i386 for consistency
- replacing return-assertions with llvm_unreachable() and adding more
checks for unexpected parameters
Differential Revision: https://reviews.llvm.org/D88682
Michał Górny [Thu, 1 Oct 2020 17:31:59 +0000 (19:31 +0200)]
[lldb] [Process/NetBSD] Fix reading FIP/FDP registers
Fix reading FIP/FDP registers to correctly return segment and offset
parts. On amd64, this roughly matches the Linux behavior of splitting
the 64-bit FIP/FDP into two halves, and putting the higher 32 bits
into f*seg and lower into f*off. Well, actually we use only 16 bits
of higher half but the CPUs do not seem to handle more than that anyway.
Differential Revision: https://reviews.llvm.org/D88681
Michał Górny [Sat, 3 Oct 2020 14:38:09 +0000 (16:38 +0200)]
[asan] Stop instrumenting user-defined ELF sections
Do not instrument user-defined ELF sections (whose names resemble valid
C identifiers). They may have special use semantics and modifying them
may break programs. This is e.g. the case with NetBSD __link_set API
that expects these sections to store consecutive array elements.
Differential Revision: https://reviews.llvm.org/D76665
Simon Pilgrim [Sat, 3 Oct 2020 17:32:47 +0000 (18:32 +0100)]
[InstCombine] Add tests for or(shl(x,c1),lshr(y,c2)) patterns that could fold to funnel shifts
Some initial test coverage toward fixing PR46896 - these are just copied from rotate.ll
Simon Pilgrim [Sat, 3 Oct 2020 16:51:40 +0000 (17:51 +0100)]
[Analysis] resolveAllCalls - fix use after std::move warning. NFCI.
We can't use Use.Calls after its std::move()'d to TmpCalls as it will be in an undefined state. Instead, swap with the known empty map in TmpCalls so we can then safely emplace_back into the now empty Use.Calls.
Fixes clang static analyzer warning.
Jacques Pienaar [Sat, 3 Oct 2020 16:41:35 +0000 (09:41 -0700)]
Revert "Add indented raw_ostream class"
This reverts commit
78530ce65375fa02bc96019e5cc9d73db8adaca4.
Fails on shared_lib build.
Simon Pilgrim [Sat, 3 Oct 2020 16:10:44 +0000 (17:10 +0100)]
[InstCombine] Add or(shl(v,and(x,bw-1)),lshr(v,bw-and(x,bw-1))) rotate tests
If we know the shift amount is less than the bitwidth we should be able to convert this to a rotate/funnel shift
Jacques Pienaar [Sat, 3 Oct 2020 15:53:43 +0000 (08:53 -0700)]
Add indented raw_ostream class
Class simplifies keeping track of the indentation while emitting. For every new line the current indentation is simply prefixed (if not at start of line, then it just emits as normal). Add a simple Region helper that makes it easy to have the C++ scope match the emitted scope.
Use this in op doc generator and rewrite generator.
Differential Revision: https://reviews.llvm.org/D84107
David Green [Sat, 3 Oct 2020 15:47:50 +0000 (16:47 +0100)]
[ARM] Fix pointer offset when splitting stores from VMOVDRR
We were not accounting for the pointer offset when splitting a store from
a VMOVDRR node, which could lead to incorrect aliasing info. In this
case it is the fneg via integer arithmetic that gives us a store->load
pair that we started getting wrong.
Differential Revision: https://reviews.llvm.org/D88653
Simon Pilgrim [Sat, 3 Oct 2020 15:26:29 +0000 (16:26 +0100)]
[InstCombine] recognizeBSwapOrBitReverseIdiom - add vector support
Add basic vector handling to recognizeBSwapOrBitReverseIdiom/collectBitParts - this works at the element level, all vector element operations must match (splat constants etc.) and there is no cross-element support (insert/extract/shuffle etc.).
Aaron Ballman [Sat, 3 Oct 2020 15:10:26 +0000 (11:10 -0400)]
Add a break statement to appease the build bots; NFC
Simon Pilgrim [Sat, 3 Oct 2020 14:29:05 +0000 (15:29 +0100)]
[InstCombine] recognizeBSwapOrBitReverseIdiom - use generic CreateIntegerCast
Try to appease buildbots breakages due to D88578
Andrzej Warzynski [Fri, 2 Oct 2020 08:53:35 +0000 (09:53 +0100)]
[flang][NFC] Fix build errors for clang-10
This patch fixes one worning. Since Flang sets `-Werror`, that's
sufficient for a build to fail. As per flang/README.md, Clang-10 is one
of the officially supported compilers.
Differential Revision: https://reviews.llvm.org/D88723
Bernhard Manfred Gruber [Sat, 3 Oct 2020 14:08:44 +0000 (10:08 -0400)]
modernize-use-trailing-return-type fix for PR44206
Prevent rewrite when an unqualified id in a typedef type collides
with a function argument name. Fixes PR44206.
Simon Pilgrim [Sat, 3 Oct 2020 13:52:25 +0000 (14:52 +0100)]
[InstCombine] recognizeBSwapOrBitReverseIdiom - support for 'partial' bswap patterns (PR47191) (Reapplied)
If we're bswap'ing some bytes and zero'ing the remainder we can perform this as a bswap+mask which helps us match 'partial' bswaps as a first step towards folding into a more complex bswap pattern.
Reapplied with early-out if recognizeBSwapOrBitReverseIdiom collects a source wider than the result type.
Differential Revision: https://reviews.llvm.org/D88578
Roman Lebedev [Sat, 3 Oct 2020 13:01:48 +0000 (16:01 +0300)]
[NFCI][clang-tidy] FunctionCognitiveComplexityCheck::check(): try to fix windows arm build bots
http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/1482/steps/build-llvm-project/logs/stdio
http://lab.llvm.org:8011/builders/llvm-clang-win-x-aarch64/builds/3285/steps/build-llvm-project/logs/stdio
Mark de Wever [Sat, 3 Oct 2020 12:31:46 +0000 (14:31 +0200)]
[Sema] List conversion validate character array.
The function `TryListConversion` didn't properly validate the following
part of the standard:
Otherwise, if the parameter type is a character array [... ]
and the initializer list has a single element that is an
appropriately-typed string literal (8.5.2 [dcl.init.string]), the
implicit conversion sequence is the identity conversion.
This caused the following call to `f()` to be ambiguous.
void f(int(&&)[1]);
void f(unsigned(&&)[1]);
void g(unsigned i) {
f({i});
}
This issue only occurs when the initializer list had one element.
Differential Revision: https://reviews.llvm.org/D87561
David Green [Sat, 3 Oct 2020 11:25:34 +0000 (12:25 +0100)]
[ARM] Test to show incorrect pointer info. NFC
Nikita Popov [Sat, 3 Oct 2020 09:27:33 +0000 (11:27 +0200)]
[MemCpyOpt] Make moveUp() a member method (NFC)
So we don't have to pass through more parameters in the future.
Nikita Popov [Sat, 3 Oct 2020 08:37:36 +0000 (10:37 +0200)]
[MemCpyOpt] Remove unnecessary -dse from test (NFC)
This one doesn't even have any dead stores to eliminate...
Craig Topper [Sat, 3 Oct 2020 02:10:29 +0000 (19:10 -0700)]
[X86] Key Locker instructions should use VR128 regclass not VR128X.
Evandro Menezes [Fri, 2 Oct 2020 21:30:39 +0000 (16:30 -0500)]
[PATCH] Fix typo (NFC)
Petr Hosek [Tue, 22 Sep 2020 08:01:16 +0000 (01:01 -0700)]
[Driver] Move detectLibcxxIncludePath to ToolChain
This helper method is useful even outside of Gnu toolchains, so move
it to ToolChain so it can be reused in other toolchains such as Fuchsia.
Differential Revision: https://reviews.llvm.org/D88452