Stephen Kelly [Sat, 26 Dec 2020 16:22:32 +0000 (16:22 +0000)]
[ASTMatchers] Fix traversal matchers with explicit and defaulted methods
Differential Revision: https://reviews.llvm.org/D94030
Joe Ellis [Mon, 4 Jan 2021 10:16:52 +0000 (10:16 +0000)]
[clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments
VLST arguments are coerced to VLATs at the function boundary for
consistency with the VLAT ABI. They are then bitcast back to VLSTs in
the function prolog. Previously, this conversion is done through memory.
With the introduction of the llvm.vector.{insert,extract} intrinsic, we
can avoid going through memory here.
Depends on D92761
Differential Revision: https://reviews.llvm.org/D92762
Whitney Tsang [Tue, 5 Jan 2021 15:08:46 +0000 (15:08 +0000)]
[LoopNest] Allow empty basic blocks without loops
Allow loop nests with empty basic blocks without loops in different
levels as perfect.
Reviewers: Meinersbur
Differential Revision: https://reviews.llvm.org/D93665
Florian Hahn [Tue, 5 Jan 2021 14:56:05 +0000 (14:56 +0000)]
[VPlan] Re-add interleave group members to plan.
Creating in-loop reductions relies on IR references to map
IR values to VPValues after interleave group creation.
Make sure we re-add the updated member to the plan, so the look-ups
still work as expected
This fixes a crash reported after D90562.
Simon Pilgrim [Tue, 5 Jan 2021 15:01:23 +0000 (15:01 +0000)]
[X86][AVX] combineVectorSignBitsTruncation - use PACKSS/PACKUS in more AVX cases
AVX512 has fast truncation ops, but if the truncation source is a concatenation of subvectors then its likely that we can use PACK more efficiently.
This is only guaranteed to work for truncations to 128/256-bit vectors as the PACK works across 128-bit sub-lanes, for now I've just disabled 512-bit truncation cases but we need to get them working eventually for D61129.
Stephen Kelly [Sat, 26 Dec 2020 21:11:21 +0000 (21:11 +0000)]
[ASTMatchers] Fix build when no targets are enabled
This makes sense to do when building only tools like clang-tidy for
example.
Differential Revision: https://reviews.llvm.org/D93987
Stephen Kelly [Mon, 21 Dec 2020 16:37:28 +0000 (16:37 +0000)]
[ASTMatchers] Ensure that we can match inside lambdas
Because we don't know in ASTMatchFinder whether we're matching in AsIs
or IgnoreUnlessSpelledInSource mode, we need to traverse the lambda
twice, but store whether we're matching in nodes spelled in source or
not.
Differential Revision: https://reviews.llvm.org/D93688
Alexander Belyaev [Tue, 5 Jan 2021 12:52:25 +0000 (13:52 +0100)]
[mlir] Add canonicalization pattern out_tensor->linalg->dim to out_tensor->dim.
Differential Revision: https://reviews.llvm.org/D94079
Anastasia Stulova [Tue, 5 Jan 2021 13:02:09 +0000 (13:02 +0000)]
[OpenCL] Restrict pointer to member functions.
Pointers to member functions are a special case
of function pointers and therefore have to be
disallowed.
Tags: #clang
Differential Revision: https://reviews.llvm.org/D93958
Simon Pilgrim [Tue, 5 Jan 2021 12:07:38 +0000 (12:07 +0000)]
[X86] getMemoryOpCost - use dyn_cast_or_null<StoreInst>. NFCI.
Use instead of the isa_and_nonnull<StoreInst> and use the StoreInst::getPointerOperand wrapper instead of a hardcoded Instruction::getOperand.
Looks cleaner and avoids a spurious clang static analyzer null dereference warning.
Kazushi (Jam) Marukawa [Sat, 26 Dec 2020 13:52:49 +0000 (22:52 +0900)]
[VE] Change clang to support SjLj Lowering
We supports SjLj exception handling in the backend, so changing
clang to allow lowering using SjLj exceptions. Update a regression
test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94076
Fraser Cormack [Tue, 5 Jan 2021 12:57:18 +0000 (12:57 +0000)]
[CodeGen] Format SelectionDAG::getConstant methods (NFC)
Jay Foad [Mon, 4 Jan 2021 10:54:42 +0000 (10:54 +0000)]
[AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands
Convert it to v_fma_legacy_f32 if it is profitable to do so, just like
other mac instructions that are converted to their mad equivalents.
Differential Revision: https://reviews.llvm.org/D94010
Jay Foad [Mon, 4 Jan 2021 10:45:09 +0000 (10:45 +0000)]
[AMDGPU] Precommit test case for D94010
Jay Foad [Mon, 4 Jan 2021 10:52:22 +0000 (10:52 +0000)]
[AMDGPU] Split out new helper function macToMad in SIFoldOperands. NFC.
Differential Revision: https://reviews.llvm.org/D94009
Giulio Girardi [Tue, 5 Jan 2021 11:44:04 +0000 (12:44 +0100)]
[clangd] When querying drivers by binary, look in PATH too
Sometimes compile_commands.json databases are created without an
absolute path for the driver in the command field. By default the driver
name is appended to the current directory, however if no driver is found
in that location assume it was in the default PATH and try finding it
there
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D93600
Sven van Haastregt [Tue, 5 Jan 2021 11:51:10 +0000 (11:51 +0000)]
[OpenCL] Warn about side effects for unevaluated vec_step arg
The argument to the `vec_step` builtin is not evaluated. Hoist the
diagnostic for this in `Sema::CheckUnaryExprOrTypeTraitOperand` such
that it comes before `Sema::CheckVecStepTraitOperandType`.
A minor side-effect of this change is that it also produces the
warning for `co_await` and `co_yield` as `sizeof` arguments now, which
seems to be reasonable given that the warning is emitted for `typeid`
already.
Differential Revision: https://reviews.llvm.org/D91348
Kazushi (Jam) Marukawa [Tue, 15 Dec 2020 12:50:17 +0000 (21:50 +0900)]
[VE] Support SJLJ exception related instructions
Support EH_SJLJ_LONGJMP, EH_SJLJ_SETJMP, and EH_SJLJ_SETUP_DISPATCH
for SjLj exception handling. NC++ uses SjLj exception handling, so
implement it first. Add regression tests also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94071
Simon Pilgrim [Tue, 5 Jan 2021 10:56:13 +0000 (10:56 +0000)]
[IR] Add ConstantInt::getBool helpers to wrap getTrue/getFalse.
Paul Walker [Fri, 18 Dec 2020 17:06:32 +0000 (17:06 +0000)]
[SVE] Lower vector CTLZ, CTPOP and CTTZ operations.
CTLZ and CTPOP are lowered to CLZ and CNT instructions respectively.
CTTZ is not a native SVE operation but is instead lowered to:
CTTZ(V) => CTLZ(BITREVERSE(V))
In the case of fixed-length support using SVE we also lower CTTZ
operating on NEON sized vectors because of its reliance on
BITREVERSE which is also lowered to SVE intructions at these lengths.
Differential Revision: https://reviews.llvm.org/D93607
Florian Hahn [Tue, 5 Jan 2021 10:30:48 +0000 (10:30 +0000)]
[LV] Simplify lambda in all_of to directly return hasVF() result. (NFC)
The if in the lambda is not necessary. We can directly return the result
of hasVF.
Simon Pilgrim [Tue, 5 Jan 2021 10:24:37 +0000 (10:24 +0000)]
[SimplifyIndVar] createWideIV - make WideIVInfo arg a const ref. NFCI.
The WideIVInfo arg is only ever used as a const.
Fixes cppcheck warning.
Simon Pilgrim [Tue, 5 Jan 2021 10:21:55 +0000 (10:21 +0000)]
[Coroutines] checkAsyncFuncPointer - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.
We're immediately dereferencing the casted pointer, so use cast<> which will assert instead of dyn_cast<> which can return null.
Fixes static analyzer warning.
Jeremy Morse [Tue, 5 Jan 2021 10:21:17 +0000 (10:21 +0000)]
[DebugInfo] Avoid LSR crash on large integer inputs
Loop strength reduction tries to recover debug variable values by looking
for simple offsets from PHI values. In really extreme conditions there may
be an offset used that won't fit in an int64_t, hitting an APInt assertion.
This patch adds a regression test and adjusts the equivalent value
collecting code to filter out any values where the offset can't be
represented by an int64_t. This means that for very large integers with
very large offsets, the variable location will become undef, which is the
same behaviour as before
2a6782bb9f1 / D87494.
Differential Revision: https://reviews.llvm.org/D94016
Andy Wingo [Tue, 8 Dec 2020 12:55:19 +0000 (13:55 +0100)]
[WebAssembly] call_indirect causes indirect function table import
For wasm-ld table linking work to proceed, object files should indicate
if they use an indirect function table. In the future this will be done
by the usual symbols and relocations mechanism, but until that support
lands in the linker, the presence of an `__indirect_function_table` in
the object file's import section shows that the object file needs an
indirect function table.
Prior to https://reviews.llvm.org/D91637, this condition was met by all
object files residualizing an `__indirect_function_table` import.
Since https://reviews.llvm.org/D91637, the intention has been that only
those object files needing an indirect function table would have the
`__indirect_function_table` import. However, we missed the case of
object files which use the table via `call_indirect` but which
themselves do not declare any indirect functions.
This changeset makes it so that when we lower a call to `call_indirect`,
that we ensure that a `__indirect_function_table` symbol is present and
that it will be propagated to the linker.
A followup patch will revise this mechanism to make an explicit link
between `call_indirect` and its associated indirect function table; see
https://reviews.llvm.org/D90948.
Differential Revision: https://reviews.llvm.org/D92840
Kazushi (Jam) Marukawa [Tue, 5 Jan 2021 09:54:05 +0000 (18:54 +0900)]
[VE][NFC] Fix typo in comments
Vassil Vassilev [Tue, 5 Jan 2021 08:11:33 +0000 (08:11 +0000)]
Inform the consumer on invalid template instantiations.
Some clients which want to track state need the information whether a template
was instantiated and made invalid.
Differential revision: https://reviews.llvm.org/D92248
Simon Pilgrim [Mon, 4 Jan 2021 18:53:43 +0000 (18:53 +0000)]
MemProfiler::insertDynamicShadowAtFunctionEntry - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.
We're immediately dereferencing the casted pointer, so use cast<> which will assert instead of dyn_cast<> which can return null.
Fixes static analyzer warning.
Simon Pilgrim [Mon, 4 Jan 2021 18:53:04 +0000 (18:53 +0000)]
SystemZTargetLowering::lowerDYNAMIC_STACKALLOC - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.
We're immediately dereferencing the casted pointer, so use cast<> which will assert instead of dyn_cast<> which can return null.
Fixes static analyzer warning.
Simon Pilgrim [Mon, 4 Jan 2021 18:51:22 +0000 (18:51 +0000)]
Sema::BuildCallExpr - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.
We're immediately dereferencing the casted pointer, so use cast<> which will assert instead of dyn_cast<> which can return null.
Fixes static analyzer warning.
Fraser Cormack [Thu, 24 Dec 2020 13:29:15 +0000 (13:29 +0000)]
[RISCV] Add vector integer min/max ISel patterns
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D94012
Kazushi (Jam) Marukawa [Tue, 15 Dec 2020 12:50:17 +0000 (21:50 +0900)]
[VE] Support llvm.eh.sjlj.lsda
In order to support SJLJ exception, implement llvm.eh.sjlj.lsda first.
Add regression test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93811
Gabriel Hjort Åkerlund [Tue, 5 Jan 2021 08:12:58 +0000 (09:12 +0100)]
[GlobalISel][TableGen] Fix ConstrainOperandRC bug
TableGen would pick the largest RC for constraining the operands, which
could potentially be an unallocatable RC. This patch removes selection
of unallocatable RCs.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D93945
Martin Storsjö [Fri, 20 Nov 2020 09:32:01 +0000 (11:32 +0200)]
[compiler-rt] [windows] Add UNUSED attributes on variables/functions only used for 64 bit targets
This fixes warnings when building for 32 bit targets.
Differential Revision: https://reviews.llvm.org/D91852
Med Ismail Bennani [Tue, 5 Jan 2021 03:49:58 +0000 (04:49 +0100)]
[llvm/Orc] Fix ExecutionEngine module build breakage
This patch updates the llvm module map to reflect changes made in
`
5efc71e119d4eba235209d262e7d171361a0b9be` and fixes the module builds
(`-DLLVM_ENABLE_MODULES=On`).
Differential Revision: https://reviews.llvm.org/D94057
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Xun Li [Tue, 5 Jan 2021 04:21:01 +0000 (20:21 -0800)]
Remove RefSCC::handleTrivialEdgeInsertion
This function no longer does anything useful. It probably did something originally but latter changes removed them and didn't clean up this function.
The checks are already done in the callers as well.
Differential Revision: https://reviews.llvm.org/D94055
Qiu Chaofan [Tue, 5 Jan 2021 03:32:16 +0000 (11:32 +0800)]
[NFC] [PowerPC] Remove dead code in BUILD_VECTOR peephole
The piece of code tries to use splat+shift to lower build_vector with
repeating bit pattern. And immediate field of vector splat is only 5
bits (-16~15). It iterates over them one by one to find which
shifts/rotates to number in build_vector.
This patch removes code to try matching constant with algebraic
right-shift because that's meaningless - any negative number's algebraic
right-shift won't produce result smaller than itself. Besides, code
(int)((unsigned)i >> j) means logical shift-right in C.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D93937
Qiu Chaofan [Tue, 5 Jan 2021 03:25:18 +0000 (11:25 +0800)]
[NFC] [PowerPC] Update vec_constants test to reflect more patterns
This patch uses update_llc_check script to update vec_constants.ll, and
add two cases to cover 'vsplti+vsldoi' with 16-bit and 24-bit offset.
QingShan Zhang [Tue, 5 Jan 2021 03:22:45 +0000 (03:22 +0000)]
[NFC] Add the getSizeInBytes() interface for MachineConstantPoolValue
Current implementation assumes that, each MachineConstantPoolValue takes
up sizeof(MachineConstantPoolValue::Ty) bytes. For PowerPC, we want to
lump all the constants with the same type as one MachineConstantPoolValue
to save the cost that calculate the TOC entry for each const. So, we need
to extend the MachineConstantPoolValue that break this assumption.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D89108
Evandro Menezes [Thu, 31 Dec 2020 09:55:19 +0000 (03:55 -0600)]
[RISCV] Rename RVV intrinsics class (NFC)
Rename the class `RISCVUnaryAAMask` to `RISCVBinaryAAAMask`, since it has two input arguments.
Qiu Chaofan [Tue, 5 Jan 2021 02:21:31 +0000 (10:21 +0800)]
[UpdateTestChecks] Fix PowerPC RE to support AIX assembly
Current update_llc_test_checks.py cannot generate checks for AIX
(powerpc64-ibm-aix-xcoff) properly. Assembly generated is little bit
different from Linux. So I use begin function comment here to capture
function name.
Reviewed By: MaskRay, steven.zhang
Differential Revision: https://reviews.llvm.org/D93676
Juneyoung Lee [Tue, 5 Jan 2021 01:58:49 +0000 (10:58 +0900)]
[InstSimplify] gep with poison operand is poison
This is a tiny update to fold gep poison into poison. :)
Alive2 proofs:
https://alive2.llvm.org/ce/z/7Nwdri
https://alive2.llvm.org/ce/z/sDP4sC
Juneyoung Lee [Tue, 5 Jan 2021 02:03:11 +0000 (11:03 +0900)]
[InstSimplify] add a test for gep with poison operand (NFC)
Heejin Ahn [Thu, 3 Dec 2020 03:55:14 +0000 (19:55 -0800)]
[WebAssembly] Remove old SDT_WebAssemblyCalls (NFC)
These are not used anymore.
Reviewed By: tlively
Differential Revision: https://reviews.llvm.org/D94036
Arthur Eubanks [Mon, 4 Jan 2021 21:04:09 +0000 (13:04 -0800)]
[JumpThreading][NewPM] Skip when target has divergent CF
Matches the legacy pass.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D94028
Roman Lebedev [Mon, 4 Jan 2021 21:59:45 +0000 (00:59 +0300)]
[SimplifyCFG] SimplifyCondBranchToTwoReturns(): switch to non-permissive DomTree updates
... which requires not deleting an edge that just got deleted,
because we could be dealing with a block that didn't go through
ConstantFoldTerminator() yet, and thus has a degenerate cond br
with matching true/false destinations.
Roman Lebedev [Mon, 4 Jan 2021 21:06:38 +0000 (00:06 +0300)]
[SimplifyCFG] SimplifyEqualityComparisonWithOnlyPredecessor(): switch to non-permissive DomTree updates
... which requires not deleting an edge that just got deleted.
Roman Lebedev [Mon, 4 Jan 2021 20:13:07 +0000 (23:13 +0300)]
[SimplifyCFG] simplifyIndirectBr(): switch to non-permissive DomTree updates
... which requires not deleting an edge that just got deleted.
Roman Lebedev [Mon, 4 Jan 2021 18:38:03 +0000 (21:38 +0300)]
[SimplifyCFGPass] mergeEmptyReturnBlocks(): switch to non-permissive DomTree updates
... which requires not inserting an edge that already exists.
Roman Lebedev [Mon, 4 Jan 2021 13:59:45 +0000 (16:59 +0300)]
[NFCI] SimplifyCFG: switch to non-permissive DomTree updates, where possible
Notably, this doesn't switch *every* case, remaining cases
don't actually pass sanity checks in non-permissve mode,
and therefore require further analysis.
Note that SimplifyCFG still defaults to not preserving DomTree by default,
so this is effectively a NFC change.
Roman Lebedev [Mon, 4 Jan 2021 13:42:13 +0000 (16:42 +0300)]
[NFCI] DwarfEHPrepare: update DomTree in non-permissive mode, when present
Being stricter will catch issues that would be just papered over
in permissive mode, and is likely faster.
Petr Hosek [Mon, 4 Jan 2021 22:24:46 +0000 (14:24 -0800)]
[clang] - Also look for devtoolset-10
devtoolset-10 has just been released so look for it as well.
Patch By: stephan.dollberg
Differential Revision: https://reviews.llvm.org/D92792
Thorsten Schütt [Mon, 4 Jan 2021 22:17:45 +0000 (23:17 +0100)]
Revert "[NFC, Refactor] Modernize StorageClass from Specifiers.h to a scoped enum (II)"
This reverts commit
efc82c4ad2bcb256a4f4c20238d08cd3afba4d2d.
Sanjay Patel [Mon, 4 Jan 2021 21:51:36 +0000 (16:51 -0500)]
[LoopUtils] remove redundant opcode parameter; NFC
While here, rename the inaccurate getRecurrenceBinOp()
because that was also used to get CmpInst opcodes.
The recurrence/reduction kind should always refer to the
expected opcode for a reduction. SLP appears to be the
only direct caller of createSimpleTargetReduction(), and
that calling code ideally should not be carrying around
both an opcode and a reduction kind.
This should allow us to generalize reduction matching to
use intrinsics instead of only binops.
Thorsten Schütt [Wed, 23 Dec 2020 15:56:00 +0000 (16:56 +0100)]
[NFC, Refactor] Modernize StorageClass from Specifiers.h to a scoped enum (II)
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D93765
Juneyoung Lee [Mon, 4 Jan 2021 21:49:19 +0000 (06:49 +0900)]
[ValueTracking] isGuaranteedNotToBePoison should return true on undef
This is a one-line fix to isGuaranteedNotToBePoison to return true if
undef is given.
Arthur Eubanks [Mon, 4 Jan 2021 21:47:07 +0000 (13:47 -0800)]
[NewPM][AMDGPU] Pass TargetMachine to AMDGPUSimplifyLibCallsPass
Missed in https://reviews.llvm.org/D93863.
Arthur Eubanks [Mon, 4 Jan 2021 21:08:32 +0000 (13:08 -0800)]
[test] Pin backedge-id-bug-xfail.ll to legacy PM
The new PM doesn't have region passes, so this doesn't really make sense in a NPM context.
Sanjay Patel [Mon, 4 Jan 2021 20:24:36 +0000 (15:24 -0500)]
[LoopUtils] reduce code for creatng reduction; NFC
We can return from each case instead creating a temporary
variable just to have a common return.
Sanjay Patel [Mon, 4 Jan 2021 20:10:03 +0000 (15:10 -0500)]
[LoopUtils] reorder logic for creating reduction; NFC
If we are using a shuffle reduction, we don't need to
go through the switch on opcode - return early.
Cameron McInally [Mon, 4 Jan 2021 20:13:14 +0000 (14:13 -0600)]
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
This patch disables the FSUB(-0,X)->FNEG(X) DAG combine when we're flushing subnormals. It requires updating the existing AMDGPU tests to use the fneg IR instruction, in place of the old fsub(-0,X) canonical form, since AMDGPU is the only backend currently checking the DenormalMode flags.
Note that this will require follow-up optimizations to make sure the FSUB(-0,X) form is handled appropriately
Differential Revision: https://reviews.llvm.org/D93243
Whitney Tsang [Mon, 4 Jan 2021 20:41:53 +0000 (20:41 +0000)]
Revert "[LoopNest] Allow empty basic blocks without loops"
This reverts commit
9a17bff4f715a9f3ec89f4eacae8fdea1b74fe79.
Arthur Eubanks [Tue, 29 Dec 2020 20:30:25 +0000 (12:30 -0800)]
[NewPM][AMDGPU] Make amdgpu-aa work with NewPM
An AMDGPUAA class already existed that was supposed to work with the new
PM, but it wasn't tested and was a bit broken.
Fix up the existing classes to have the right keys/parameters.
Wire up AMDGPUAA inside AMDGPUTargetMachine.
Add it to the list of alias analyses for the "default" AAManager since
in adjustPassManager() amdgpu-aa is added into the pipeline at the
beginning.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D93914
Arthur Eubanks [Sun, 3 Jan 2021 05:55:55 +0000 (21:55 -0800)]
[NewPM][AMDGPU] Port amdgpu-always-inline
And add to AMDGPU opt pipeline.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D94025
Arthur Eubanks [Sun, 3 Jan 2021 06:05:23 +0000 (22:05 -0800)]
[NewPM][AMDGPU] Port amdgpu-printf-runtime-binding
And add to AMDGPU opt pipeline.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D94026
Craig Topper [Mon, 4 Jan 2021 20:20:18 +0000 (12:20 -0800)]
[RISCV] Remove unused method RISCVInstPrinter::printSImm5Plus1. NFC
simm5_plus1 is only used by InstAliases so should never be printed.
Valentin Clement [Mon, 4 Jan 2021 20:18:46 +0000 (15:18 -0500)]
[flang][openmp] Make Reduction clause part of OmpClause
After discussion in D93105 we found that the reduction clause was not following
the common OmpClause convention. This patch makes reduction clause part of OmpClause
with a value of OmpReductionClause in a similar way than task_reduction.
The unparse function for OmpReductionClause is adapted since the keyword and parenthesis
are issued by the corresponding unparse function for parser::OmpClause::Reduction.
Reviewed By: sameeranjoshi
Differential Revision: https://reviews.llvm.org/D93482
Hongtao Yu [Mon, 4 Jan 2021 18:15:59 +0000 (10:15 -0800)]
Switching Clang UniqueInternalLinkageNamesPass scheduling to using the LLVM one with newpm.
As a follow-up to D93656, I'm switching the Clang UniqueInternalLinkageNamesPass scheduling to using the LLVM one with newpm.
Test Plan:
Reviewed By: aeubanks, tmsriram
Differential Revision: https://reviews.llvm.org/D94019
Whitney Tsang [Mon, 4 Jan 2021 19:57:44 +0000 (19:57 +0000)]
[LoopNest] Allow empty basic blocks without loops
Allow loop nests with empty basic blocks without loops in different
levels as perfect.
Reviewers: Meinersbur
Differential Revision: https://reviews.llvm.org/D93665
Arthur Eubanks [Sun, 3 Jan 2021 06:05:23 +0000 (22:05 -0800)]
[NewPM][AMDGPU] Port amdgpu-unify-metadata
And add to AMDGPU opt pipeline.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D94023
Arthur Eubanks [Tue, 29 Dec 2020 18:25:26 +0000 (10:25 -0800)]
[NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late
And add to AMDGPU opt pipeline.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D94022
Kazu Hirata [Mon, 4 Jan 2021 19:42:47 +0000 (11:42 -0800)]
[llvm] Use llvm::any_of (NFC)
Kazu Hirata [Mon, 4 Jan 2021 19:42:45 +0000 (11:42 -0800)]
[DebugInfo] Use llvm::append_range (NFC)
Kazu Hirata [Mon, 4 Jan 2021 19:42:43 +0000 (11:42 -0800)]
[llvm] Construct SmallVector with iterator ranges (NFC)
Arthur Eubanks [Tue, 29 Dec 2020 04:32:58 +0000 (20:32 -0800)]
[NewPM][AMDGPU] Run InternalizePass when -amdgpu-internalize-symbols
The legacy PM doesn't run EP_ModuleOptimizerEarly on -O0, so skip
running it here when given O0.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D93886
Craig Topper [Mon, 4 Jan 2021 18:23:40 +0000 (10:23 -0800)]
[RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) isel patterns.
With the i32 these patterns will only fire on RV32, but they
don't look RV32 specific.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D93843
Sanjay Patel [Mon, 4 Jan 2021 15:57:48 +0000 (10:57 -0500)]
[InstCombine] add tests for ashr+icmp; NFC
Matt Arsenault [Tue, 22 Dec 2020 22:45:34 +0000 (17:45 -0500)]
CodeGen: Use Register
Philip Reames [Mon, 4 Jan 2021 17:50:47 +0000 (09:50 -0800)]
Revert "[LoopDeletion] Break backedge of loops when known not taken"
This reverts commit
dd6bb367d19e3bf18353e40de54d35480999a930.
Multi-stage builders are showing an assertion failure w/LCSSA not being preserved on entry to IndVars. Reason isn't clear, reverting while investigating.
Philip Reames [Mon, 4 Jan 2021 17:19:29 +0000 (09:19 -0800)]
[LoopDeletion] Break backedge of loops when known not taken
The basic idea is that if SCEV can prove the backedge isn't taken, we can go ahead and get rid of the backedge (and thus the loop) while leaving the rest of the control in place. This nicely handles cases with dispatch between multiple exits and internal side effects.
Differential Revision: https://reviews.llvm.org/D93906
Joseph Huber [Fri, 18 Dec 2020 20:14:44 +0000 (15:14 -0500)]
[OpenMP] Add using bit flags to select Libomptarget Information
Summary:
This patch adds more fine-grained support over which information is output from the libomptarget runtime when run with the environment variable LIBOMPTARGET_INFO set. An extensible set of flags can be used to pick and choose which information the user is interested in.
Reviewers: jdoerfert JonChesterfield grokos
Differential Revision: https://reviews.llvm.org/D93727
Simon Pilgrim [Mon, 4 Jan 2021 16:39:07 +0000 (16:39 +0000)]
[ProfileData] GCOVFile::readGCNO - silence undefined pointer warning. NFCI.
Silence clang static analyzer warning that 'fn' could still be in an undefined state - this shouldn't happen depending on the likely tag order, but the analyzer can't know that.
Jon Chesterfield [Mon, 4 Jan 2021 16:48:46 +0000 (16:48 +0000)]
[libomptarget][amdgpu] Call into deviceRTL instead of ockl
[libomptarget][amdgpu] Call into deviceRTL instead of ockl
Amdgpu codegen presently emits a call into ockl. The same functionality
is already present in the deviceRTL. Adds an amdgpu specific entry point
to avoid the dependency. This lets simple openmp code (specifically, that
which doesn't use libm) run without rocm device libraries installed.
Reviewed By: ronlieb
Differential Revision: https://reviews.llvm.org/D93356
Krzysztof Parzyszek [Mon, 4 Jan 2021 16:34:17 +0000 (10:34 -0600)]
[Hexagon] Fix bad SDNodeXForm
Fixes https://llvm.org/PR48651
Florian Hahn [Mon, 4 Jan 2021 16:26:58 +0000 (16:26 +0000)]
[SimplifyCFG] Enabled hoisting late in LTO pipeline.
bb7d3af1139c disabled hoisting in SimplifyCFG by default, but enabled it
late in the pipeline. But it appears as if the LTO pipelines got missed.
This patch adjusts the LTO pipelines to also enable hoisting in the
later stages.
Unfortunately there's no easy way to add a test for the change I think.
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D93684
Michael Munday [Mon, 4 Jan 2021 16:00:38 +0000 (16:00 +0000)]
[RISCV][NFC] Add additional cmov tests
One or more cmov instructions could be generated for these functions
when the Zbt extension is present.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D93768
Florian Hahn [Mon, 4 Jan 2021 15:49:47 +0000 (15:49 +0000)]
[InterleavedAccess] Return correct 'modified' status.
Both tryReplaceExtracts and replaceBinOpShuffles may modify the IR, even
if no interleaved loads are generated, but currently the pass pretends
no changes were made.
This patch updates the pass to return true if either of the functions
made any changes. In case of tryReplaceExtracts, changes are made if
there are any Extracts and true is returned.
`replaceBinOpShuffles` always makes changes if BinOpShuffles is not empty.
It also always returned true, so I went ahead and change it to just
`replaceBinOpShuffles`.
Fixes PR48208.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D93997
Simon Pilgrim [Mon, 4 Jan 2021 15:30:15 +0000 (15:30 +0000)]
[IR] CallBase::getBundleOpInfoForOperand - ensure Current iterator is defined. NFCI.
Fix clang static analyzer undefined pointer warning in the case Begin == End.
Simon Pilgrim [Mon, 4 Jan 2021 15:12:55 +0000 (15:12 +0000)]
DeclCXX - Fix getAs<> null-dereference static analyzer warnings. NFCI.
getAs<> can return null if the cast is invalid, which can lead to null pointer deferences. Use castAs<> instead which will assert that the cast is valid.
Hansang Bae [Fri, 18 Dec 2020 00:43:36 +0000 (18:43 -0600)]
[OpenMP] Add definition/interface for target memory routines
The change includes new routines introduced in 5.1 and Fortran
interface.
Differential Revision: https://reviews.llvm.org/D93505
Simon Pilgrim [Mon, 4 Jan 2021 14:08:09 +0000 (14:08 +0000)]
[Sparc] SparcMCExpr::printVariantKind - fix Wcovered-switch-default gcc warning. NFCI.
Caroline Concatto [Thu, 17 Dec 2020 16:15:28 +0000 (16:15 +0000)]
[AArch64][SVE]Add cost model for masked gather and scatter for scalable vector.
A new TTI interface has been added 'Optional <unsigned>getMaxVScale' that
returns the maximum vscale for a given target.
When known getMaxVScale is used to compute the cost of masked gather scatter
for scalable vector.
Depends on D92094
Differential Revision: https://reviews.llvm.org/D93030
Florian Hahn [Mon, 4 Jan 2021 13:28:44 +0000 (13:28 +0000)]
[AArch64] Add patterns for FMCLA*_indexed.
This patch adds patterns for the indexed variants of FCMLA. Mostly based
on a patch by Tim Northover.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D92947
Simon Pilgrim [Mon, 4 Jan 2021 12:18:59 +0000 (12:18 +0000)]
[Support] Add KnownBits::icmp helpers.
Check if all possible values for a pair of knownbits give the same icmp result - these are based off the checks performed in InstCombineCompares.cpp and D86578.
Add exhaustive unit test coverage - a followup will update InstCombineCompares.cpp to use this.
David Green [Mon, 4 Jan 2021 12:44:43 +0000 (12:44 +0000)]
[ARM] Extend lowering for i64 reductions
The lowering of a <4 x i16> or <4 x i8> vecreduce.add into an i64 would
previously be expanded, due to the i64 not being legal. This patch
adjusts our reduction matchers, making it produce a VADDLV(sext A to
v4i32) instead.
Differential Revision: https://reviews.llvm.org/D93622
LemonBoy [Mon, 4 Jan 2021 08:41:58 +0000 (09:41 +0100)]
[Sparc] Fixes for the internal assembler
* Prevent the generation of invalid shift instructions by constraining
the immediate field. I've limited the shift field to constant values
only, adding the `R_SPARC_5`/`R_SPARC_6` relocations is trivial if
needed (but I can't really think of a use case for those).
* Fix the generation of PC-relative `call`
* Fix the transformation of `jmp sym` into `jmpl`
* Emit fixups for simm13 operands
I moved the choice of the correct relocation into the code emitter as I've
seen the other backends do, it can be definitely cleaner but the aim was
to reduce the scope of the patch as much as possible.
Fixes the problems raised by joerg in L254199
Reviewed By: dcederman
Differential Revision: https://reviews.llvm.org/D78193
Chih-Ping Chen [Fri, 18 Dec 2020 21:12:57 +0000 (16:12 -0500)]
[docs] Release notes for IsDecl in DIModule.
Please see https://reviews.llvm.org/D93462 for the actual code change.
Differential Revision: https://reviews.llvm.org/D93558
David Green [Mon, 4 Jan 2021 11:29:18 +0000 (11:29 +0000)]
[AArch64] Attempt to fix Mac tests with a more specific triple. NFC
Kazushi (Jam) Marukawa [Sun, 27 Dec 2020 14:28:20 +0000 (23:28 +0900)]
[VE] Change default CPU name to "generic"
Change default CPU name of SX-Aurora VE from "ve" to "generic" similar
to other architectures.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93836
Usman Nadeem [Mon, 4 Jan 2021 10:58:43 +0000 (10:58 +0000)]
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
The old CPU model only had MLA->MLA forwarding. I added some missing
MUL->MLA read advances and a missing absolute diff accumulator read
advance according to the Cortex A57 Software Optimization Guide.
The patch improves performance in EEMBC rgbyiqv2 by about 6%-7% and
spec2006/milc by 8% (repeated runs on multiple devices), causes no
significant regressions (none in SPEC).
Differential Revision: https://reviews.llvm.org/D92296