Simon Glass [Wed, 16 Mar 2016 13:44:36 +0000 (07:44 -0600)]
x86: Move common PCH code into a common place
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 16 Mar 2016 13:44:35 +0000 (07:44 -0600)]
dhry: Correct dhrystone calculation for fast machines
At present samus reports about 5600 DMIPS. With the default iteration count
this is OK, but if 10 million runs are performed it overflows. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 16 Mar 2016 13:44:34 +0000 (07:44 -0600)]
arm: Add a 64-bit division routine to the private library
This is missing, with causes lldiv() to fail on boards with use the private
libgcc. Add the missing routine.
Code is available for using the CLZ instruction but it is not enabled at
present.
This comes from coreboot version 4.0.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 12 Mar 2016 05:07:35 +0000 (22:07 -0700)]
x86: Fix a header nit in x86-chromebook.h
There is an extra line in the comment in the header. Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:34 +0000 (22:07 -0700)]
x86: Add a function to set the IOAPIC ID
Add a function to set the ID in the IOAPIC.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:33 +0000 (22:07 -0700)]
x86: Update README for new developments
Update a few points which have become out-of-date.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:32 +0000 (22:07 -0700)]
x86: Use white on black for the console on chromebooks
This is a little easier on the eyes, particularly when the backlight is set
to maximum.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:31 +0000 (22:07 -0700)]
x86: Add a default address for reference code
Add an address which can be used for loading and running the reference code
when needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:30 +0000 (22:07 -0700)]
x86: broadwell: Add video support
Add a video driver for Intel's broadwell integrated graphics controller.
This uses a binary blob for most init, with the driver just performing a few
basic tasks.
This driver supports VESA as the mode-setting mechanism. Since most boards
don't support driver model yet with VESA, a special case is added to the
Kconfig for broadwell. Eventually all boards will use driver model and this
can be removed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:28 +0000 (22:07 -0700)]
x86: broadwell: Add support for high-speed I/O lane with ME
Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:27 +0000 (22:07 -0700)]
x86: broadwell: Add a GPIO driver
Add a GPIO driver for the GPIO peripheral found on broadwell devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:26 +0000 (22:07 -0700)]
x86: broadwell: Add support for SDRAM setup
Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:25 +0000 (22:07 -0700)]
x86: broadwell: Add power-control support
Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598373/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:24 +0000 (22:07 -0700)]
x86: broadwell: Add reference code support
Broadwell needs a special binary blob to set up the PCH. Add code to run
this on start-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:23 +0000 (22:07 -0700)]
x86: broadwell: Add an LPC driver
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:22 +0000 (22:07 -0700)]
x86: broadwell: Add a northbridge driver
Add a driver for the broadwell northbridge. This sets up the location of
several blocks of registers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:21 +0000 (22:07 -0700)]
x86: broadwell: Add a SATA driver
Add a SATA driver for broadwell. This supports connecting an SSD and the
usual U-Boot commands to read and write data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:20 +0000 (22:07 -0700)]
x86: broadwell: Add a pinctrl driver
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.
The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:19 +0000 (22:07 -0700)]
x86: broadwell: Add a PCH driver
Add a driver for the broadwell low-power platform controller hub.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:18 +0000 (22:07 -0700)]
x86: Add basic support for broadwell
This adds the broadwell architecture, with the CPU driver and some useful
header files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:17 +0000 (22:07 -0700)]
x86: dts: Update the pinctrl binding a little
Make a few minor updates to make the meaning clearer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:16 +0000 (22:07 -0700)]
x86: Add support for running Intel reference code
Intel has invented yet another binary blob which firmware is required to
run. This is run after SDRAM is ready. It is linked to load at a particular
address, typically 0, but is a relocatable ELF so can be moved if required.
Add support for this in the build system. The file should be placed in the
board directory, and called refcode.elf.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:15 +0000 (22:07 -0700)]
x86: Drop all the old pin configuration code
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:14 +0000 (22:07 -0700)]
x86: gpio: Allow the pinctrl driver to set up the pin config
Rather than setting up the pin configuration in the GPIO driver, use the
new pinctrl driver to do it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:13 +0000 (22:07 -0700)]
x86: Add an ICH6 pin configuration driver
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.
The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:
- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed
It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH
However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.
Also add an 'invert' property to support inverting the input.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:12 +0000 (22:07 -0700)]
x86: link: Add pin configuration to the device tree
At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.
Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:11 +0000 (22:07 -0700)]
x86: Update microcode for secondary CPUs
Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:10 +0000 (22:07 -0700)]
x86: ivybridge: Show microcode version for each core
Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:09 +0000 (22:07 -0700)]
x86: Record the CPU details when starting each core
As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:08 +0000 (22:07 -0700)]
x86: Move common MRC Kconfig options to the common file
At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:07 +0000 (22:07 -0700)]
x86: Allow I/O functions to use pointers
It is common with memory-mapped I/O to use the address of a structure member
to access memory, as in:
struct some_regs {
u32 ctrl;
u32 data;
}
struct some_regs *regs = (struct some_regs *)BASE_ADDRESS;
writel(1, ®->ctrl);
writel(2, ®->data);
This does not currently work with inl(), outl(), etc. Add a cast to permit
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:06 +0000 (22:07 -0700)]
x86: Add macros to clear and set I/O bits
The clrsetbits_...() macros are useful for working with memory mapped I/O.
But they do not work with I/O space, as used on x86 machines.
Add some macros to provide similar features for I/O.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:01 +0000 (22:07 -0700)]
x86: ivybridge: Drop sandybridge_early_init()
This function was removed in the previous clean-up. Drop it from the header
file also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:07:00 +0000 (22:07 -0700)]
x86: Move Intel Management Engine code to a common place
Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:59 +0000 (22:06 -0700)]
x86: Rename PORT_RESET to IO_PORT_RESET
This same name is used in USB. Add a prefix to distinguish it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:58 +0000 (22:06 -0700)]
x86: Move common CPU code to its own place
Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:57 +0000 (22:06 -0700)]
x86: Move common LPC code to its own place
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:56 +0000 (22:06 -0700)]
x86: Add the root-complex block to common intel registers
This is similar to MCH in that it is used in various drivers. Add it to
the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:55 +0000 (22:06 -0700)]
x86: Create a common header for Intel register access
There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.
An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).
Add a new header file for these registers, and move MCH into it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:54 +0000 (22:06 -0700)]
x86: Move microcode code to a common location
This code is used on several Intel CPUs. Move it into a common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:53 +0000 (22:06 -0700)]
x86: Move cache-as-RAM code into a common location
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:52 +0000 (22:06 -0700)]
x86: cpu: Add functions to return the family and stepping
These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:51 +0000 (22:06 -0700)]
x86: Allow use of serial soon after relocation
At present on x86 machines with use cache-as-RAM, the memory goes away just
before board_init_r() is called. This means that serial drivers are
no-longer unavailable, until initr_dm() it called, etc.
Any attempt to use printf() within this period will cause a hang.
To fix this, mark the serial devices as 'unavailable' when it is no-longer
available. Bring it back when serial_initialize() is called. This means that
the debug UART will be used instead for this period.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:50 +0000 (22:06 -0700)]
input: i8042: Make sure the keyboard is enabled
Add one more step into the init sequence. This fixes the keyboard on samus,
which otherwise does not work.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:49 +0000 (22:06 -0700)]
syscon: Avoid returning a device on failure
If the device cannot be probed, syscon_get_by_driver_data() will still
return a useful value in its devp parameter. Ensure that it returns NULL
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 12 Mar 2016 05:06:46 +0000 (22:06 -0700)]
dm: timer: Correct timer init ordering after relocation
Commit 1057e6c broke use of the timer with driver model. If the timer is used
before relocation, then it becomes broken after relocation. This prevents
some x86 boards from booting. Fix it.
Fixes: 1057e6c (timer: Set up the real timer after driver model is available)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:34 +0000 (19:28 -0700)]
x86: broadwell: Add a few microcode files
Add two microcode files for broadwell.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:25 +0000 (19:28 -0700)]
x86: Add comments to the SIPI vector
The Intel SIPI (start-up inter-processor interrupt) vector is the entry
point for each secondary CPU (also called an AP - applications processor).
The assembler and C code are linked, so add comments to indicate this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:22 +0000 (19:28 -0700)]
x86: Tidy up mp_init to reduce duplication
The timeout step is always 50us. By updating apic_wait_timeout() to print
the debug messages we can simplify the code. Also tidy up a few messages and
comments while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:18 +0000 (19:28 -0700)]
x86: Correct duplicate POST values
Two power-on-self-test values are the same. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:17 +0000 (19:28 -0700)]
x86: Add a script to aid code conversion from coreboot
It is useful to automate the process of converting code from coreboot a
little. Add a sed script which performs some common transformations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:13 +0000 (19:28 -0700)]
x86: gpio: Correct GPIO setup ordering
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.
Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:12 +0000 (19:28 -0700)]
x86: dts: link: Add board ID GPIOs
At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:11 +0000 (19:28 -0700)]
x86: dts: link: Move SPD info into the memory controller
The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.
As a first step, move the information.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:10 +0000 (19:28 -0700)]
x86: link: Add required GPIO properties
In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:28:04 +0000 (19:28 -0700)]
x86: Add some more common MSR indexes
Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:27:57 +0000 (19:27 -0700)]
x86: cpu: Make the vendor table const
This does not need to be modified at run-time, so make it const.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:27:55 +0000 (19:27 -0700)]
malloc_simple: Add a little more debugging
Output the pointer returned by each call to malloc(). This can be useful
when debugging memory problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:27:53 +0000 (19:27 -0700)]
pci: Correct a few comments and nits
Two comments are missing a parameter and there is an extra blank line. Also
two of the region access macros are misnamed. Correct these problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:27:52 +0000 (19:27 -0700)]
pci: Add functions to update PCI configuration registers
It is common to read a config register value, clear and set some bits, then
write back the updated value. Add functions to do this in one step, for
convenience.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:27:51 +0000 (19:27 -0700)]
gpio: Use const where possible
Some functions do not change the struct gpio_desc parameter. Update these to
use const so this is clear.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:27:50 +0000 (19:27 -0700)]
gpio: Add a function to obtain a GPIO vector value
We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO
is assigned a single bit and can be set high or low on the circuit board. We
already have a legacy function for reading these values. Add one that
supports driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:27:49 +0000 (19:27 -0700)]
cpu: Add support for microcode version and CPU ID
Some CPUs use microcode and each core can have a different version of
microcode loaded. Also some CPUs support the concept of an integer ID used
for identification purposes. Add support for these in the CPU uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 7 Mar 2016 02:27:48 +0000 (19:27 -0700)]
video: Allow simple-panel to be used without regulators
At present simple-panel requires regulator support and will not build
without it. But some panels do not have a power supply, or at least not one
that can be controlled. Update the implementation to cope with this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Bin Meng [Mon, 29 Feb 2016 07:54:52 +0000 (23:54 -0800)]
x86: Document how to play with SeaBIOS
Boting SeaBIOS is done via U-Boot's bootelf command. Document this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 29 Feb 2016 07:54:51 +0000 (23:54 -0800)]
x86: qemu: Enable ACPI table generation by default
Now that ACPI is supported on QEMU, enable it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 29 Feb 2016 07:54:50 +0000 (23:54 -0800)]
x86: Support booting SeaBIOS
SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
It can run in an emulator or natively on x86 hardware with the
use of coreboot. With SeaBIOS's help, we can boot some OSes
that require 16-bit BIOS services like Windows/DOS.
As U-Boot, we have to manually create a table where SeaBIOS gets
system information (eg: E820) from. The table unfortunately has
to follow the coreboot table format as SeaBIOS currently supports
booting as a coreboot payload.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 28 Feb 2016 06:58:03 +0000 (22:58 -0800)]
x86: Implement functions for writing coreboot table
To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 28 Feb 2016 06:58:02 +0000 (22:58 -0800)]
x86: Support writing configuration tables in high area
For those secondary bootloaders like SeaBIOS who want to live in
the F segment, which conflicts the configuration table address,
now we allow write_tables() to write the configuration tables in
high area (malloc'ed memory).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 28 Feb 2016 06:58:01 +0000 (22:58 -0800)]
x86: Simplify codes in write_tables()
Given all table write routines have the same signature, we can
simplify the codes by using a function table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 28 Feb 2016 06:58:00 +0000 (22:58 -0800)]
x86: Change write_acpi_tables() signature a little bit
Change the parameter and return value of write_acpi_tables() to u32
to conform with other table write routines.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 28 Feb 2016 06:57:59 +0000 (22:57 -0800)]
x86: Use a macro for ROM table alignment
Define ROM_TABLE_ALIGN instead of using 1024 directly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 28 Feb 2016 06:57:58 +0000 (22:57 -0800)]
x86: Change to use start/end address pair in write_tables()
Add a new variable rom_table_start and pass it to ROM table write
routines. This reads better than previous single rom_table_end.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 28 Feb 2016 06:57:57 +0000 (22:57 -0800)]
x86: Clean up coreboot_tables.h
Clean up this file a little bit:
- Remove inclusion of <linux/compiler.h>
- Use tab in the macro definition
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 28 Feb 2016 06:57:56 +0000 (22:57 -0800)]
x86: Move sysinfo related to sysinfo.h
coreboot_tables.h should not include sysinfo related stuff.
Move those to asm/arch-coreboot/sysinfo.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 28 Feb 2016 06:57:55 +0000 (22:57 -0800)]
x86: Move asm/arch-coreboot/tables.h to a common place
Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that
coreboot table definitions can be used by other x86 builds.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 15 Mar 2016 21:56:29 +0000 (17:56 -0400)]
spl: arm: Make sure to include all of the u_boot_list entries
Starting with 96e5b03 we use a linker list for partition table
information. However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well. While doing this, it's
best to simply include all linker lists to future proof ourselves.
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reported-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 16 Mar 2016 19:25:46 +0000 (15:25 -0400)]
mvebu: ds414: Move cmd_syno into ds414 directory
When we switch to including all linker lists in SPL it is important to
not include commands as that may lead to link errors due to other things
we have already discarded. In this case as we don't have other common
code nor other Synology borads, move the cmd_syno.c file (which claims
to be ds414 specific anyways!) into the ds414 directory and only build
it for non-SPL builds.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 16 Mar 2016 14:38:21 +0000 (10:38 -0400)]
arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX
On OMAP4 platforms that also need to calculate their DDR settings we are
now getting very close to the linker limit size. Since OMAP44XX is only
seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we
will know that we don't have it for OMAP44XX.
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 16 Mar 2016 13:56:55 +0000 (09:56 -0400)]
lpc32xx: work_92105: Rework Makefile
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case change things so that we
only build the right objects for SPL or non-SPL
Cc: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 16 Mar 2016 13:45:03 +0000 (09:45 -0400)]
cmd: scsi: Group the command portion together, guard with !CONFIG_SPL_BUILD
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case, the SCSI code needs a lot
of attention so for now just guard the command portions.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 16 Mar 2016 13:24:00 +0000 (09:24 -0400)]
ARM: keystone2: Only link cmd_ddr3.o on non-SPL builds
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case simply move cmd_ddr3.o
over to the list with the rest.
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 16 Mar 2016 13:19:43 +0000 (09:19 -0400)]
ARM: keystone2: Switch to using the poweroff command
Now that we have a standard way to power off the hardware, switch to
using that rather than our own command.
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 16 Mar 2016 13:10:08 +0000 (09:10 -0400)]
ARM: keystone2: Split monitor code / command code
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case, we split the code for
supporting the monitor out from the code for loading it.
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Andrew F. Davis [Fri, 11 Mar 2016 21:22:20 +0000 (15:22 -0600)]
ARM: DRA7xx: Enable NFS boot command
NFS loading works on DRA7 variants, remove the undefinition.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Andrew F. Davis [Fri, 11 Mar 2016 21:04:03 +0000 (15:04 -0600)]
ti_armv7_common: env: Add NFS loading support to default enviroment
NFS loading is similar to net loading except initial files are loaded
over NFS instead of TFTP, this removes the need for multiple different
protocol servers running on the host and allows the use of a single
network file system containing boot related files in their usual
in-filesystem directory. Add defaults for this boot style here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Masahiro Yamada [Mon, 29 Feb 2016 11:50:34 +0000 (20:50 +0900)]
spl_nor: fix warning when compiled for 64bit target
Fix "warning: cast to pointer from integer of different size".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Wed, 9 Mar 2016 12:09:56 +0000 (17:39 +0530)]
ARM: DRA7: DDR: Enable SR in Power Management Control
If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Yan Liu [Wed, 9 Mar 2016 10:09:39 +0000 (15:39 +0530)]
keystone2: env: Set mmc as default boot for k2g-evm
For k2l, k2e and k2hk, ubi is set to default boot in uboot
environment settings; while for k2g, mmc should be the
default boot. This patch is to set mmc as default for k2g-evm
Signed-off-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Murali Karicheri [Wed, 9 Mar 2016 10:09:38 +0000 (15:39 +0530)]
keystone2: env: add env script for booting with an initramfs with firmware
This patch updates the env script to include a initramfs with firmware
loaded and provided to kernel through second argument of bootz command
during boot. Defined DEFAULT_FW_INITRAMFS_BOOT_ENV to have all of the
required env variables and use it in evm specific config file.
The K2 linux drivers for PCIe and NetCP (1G, 10G) requires serdes
firmwares. These requires firmware to be available early through the boot
process in some cases to satisfy firmware requests from driver. Hence use
a small initramfs to provide the same and update boot env to accommodate
this in the boot flow. This method is used when rootfs is nfs and ubifs.
This fs contains just lib/firmware folder with all required firmware.
When rootfs is on initramfs, then the filesystem has the firmware under
lib/firmware and this early initramfs is not required and is not used.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 9 Mar 2016 10:09:37 +0000 (15:39 +0530)]
k2g: configs: Add support to save env in MMC
Adding support to save env in MMC on k2g platforms, as it is the
preferred peripheral in saving env.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 9 Mar 2016 10:09:36 +0000 (15:39 +0530)]
k2g: env: Allow use of a script and plain text env files
For development purposes, it is easier to use the env import command
and plain text or script files instead of script-images. So allow
u-boot to load env var from a text file or a script file.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 9 Mar 2016 10:09:35 +0000 (15:39 +0530)]
ti_armv7_common: env: Consolidate support for loading script and text env files
Support for loading bootscript and text env file is duplicated in all TI
platforms. Add this information to DEFAULT_MMC_TI_ARGS so that it can be
reused in all TI platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Wed, 9 Mar 2016 10:09:34 +0000 (15:39 +0530)]
am43xx: configs: Enable USB commands for non usb boot also
With commit
aee119bd70b8 ('am43xx_evm: add usb host boot support') usb
commands is removed from U-boot second stage and enbaled only on USB
boot config. Fixing this by enable USB commands for both USB boot and
in second stage u-boot.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 9 Mar 2016 10:09:33 +0000 (15:39 +0530)]
am335x: configs: Fix usb ether boot support
CONFIG_SPL_NET_VCI_STRING is available only with BOOTP. So if
CMD_DHCP is enabled for SPL in usb ether boot, it will not pass
the right vendor name and failing to download the right file.
Also all the net CMD_* are not required in SPL builds. So defining
these only for non-SPL builds.
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Carlos Hernandez [Wed, 9 Mar 2016 10:09:32 +0000 (15:39 +0530)]
ti_armv7_keystone2: env: Remove securedb.key.bin load
securedb.key.bin is not supported so it should not be loaded by
default init_ubi command.
Signed-off-by: Carlos Hernandez <ceh@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Carlos Hernandez [Wed, 9 Mar 2016 10:09:31 +0000 (15:39 +0530)]
ti_armv7_keystone2: env: Update UBIFS image paths
UBI images created by OE does not contain boot partition by default,
instead kernel and dtb are placed in /boot directory inside rootfs
partition. So update env commands to load files from correct
location.
Signed-off-by: Carlos Hernandez <ceh@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Wed, 9 Mar 2016 10:09:30 +0000 (15:39 +0530)]
ti_armv7_keystone2: configs: add usb mass storage support
Add USB mass storage support so that kernel can be read from
connected usb storage.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Alexander Graf [Fri, 4 Mar 2016 00:10:14 +0000 (01:10 +0100)]
efi_loader: Pass proper device path in on boot
EFI payloads can query for the device they were booted from. Because
we have a disconnect between loading binaries and running binaries,
we passed in a dummy device path so far.
Unfortunately that breaks grub2's logic to find its configuration
file from the same device it was booted from.
This patch adds logic to have the "load" command call into our efi
code to set the device path to the one we last loaded a binary from.
With this grub2 properly detects where we got booted from and can
find its configuration file, even when searching by-partition.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Fri, 4 Mar 2016 00:10:13 +0000 (01:10 +0100)]
efi_loader: Call fdt preparation functions
We have a nice framework around image fils to prepare a device tree
for OS execution. That one patches in missing device tree nodes and
fixes up the memory range bits.
We need to call that one from the EFI boot path too to get all those
nice fixups. This patch adds the call.
Signed-off-by: Alexander Graf <agraf@suse.de>