Christian Gmeiner [Fri, 11 Nov 2022 18:05:24 +0000 (19:05 +0100)]
etnaviv: Support negative float inline immediates
Closes: #7652
Fixes:
45a111c21c2 ("nir/opt_algebraic: Fuse c - a * b to FMA")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19776>
Lucas Stach [Tue, 22 Nov 2022 09:21:43 +0000 (10:21 +0100)]
etnaviv: fix NULL pointer dereference in TS allocation
Commit
c2b06e1a3820 ("etnaviv: add support for sharing the TS buffer")
introduced a problem similar to the one fixed in
3b3cd5128672 ("etnaviv:
fix renderonly check in etna_resource_alloc") in a different code path.
This causes a NULL pointer dereference when the screen is instanciated
on the render node. Fix it in the same way by just checking for a valid
pointer.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19923>
Lionel Landwerlin [Tue, 22 Nov 2022 10:22:06 +0000 (12:22 +0200)]
anv: enable sample location enable dynamic state
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19925>
Pedro J. Estébanez [Mon, 21 Nov 2022 11:56:37 +0000 (12:56 +0100)]
microsoft/nir_to_dxil: Avoid emitting SampleCmpLevel prior to SM 6.7 if possible
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19896>
Tomeu Vizoso [Tue, 22 Nov 2022 11:39:53 +0000 (12:39 +0100)]
rusticl: Emit build-id in libRusticlOpenCL
Drivers may need it for their on-disk shader caches.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19927>
Eric Engestrom [Mon, 21 Nov 2022 15:37:54 +0000 (15:37 +0000)]
v3d: make format/modifier logic easier to read
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19900>
Constantine Shablya [Sun, 20 Nov 2022 11:06:17 +0000 (13:06 +0200)]
nir: convert nir_opt_idiv_const to nir_shader_instructions_pass
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19881>
Lucas Stach [Wed, 16 Nov 2022 16:15:07 +0000 (17:15 +0100)]
etnaviv: remove use of flush_seqno as trigger for texture cache invalidate
The flush_seqno is only to be used/updated when a dirty tile status has
been written back to the resource. Using it as a marker to trigger a
texture cache invalidation is bogus and not actually needed. When the
texture resource is updated via a mapping or blit the texture cache
invalidation is already triggered by marking the caches as dirty. If the
resource is updated by fragment output, OpenGL explicitly defines the
result of a later texture read as undefined unless a TextureBarrier is
inserted, which also properly triggers the texture cache invalidate.
Also the current check is bogus as it doesn't handle seqno wraparound.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19800>
Lucas Stach [Wed, 16 Nov 2022 16:27:38 +0000 (17:27 +0100)]
etnaviv: mark texture caches as dirty when blitting into a sampler resource
Same as with resource mappings the blit can target a resource that may be
cached in the texture cache. Mark the cache as dirty to make sure it is
invalidated before the next draw.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19800>
Lucas Stach [Wed, 16 Nov 2022 15:24:54 +0000 (16:24 +0100)]
etnaviv: drop useless ts_for_sampler_view pointer check
Both state and desc texture implementations set this function pointer,
so there is no point in guarding against its absence.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19800>
Marek Olšák [Thu, 17 Nov 2022 13:31:33 +0000 (08:31 -0500)]
st/mesa: suppress async glthread flushing for GLX_EXT_texture_from_pixmap
This might fix some window system issues.
Fixes:
3da170faaec - glthread: change when glFlush flushes asynchronously
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19809>
Lionel Landwerlin [Sun, 20 Nov 2022 22:00:22 +0000 (00:00 +0200)]
util/glsl2spirv: don't store preprocessed files in source tree
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19893>
Danylo Piliaiev [Thu, 10 Nov 2022 14:40:48 +0000 (15:40 +0100)]
freedreno,tu,ir3: DCE ij_pix
SP_FS_PREFETCH_CNTL.IJ_WRITE_DISABLE allows disabling ij write, so
now we could DCE it.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19652>
Danylo Piliaiev [Thu, 10 Nov 2022 14:38:28 +0000 (15:38 +0100)]
freedreno,tu: Update SP_FS_PREFETCH,SP_FS_PREFETCH_CNTL regs definition
Reverse engineer more fields of these regs.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19652>
Marek Olšák [Fri, 18 Nov 2022 10:13:42 +0000 (05:13 -0500)]
mesa: add unlikely() and adjust error handling in BindBuffer
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19844>
Marek Olšák [Thu, 17 Nov 2022 17:02:16 +0000 (12:02 -0500)]
mesa: add no_error support into get_buffer_target()
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19844>
Marek Olšák [Thu, 17 Nov 2022 16:15:56 +0000 (11:15 -0500)]
mesa: remove ctx->Extensions.EXT_pixel_buffer_object capability flag
to get rid of the fail path in get_buffer_target.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19844>
Lucas Stach [Fri, 18 Nov 2022 11:24:58 +0000 (12:24 +0100)]
etnaviv: fix tile status interaction with write mappings
This fixes a longstanding bug in the interaction between TS and a write
mapping. The write does not update TS regardless of the way the update
is done. Update via etna_copy_resource would just set the target ts_valid
to false without actually writing back any dirty TS to the resource.
Writes via the CPU would update the resource, but keep ts_valid at true
even if the tile status may now not match the actually written tiles of
the resource anymore.
Fix this by writing back a dirty TS to the target resource if needed
before updating the level with the write data. Always invalidate TS,
even when the update is done by the CPU.
Cc: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19846>
Lionel Landwerlin [Tue, 22 Nov 2022 08:47:58 +0000 (10:47 +0200)]
anv: fixup context initialization on DG2
Fixing a typo :(
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
507a86e131d6 ("anv: ensure CPS is initialized when KHR_fragment_shading_rate is disabled")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19922>
Frank Binns [Thu, 17 Nov 2022 11:36:53 +0000 (11:36 +0000)]
CODEOWNERS: add MTCoster as an Imagination maintainer
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19845>
Yonggang Luo [Mon, 21 Nov 2022 11:01:50 +0000 (19:01 +0800)]
util: Remove EXPLICIT_CONVERSION macro and use c++11 explicit directly
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19895>
Yonggang Luo [Sun, 20 Nov 2022 04:50:41 +0000 (12:50 +0800)]
tree-wide: Fixes multi-line macro width after replace to __func__
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19861>
Yonggang Luo [Thu, 17 Nov 2022 21:40:21 +0000 (05:40 +0800)]
gallium: __FUNCTION__ now never be used, remove it
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19861>
Yonggang Luo [Thu, 17 Nov 2022 21:39:49 +0000 (05:39 +0800)]
gallium: Replace the usage of __FUNCTION__ with __func__ in all gallium code
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19861>
Yonggang Luo [Thu, 17 Nov 2022 21:38:36 +0000 (05:38 +0800)]
tree-wide: Use __func__ instead of __FUNCTION__ in non-gallium code
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19861>
Danylo Piliaiev [Tue, 1 Nov 2022 16:42:08 +0000 (17:42 +0100)]
meson: do not use source_root() when possible
source_root() function is deprecated in Meson version 0.56.0 because
it returns the source root of the parent project if called from a
subproject.
Why would anyone need Mesa as a meson subproject?
It would be used as subproject in a project generated by command buffer
"decompiler" for Freedreno.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19901>
Qiang Yu [Sat, 19 Nov 2022 09:48:22 +0000 (17:48 +0800)]
ac/nir/cull: fix culling for lines
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19868>
Qiang Yu [Thu, 17 Nov 2022 02:17:21 +0000 (10:17 +0800)]
ac/nir/ngg,radv: use intrinsic base for instance_rate_inputs check
radeonsi use packed location base while radv use un-packed location.
So we adjust instance_rate_inputs in each driver to hide the difference.
Note the attribute slot number is less than 16, so we can shift
instance_rate_inputs in radv by VERT_ATTRIB_GENERIC0 which is 16.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19868>
Jason Ekstrand [Thu, 17 Nov 2022 16:40:58 +0000 (10:40 -0600)]
vulkan: Add a dummy vk_common_CmdSetColorBlendAdvancedEXT()
The entrypoint needs to exist but we don't need to do anything with it.
Fixes:
13c422e1b2ed ("anv: toggle on EXT_extended_dynamic_state3")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19817>
Jason Ekstrand [Thu, 17 Nov 2022 16:39:05 +0000 (10:39 -0600)]
vulkan: Add a common implementation of CmdSetSampleLocationsEnableEXT
Fixes:
13c422e1b2ed ("anv: toggle on EXT_extended_dynamic_state3")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19817>
Jason Ekstrand [Thu, 17 Nov 2022 16:35:49 +0000 (10:35 -0600)]
vulkan: Add state for extraPrimitiveOverestimationSize
Fixes:
13c422e1b2ed ("anv: toggle on EXT_extended_dynamic_state3")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19817>
Karol Herbst [Sat, 12 Nov 2022 16:10:59 +0000 (17:10 +0100)]
rusticl: advertise conformance on 12th Intel iGPUs
Submission can be found here:
https://www.khronos.org/conformance/adopters/conformant-products/opencl#submission_405
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Hard-reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19699>
Lionel Landwerlin [Sat, 19 Nov 2022 01:35:27 +0000 (03:35 +0200)]
anv: ensure CPS is initialized when KHR_fragment_shading_rate is disabled
We need to set CPS_MODE_NONE when no per coarse pixel dispatch.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
231651fd89fb ("anv: implement VK_KHR_fragment_shading_rate")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19867>
Lionel Landwerlin [Sat, 19 Nov 2022 12:29:43 +0000 (14:29 +0200)]
anv: fix 3d state initialization
We missed a couple of restriction leading to inconsistent 3d pipeline
state. It is mostly noticeable when doing a multiple sample dispatch
as the verify first 3d operation.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7531
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19867>
Ian Romanick [Mon, 9 Aug 2021 22:05:33 +0000 (15:05 -0700)]
nir/loop_analyze: Fix get_iteration for nir_op_fneu
Consider the loop:
float i = 0.0;
while (true) {
if (i != 0.0)
break;
i = i + 1.0;
}
This loop clearly executes exactly one time.
Some trickery is necessary to handle cases where the initial loop value
is very large and the increment is, by comparison, very small. From the
fenu_once test case,
float i = -
604462909807314587353088.0;
while (true) {
if (i != -
604462909807314587353088.0)
break;
i = i +
36028797018963968.0;
}
This loop should also execute exactly once, but this is much more
challenging to calculate due to precision issues.
Going towards smaller magnitude (i.e., adding a small positive value to
a large negative value) requires a smaller delta to make a difference
than going towards a larger magnitude. For this reason,
-
604462909807314587353088.0 +
36028797018963968.0 !=
-
604462909807314587353088.0, but -
604462909807314587353088.0 +
-
36028797018963968.0 == -
604462909807314587353088.0. Math class is
tough.
No changes in shader-db or fossil-db.
v2: Fix major bug in checking result of the eval_const_binop(nir_op_feq,
...) discovered while developing fneu_once_easy unit test. Fix a typo in
the comment just above that. Add fneu_once_easy test.
v3: Skip the iteration count adjustment tests for nir_op_fenu and
nir_op_ine. Since the iteration count is either 1 or unknown, all this
function can do is add numerical error. Add fenu_once tests.
v4: Change the initial value in the fneu_once test from large positive
to large negative. Change check in get_iteration from nir_op_fsub to
nir_op_fadd. Both changes from discussion with M Henning. Also add some
more explanation in fneu_once.
v5: Rename test cases.
Fixes:
6772a17acc8 ("nir: Add a loop analysis pass")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19732>
Ian Romanick [Mon, 9 Aug 2021 22:05:33 +0000 (15:05 -0700)]
nir/loop_analyze: Fix get_iteration for nir_op_ine
I discovered this problem because adding an algebraic transformation to
convert some uge and ult to ieq or ine caused a couple loops to stop
unrolling. Consider the loop:
uint i = 0;
while (true) {
if (i >= 1)
break;
i++;
}
This loop clearly executes exactly one time. Note that uge(x, 1) is
equivalent to ine(x, 0). Changing the condition to 'if (i != 0)' will
also execute exactly one time.
In the added test cases, uge_once correctly get an exact loop trip count
of 1. Without the changes to nir_loop_analyze.c, the ine_once case
detects a maximum loop trip count of zero and does not get an exact loop
trip count.
No changes in shader-db or fossil-db.
v2: Move nir_op_fneu changes to a separate commit.
v3: Rename test cases.
Fixes:
6772a17acc8 ("nir: Add a loop analysis pass")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19732>
Ian Romanick [Tue, 15 Nov 2022 03:07:06 +0000 (19:07 -0800)]
nir/loop_analyze: Add basic unit test framework
This test comes from a comment in the loop analysis code.
The ine_zero test checks that zero iteration loops involving ine are
correctly identified.
v2: Add ine_zero test. Suggested by Tim.
v3: Rename test cases.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19732>
Karol Herbst [Sat, 19 Nov 2022 20:44:28 +0000 (21:44 +0100)]
rusticl/device: put space at the end of CL_DEVICE_VERSION
Apparently some software relies on that and the spec kind of says it's
there.
Fixes:
20c90fed5a0 ("rusticl: added")
Reported-by: sobkas
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19872>
Adam Jackson [Mon, 21 Nov 2022 20:46:03 +0000 (15:46 -0500)]
egl: Fix uninitialized variable warning
Fedora's gcc 12.2.1 says:
../src/egl/main/eglapi.c: In function ‘eglDupNativeFenceFDANDROID’:
../src/egl/main/eglapi.c:2268:11: warning: ‘ret’ may be used uninitialized [-Wmaybe-uninitialized]
2268 | EGLint ret;
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19913>
Pavel Ondračka [Wed, 16 Nov 2022 21:09:50 +0000 (22:09 +0100)]
r300: don't reuse destination registers when lowering
Regalloc can sort it out later. No significant change is shader-db, the
one instruction reduction is likely because some optimize pass can
actually work better when we are closer to ssa-like form.
RV530:
total instructions in shared programs: 133718 -> 133717 (<.01%)
instructions in affected programs: 47 -> 46 (-2.13%)
helped: 1
HURT: 0
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19853>
Pavel Ondračka [Fri, 7 Oct 2022 20:02:40 +0000 (22:02 +0200)]
r300: simplify rc_find_free_temporary
Back when we had a stupid register allocator we did a lot of tricks to
optimize the register usage. The old version of rc_find_free_temporary
did a full program search each time it was called to find out what
registers and channels are actually used and than used that info to give
us the first free register to use.
Now that we have a proper register allocator both for vertex and
fragment shaders, this is no longer needed. Just scan the program when
called for the first time to find the first unused temporary index and
than increment by one everytime. Regalloc can sort it out later.
No change in shader-db confirms this assumption is sound.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19853>
Rob Clark [Tue, 15 Nov 2022 17:19:19 +0000 (09:19 -0800)]
freedreno/a6xx: Remove unneeded MSAA clear fallback
This was added in commit
911ce374caf ("freedreno/a6xx: Fix MSAA clear"),
but the only case that can't handle fast-clear is sysmem blitter clear
path.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19884>
Rob Clark [Sun, 20 Nov 2022 17:21:43 +0000 (09:21 -0800)]
freedreno/a6xx: Use fallback path for MSAA clear_texture()
The trick for emulating MSAA clear by adjusting blit coords tends to
fall over with tiled/ubwc, so just use the fallback path instead.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19884>
David Heidelberg [Mon, 21 Nov 2022 16:19:33 +0000 (17:19 +0100)]
.gitignore: add VSCode and VSCodium
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19902>
David Heidelberg [Sat, 19 Nov 2022 20:30:39 +0000 (21:30 +0100)]
ci: ci_run_n_monitor.py: fail when job is not found
Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19902>
Emma Anholt [Mon, 21 Nov 2022 18:52:13 +0000 (10:52 -0800)]
ci/freedreno: add some missing a630 flakes.
Two from the GL 4.5 update, one that's been around longer.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19905>
Emma Anholt [Mon, 21 Nov 2022 17:31:59 +0000 (09:31 -0800)]
ci/turnip+zink: Generalize the 16-bit copy_image fails.
We just had another fail of the non_compressed texture2d_array group, and
we've got enough of a pattern here.
I left in the specific cases that had some debug info, though.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19905>
Alyssa Rosenzweig [Sun, 13 Nov 2022 03:05:58 +0000 (22:05 -0500)]
asahi: Wire up all BCn formats
We have these native. Passes the relevant piglits. Large reduction in memory
usage on Xonotic on higher settings (8x less memory per texture), which allows
Xonotic to run at high settings without OOMing.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Tested-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19903>
Gert Wollny [Thu, 10 Nov 2022 17:48:29 +0000 (18:48 +0100)]
virgl: don't a use staging when a resources created with the shared flag
There seems to be a problem with running firefox by using Xwayland that
results in a shared resources being not always tagged as using staging.
As a result one process tries to map the resource that was allocated as
one that uses staging without actually using the staging resource, and
hence the mapped range only accounts for the small region that we have
to allocated because a zero-allocation doesn't work, but the application
mapping the resource assumes that a properly sized range is mapped, and
consequently this results in invalid memory access.
To work around this issue disable creating staging for resources that
are created by using shared binding. It is not clear to me whether this
is the best fix, but it seems to quell the issue.
Fixes:
c9d99b7eec7ec14d6d71d381a424b6280d75a882
virgl: Fix texture transfers by using a staging resource
Related: https://gitlab.freedesktop.org/virgl/virglrenderer/-/issues/291
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19655>
Sajeesh Sidharthan [Sun, 20 Nov 2022 06:47:50 +0000 (22:47 -0800)]
gallium/drivers: copy only the actual number of slice parameters
currently max number of slice(tile) parameters are copied for av1.
copy only actual number of slice parameters
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19878>
Rhys Perry [Tue, 15 Nov 2022 12:10:40 +0000 (12:10 +0000)]
nir/algebraic: shrink 64-bit bitwise operations with 0/-1 constant half
fossil-db (navi21):
Totals from 457 (0.34% of 135636) affected shaders:
Instrs: 259349 -> 250383 (-3.46%)
CodeSize: 1411976 -> 1369136 (-3.03%)
Latency: 2175961 -> 2148158 (-1.28%)
InvThroughput: 502206 -> 490244 (-2.38%)
Copies: 15238 -> 15232 (-0.04%); split: -0.07%, +0.03%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19748>
Konstantin Seurer [Sun, 20 Nov 2022 15:05:21 +0000 (16:05 +0100)]
radv/rt: Return the correct result for requested deferral
We do not implement deferred host operations so we will return
VK_OPERATION_NOT_DEFERRED_KHR for now.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19882>
Sajeesh Sidharthan [Sun, 20 Nov 2022 06:34:37 +0000 (22:34 -0800)]
frontends/va: remove unused slice_param_idx variable
slice_param_idx was added to handle multiple slice params.
it's not used anymore.
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19877>
Rhys Perry [Wed, 16 Nov 2022 15:08:34 +0000 (15:08 +0000)]
aco: ensure MRT0 is written with dual source blending
Fixes crucible test func.shader.dualsrc_mrt0_undef on polaris10.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19806>
Rhys Perry [Wed, 16 Nov 2022 15:08:34 +0000 (15:08 +0000)]
radv: disable MRT compaction with dual-source blending
Fixes crucible tests func.shader.dualsrc_mrt0_undef on navi21 and
func.shader.dualsrc_mrt1_undef on polaris10.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19806>
José Roberto de Souza [Thu, 17 Nov 2022 20:15:11 +0000 (12:15 -0800)]
iris: Fix iris_bo_alloc() flags call argument
binder_realloc() -> iris_bo_alloc() is setting 4096 as flags parameter.
Up to now this is harmeless as there is no BO_ALLOC flag that uses
bit 12 but is better to avoid any future issues.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19898>
Danylo Piliaiev [Fri, 11 Nov 2022 15:40:53 +0000 (16:40 +0100)]
tu: Implement VK_EXT_post_depth_coverage
Passes:
dEQP-VK.pipeline.monolithic.multisample.sample_mask_with_depth_test.*
KHR-GL45.post_depth_coverage_tests.*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19682>
Pavel Ondračka [Tue, 15 Nov 2022 12:33:19 +0000 (13:33 +0100)]
r300: more informative too many ALU instructions error
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19766>
Pavel Ondračka [Tue, 15 Nov 2022 11:48:00 +0000 (12:48 +0100)]
r300: delete backend branch emulation
We now depend on NIR doing the right thing. It was not able to
handle the few cases where NIR failed anyway (and even if it did,
such complex cases would hit the instruction limit later).
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19766>
Pavel Ondračka [Tue, 15 Nov 2022 11:46:50 +0000 (12:46 +0100)]
r300: abort shader compilation early on loops and branches
R300/R400 GPUs can't do it in hardware and all the lowering should have
happened in NIR already, there is no point in wasting CPU time, just to
abort later when emitting.
Reduces CPU time for dEQP run by ~25% for RV370. The wallclock time is
now just slighly above 1 minute at 10 threads, mostly determined by the
long-running dEQP-GLES2.functional.flush_finish.* tests.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19766>
Bas Nieuwenhuizen [Sat, 19 Nov 2022 02:28:56 +0000 (03:28 +0100)]
radv: Fix custom build id with C90 compilation.
Seems some build configurations have problems with VLAs still.
Fixes:
97641e5c942 ("radv: Add ability to override the build id for the cache.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19869>
Maíra Canal [Fri, 4 Nov 2022 21:04:49 +0000 (18:04 -0300)]
v3dv: fix multiple typos
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19538>
Gert Wollny [Mon, 21 Nov 2022 08:39:35 +0000 (09:39 +0100)]
r600: Fix lower-to-scalar on TTN path
We must limit what alu ops are scalazized, and since we now
run finalize_nir we also have to make sure not to try to
scalarize backend specific instructions that are introduced
there.
While we touch the code, also remove the vectorization, it is
no longer helping.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7747
Fixes:
a81c50a2 (r600/sfn: implement finalize_nir)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19892>
Gert Wollny [Sun, 20 Nov 2022 16:32:21 +0000 (17:32 +0100)]
r600: reference glsl type system during translation
VL doesn't initialize the type systen, but creates shaders in TGSI.
When these are translated to NIR and then compiled in the driver
we need to have a reference to the glsl type system.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7453
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19883>
Daniil Tatianin [Sun, 20 Nov 2022 11:26:36 +0000 (14:26 +0300)]
intel_batch_decoder: disasm shaders when decoding states besides VS
Previously only 'decode_vs_state' would dump the referenced shader,
which meant we completely ignored every other shader when decoding
the '3DSTATE_PIPELINED_POINTERS' command.
Move the program disassembly logic from 'decode_vs_state' into a
common 'disasm_program_from_group' helper and call it from every
other decode_*_state function, too.
Signed-off-by: Daniil Tatianin <99danilt@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19880>
Jose Maria Casanova Crespo [Wed, 9 Nov 2022 11:37:18 +0000 (12:37 +0100)]
v3d: Minor fixes on sand8 blit based on sand30 modifications
* load_uniform for sand8_stride is uint32 instead of int32 and its range
is 4 instead of 1 as it is counted in bytes.
* Now we save and restore constant buffer 1 properly for the ubo used
in the blit. We need to take into account that in V3D the first UBO
with index 0 is stored on constant buffer 1, because gallium uses
internally contant buffer 0 (See for reference commit
c8212731e7d67a7)
* Removed not needed return.
* Added shader information about uniforms, ubos, inputs and outputs.
* Fixed typos in the comments.
Fixes:
95c4f0f91098 "v3d: Enables DRM_FORMAT_MOD_BROADCOM_SAND128 support"
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
Jose Maria Casanova Crespo [Wed, 9 Nov 2022 12:10:12 +0000 (13:10 +0100)]
v3d: Also expose DRM_FORMAT_MOD_BROADCOM_SAND128 with PIPE_FORMAT_P030
Now we can display h265-10bit decoded frames formats on Raspberry Pi 4
devices on GL/ES applications.
v2: Don't expose LINEAR or UIF formats for P030 format.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
Jose Maria Casanova Crespo [Wed, 9 Nov 2022 11:39:01 +0000 (12:39 +0100)]
v3d: Blit for P030 format with BROADCOM_SAND128 modifier to P010 UIF
Implements the support to blit SAND modifier with columns 128-bytes-wide
support for P030 format to P010 with UIF layout. This allows sampling
from H265 10-bit frames exported by the video decoder on the Raspberry
Pi 4 devices.
When a DRM_FORMAT_MOD_BROADCOM_SAND128 is enabled with an imported P030
texture. The sand30 blit converts the Luma and Chroma planes to
a tiled P010 format that can be sampled using gallium YUV lowerings
without the interleaved 128-bytes-wide-columns.
This patch follows a similar approach to SAND8 blit but extracting luma
and chroma components from the DRM_FORMAT_P030 format. P030 is a two
plane YCbCr420 format where 3 10 bit components with 2 padding bits are
packed in 4 bytes.
index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0
[2:10:10:10:2:10:10:10] little endian
After the sand30_blit is done, the shadow texture is an UIF tiled texture
with an R16_UNORM format for luma and R16G16_UNORM for chroma.
To reduce the number of texture-fetch operations during the blit, we
read pairs of 32-bit dwords. They include 6 10-bit unorm components.
And then we write 4 UNORM16 components from an uvec4 because our render
targets do not support writing to UNORM16 formats.
As sampling will be done using 16bpp (luma) and 32bpp (chroma), the
sand30_blit writes consider the different microtile layouts of UIF
format between 64, 32 and 16 bpp.
v2: Fixes save and recovery of constant buffers (Iago)
Typo corrections. (Iago)
Removed not needed return. (Iago)
Added shader information about uniforms, ubos, inputs and outputs.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
Jose Maria Casanova Crespo [Wed, 9 Nov 2022 12:07:26 +0000 (13:07 +0100)]
gallium/dri: Add P030 format
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
Samuel Pitoiset [Fri, 18 Nov 2022 08:36:46 +0000 (09:36 +0100)]
zink: require extendedDynamicState3ColorBlendEquation for full ds3
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19851>
Tatsuyuki Ishi [Fri, 18 Nov 2022 06:59:50 +0000 (15:59 +0900)]
radv: Support accelerationStructureCaptureReplay.
The address itself was already stable assuming that the memory itself was
allocated with capture/replay. Enable the feature flag and add an equality
check to return VK_ERROR_INVALID_OPAQUE_CAPTURE_ADDRESS_KHR on mismatch.
Tested with:
- dEQP-VK.ray_tracing_pipeline.capture_replay.*
- q2rtx gfxrecon replays correctly without major errors.
* There are debug logs about VkBuffers missing opaque address
for unknown reason, however the AS part is confirmed to be correctly
captured.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19841>
Samuel Pitoiset [Fri, 18 Nov 2022 13:13:54 +0000 (14:13 +0100)]
radv/ci: add one more pipeline barrier test as flake
With the new memory type, this test timeout most of the time but it
always pass.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
Samuel Pitoiset [Tue, 20 Sep 2022 12:05:39 +0000 (14:05 +0200)]
radv: advertise VK_EXT_descriptor_buffer
Pass dEQP-VK.*descriptor_buffer*.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
Samuel Pitoiset [Thu, 29 Sep 2022 12:12:08 +0000 (14:12 +0200)]
radv: implement VK_EXT_descriptor_buffer
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
Samuel Pitoiset [Wed, 21 Sep 2022 13:20:09 +0000 (15:20 +0200)]
radv: always restore NULL descriptor sets for meta operations
A valid but NULL descriptor set indicates a descriptor buffer.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
Samuel Pitoiset [Thu, 29 Sep 2022 12:11:18 +0000 (14:11 +0200)]
radv: rework writing image/buffer/accel_struct descriptors slightly
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
Samuel Pitoiset [Thu, 29 Sep 2022 11:55:46 +0000 (13:55 +0200)]
radv: avoid RMW operations in radv_make_texel_buffer_descriptor()
This would hurt performance depending on the memory type.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
Samuel Pitoiset [Wed, 21 Sep 2022 15:51:57 +0000 (17:51 +0200)]
radv: force 32-bit address-space for descriptor buffers usage
Descriptor pointers are passed through shaders with 32-bit.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
Samuel Pitoiset [Thu, 29 Sep 2022 12:17:03 +0000 (14:17 +0200)]
radv: add 32-bit memory types for visible VRAM and cached GTT
These would be only exposed for descriptor buffers which need to be
CPU accessible and because descriptor pointers are 32-bit.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
Vinson Lee [Sun, 20 Nov 2022 22:08:50 +0000 (14:08 -0800)]
asahi: Fix memory leak on error path.
Fix defect reported by Coverity Scan.
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable nresource going out of scope leaks the storage it points to.
Fixes:
7522f4f7147 ("asahi: Make resource creation code modifier-aware")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19889>
Qiang Yu [Fri, 18 Nov 2022 08:37:19 +0000 (16:37 +0800)]
ac/llvm: fix 16bit varying llvm compile error
Found when 16bit vec3 varying with llvm14 (not found
when llvm15), one 32bit vec4 slot is filled like this:
vec3[0] | undef
vec3[1] | undef
vec3[2] | undef
undef | undef
LLVM error is for the elements with undef:
%287 = insertelement float %280, half %279, i64 0
After this change, we get:
%287 = insertelement <2 x half> %280, half %279, i64 0
Fixes:
279eea5bda2 ("amd/llvm: Transition to LLVM "opaque pointers"")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19848>
Vinson Lee [Sun, 20 Nov 2022 21:41:55 +0000 (13:41 -0800)]
asahi: Fix memory leak on error path.
Fix defect reported by Coverity Scan.
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable rsc going out of scope leaks the storage it points to.
Fixes:
01964625eb2 ("asahi: Implement agx_resource_from_handle")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19887>
Yusuf Khan [Sun, 20 Nov 2022 02:33:31 +0000 (20:33 -0600)]
mapi: update gles 1.1 extention packet link
Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19874>
Daniel Schürmann [Fri, 18 Nov 2022 12:58:26 +0000 (13:58 +0100)]
radv/rt: use explicitly named sbt entries in radv_pipeline_group_handle
This improves readability, makes it less error-prone and
allows for easier changes in future.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19850>
Eric Engestrom [Thu, 10 Nov 2022 12:14:12 +0000 (12:14 +0000)]
v3d(v): account for debug flags when using the cache
Signed-off-by: Eric Engestrom <eric@igalia.com>
Cc: mesa-stable
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19796>
Alyssa Rosenzweig [Sat, 19 Nov 2022 03:28:05 +0000 (22:28 -0500)]
asahi: Advertise all supported renderable formats
Now that we have the new tilebuffer infrastructure in place, all renderable
formats should be working.
This reverts commit
32ab63b4fcaaaf832d549ddcf7b3a225c5f73df4.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 18:48:14 +0000 (13:48 -0500)]
asahi,agx: Use new tilebuffer infrastructure
Flag day change to replace the previous hardcoded background/end-of-tile shaders
and the API-style load/store_output in fragment shaders with the generated
shaders and lowered *_agx intrinsics. This gets us working non-UNORM8 render
targets and working MRT. It's also a step in the direction of working MSAA but
that needs a lot more work, since the multisampling programming model on AGX is
quite different from any of the APIs (including Metal).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 18:12:02 +0000 (13:12 -0500)]
asahi: Add new clear/reload/store infrastructure
With multiple render targets, it's not practical to generate all
variants of the background and end-of-tile programs at start up. Rather
than trying, add a hash table of meta program keys to background
programs, and compile variants as they're needed.
With the new infrastructure, it's sensible to handle clears with the
same code path as reloads. In addition to getting us closer to multiple
render target support, this gets us support for non-RGBA8 render
targets, as the u8norm tilebuffer format was baked into the hardcoded
clear shader and store shaders used before.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 04:18:14 +0000 (23:18 -0500)]
asahi: Use correct tib settings for USC
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 04:08:29 +0000 (23:08 -0500)]
asahi: Extend texture descriptor packing for MSAA
Multisampling uses different values of the dimension enum in tandem with a new
samples field. Handle this in agx_pack_texture (split off here) so we can use
the new functionality for texture descriptors in reloads too.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 04:07:24 +0000 (23:07 -0500)]
asahi: Remove some bogus asserts
Hitting in dEQP-GLES31
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 04:00:48 +0000 (23:00 -0500)]
asahi: Implement texture_barrier trivially
For the advanced blending tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 03:59:42 +0000 (22:59 -0500)]
asahi: Calculate tilebuffer layout per batch
It won't be fixed soon.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 03:50:03 +0000 (22:50 -0500)]
asahi: Add agx_usc_shared_none helper
Convenience for vertex USC programs.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 03:49:45 +0000 (22:49 -0500)]
asahi: Add R16 SNORM formats
For completeness, since we do have hardware for this.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 03:48:20 +0000 (22:48 -0500)]
asahi: Add more XML via PowerVR
These bits are the same as RGX.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 03:47:52 +0000 (22:47 -0500)]
asahi: Add note to XML about 16-bit varyings
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 03:47:28 +0000 (22:47 -0500)]
asahi: Identify more depth-related fields in XML
Needed for gl_FragDepth writes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 03:46:55 +0000 (22:46 -0500)]
asahi: Add XML for layered rendering
We don't need to support this for a while but it's good to know the mechanism.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Alyssa Rosenzweig [Sat, 19 Nov 2022 03:35:05 +0000 (22:35 -0500)]
asahi: Add NIR pass to lower tilebuffer access
The compiler can't handle load/store_output directly for nontrivial tilebuffer
layouts. Add a NIR pass to lower these intrinsics, applying a given layout.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>