Rhys Perry [Tue, 25 May 2021 16:01:23 +0000 (17:01 +0100)]
radv: don't allocate DCC predicate if the image doesn't use DCC
Fixes replay of RenderDoc captures created before
a7c0cf500b3.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10983>
Samuel Pitoiset [Mon, 24 May 2021 15:05:30 +0000 (17:05 +0200)]
aco: fix emitting discard when the program just ends
For fragment shaders that only contain a discard, the exec mask has
to be zero'd and everything discarded.
It seems unnecessary to emit an export here because if the FS has no
exports, the compiler already emits a null export at the end.
Fixes incorrect hair rendering in Detroit: Become Human.
fossil-db (Sienna Cichlid):
Totals from 3 (0.00% of 149839) affected shaders:
CodeSize: 2896 -> 2872 (-0.83%)
Instrs: 556 -> 553 (-0.54%)
Latency: 29266 -> 29214 (-0.18%)
InvThroughput: 3374 -> 3372 (-0.06%)
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10955>
Iago Toral Quiroga [Tue, 25 May 2021 11:21:55 +0000 (13:21 +0200)]
v3dv: implement VK_KHR_bind_memory2
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11001>
Erik Faye-Lund [Tue, 25 May 2021 14:03:27 +0000 (16:03 +0200)]
v3d: use helper to simplify things
We can use the util_prim_restart_index_from_size helper to avoid
open-coding the implicit index size here.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10981>
Iago Toral Quiroga [Tue, 25 May 2021 08:49:06 +0000 (10:49 +0200)]
v3dv: implement VK_KHR_maintenance3
We don't have any special restrictions associated with the number
of descriptors in a set other than maybe not exceeding what we can
put in a single memory allocation, so in practice, applications will
be limited by the per-stage contraints defined by other Vulkan limits.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10970>
Iago Toral Quiroga [Tue, 25 May 2021 07:48:39 +0000 (09:48 +0200)]
v3dv: define V3D_MAX_BUFFER_RANGE
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10970>
Samuel Pitoiset [Thu, 6 May 2021 12:51:04 +0000 (14:51 +0200)]
radv: use radv_dcc_enabled() for the FB mip flush workaround
This has no effects because radv_image_has_CB_metadata() still
accounts for DCC which is incorrect. This should be changed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10667>
Samuel Pitoiset [Thu, 6 May 2021 12:38:56 +0000 (14:38 +0200)]
radv: do not decompress DCC for partial resolves if stores are supported
It seems unnecessary.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10667>
Samuel Pitoiset [Thu, 6 May 2021 12:30:19 +0000 (14:30 +0200)]
radv: only init DCC if compressed in the HW resolve path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10667>
Samuel Pitoiset [Thu, 6 May 2021 12:18:40 +0000 (14:18 +0200)]
radv: only mark DCC as compressed when drawing if layout allows it
Just having DCC enabled on the base level doesn't mean we are
using compressed rendering.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10667>
Samuel Pitoiset [Thu, 6 May 2021 12:06:05 +0000 (14:06 +0200)]
radv: remove redundant call to radv_dcc_enabled()
radv_layout_dcc_compressed() is now per level.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10667>
Samuel Pitoiset [Thu, 6 May 2021 10:20:37 +0000 (12:20 +0200)]
radv: pass an image range to radv_layout_dcc_compressed()
With DCC and mipmaps, some mips can't be compressed and it makes
sense to check this here.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10667>
Emma Anholt [Tue, 25 May 2021 18:37:00 +0000 (11:37 -0700)]
ci/freedreno: Add another a630 piglit flake.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10986>
Andres Gomez [Tue, 18 May 2021 11:14:35 +0000 (14:14 +0300)]
ci: disentangle tags for containers and artifacts produced by them
In order to reduce the amount of building work and network traffic, we
use docker caching. For that, we use the MESA_IMAGE_TAG and
MESA_BASE_TAG env variables which build the MESA_IMAGE variable to
identify different containers.
We are also using these tags to identify the cached artifacts produced
by other containers when those are part of the underlying OS to run
directly in DUTs through the DISTRIBUTION_TAG env variable.
The undesirable collateral effect is that we cannot combine a test job
using a container which would like to make use of some of the cached
artifacts created by another container. In other words, we cannot have
a job using a DISTRIBUTION_TAG and a MESA_IMAGE using a different
MESA_[IMAGE|BASE]_TAG variables.
Now, we split the usage in the DISTRIBUTION_TAG through the definition
of MESA_ARTIFACTS_TAG AND MESA_ARTIFACTS_BASE_TAG.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10977>
Mike Blumenkrantz [Tue, 4 May 2021 14:24:03 +0000 (10:24 -0400)]
nir/builder: add nir_mask
it's handy to have functions for generating masks
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10620>
Mike Blumenkrantz [Tue, 26 Jan 2021 21:41:37 +0000 (16:41 -0500)]
zink: disable push descriptors on amd
I'm told this is bad for perf
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10998>
Mike Blumenkrantz [Tue, 23 Mar 2021 15:11:00 +0000 (11:11 -0400)]
zink: hook up push descriptor and descriptor template extensions
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10998>
Mike Blumenkrantz [Thu, 21 Jan 2021 19:40:26 +0000 (14:40 -0500)]
zink: switch to memory barriers instead of actual buffer barriers
drivers don't seem to actually use the buffer part of the info, so this is
just wasting cycles initializing the values
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10996>
Mike Blumenkrantz [Thu, 21 Jan 2021 19:40:09 +0000 (14:40 -0500)]
zink: mark some buffer barrier functions inline/static
minor optimization
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10996>
Mike Blumenkrantz [Wed, 19 May 2021 13:59:31 +0000 (09:59 -0400)]
zink: call tc_driver_internal_flush_notify() on flush
I think this is right?
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10882>
Mike Blumenkrantz [Wed, 19 May 2021 13:51:17 +0000 (09:51 -0400)]
zink: implement a tc is_resource_busy hook
this is kinda gross for now, but it gets the job done
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10882>
Mike Blumenkrantz [Wed, 19 May 2021 16:39:48 +0000 (12:39 -0400)]
zink: force streamout rebind when mapping a streamout buffer for writing
if the contents of the buffer change between uses, trigger the rebind path
next time a draw happens for synchronization
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10882>
Mike Blumenkrantz [Wed, 19 May 2021 14:08:22 +0000 (10:08 -0400)]
zink: implement tc idalloc resource id stuff
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10882>
Mike Blumenkrantz [Wed, 12 May 2021 15:08:04 +0000 (11:08 -0400)]
zink: move timeline_wait() to screen function
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10882>
Mike Blumenkrantz [Wed, 12 May 2021 15:06:11 +0000 (11:06 -0400)]
zink: make timeline_wait use only a screen param
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10882>
Mike Blumenkrantz [Tue, 19 Jan 2021 17:05:48 +0000 (12:05 -0500)]
zink: add vertex buffer barriers during bind
now we have tracking for vbo binds and can automatically reapply the correct
barrier just before draw if the resource is modified after bind
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Mike Blumenkrantz [Fri, 15 Jan 2021 18:22:10 +0000 (13:22 -0500)]
zink: emit descriptor barriers and references during bind
there's not actually any reason to do these during draw other than wasting
cpu cycles, and it has the side benefit of providing a bunch more info for rebinds
image resources for gfx shaders need to have their barriers deferred until draw time,
however, as it's unknown what layout they'll require until that point due to potentially
being bound to multiple descriptor types
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Mike Blumenkrantz [Mon, 18 Jan 2021 17:16:51 +0000 (12:16 -0500)]
zink: improve samplerview update flagging
we shouldn't actually need to use the hash value here now that the
surfaces and bufferviews have been deduplicated
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Mike Blumenkrantz [Thu, 1 Apr 2021 19:18:51 +0000 (15:18 -0400)]
zink: abstract descriptor functionality and make descriptor structs private
the first step to adding modular descriptor managers is to isolate the existing one
so that it can be easily swapped out
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Mike Blumenkrantz [Thu, 1 Apr 2021 19:18:16 +0000 (15:18 -0400)]
zink: replace has_descriptors program member with a util function
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Mike Blumenkrantz [Thu, 1 Apr 2021 19:11:42 +0000 (15:11 -0400)]
zink: pass descriptor type to set layout create()
this will be useful in the future
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Mike Blumenkrantz [Thu, 1 Apr 2021 19:08:47 +0000 (15:08 -0400)]
zink: unify pipeline layout creation and move to descriptor_program_init
the descriptor layouts are the last component needed to create the pipeline
layout, so it makes sense to streamline setup by having the pipeline layout
created from a single place for both types of pipelines
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Mike Blumenkrantz [Thu, 1 Apr 2021 19:00:51 +0000 (15:00 -0400)]
zink: make a public util function for allocating descriptor sets
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Mike Blumenkrantz [Thu, 1 Apr 2021 18:59:37 +0000 (14:59 -0400)]
zink: make descriptor_layout_get a public util function
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Mike Blumenkrantz [Thu, 1 Apr 2021 18:13:16 +0000 (14:13 -0400)]
zink: rename ptr_add_usage -> batch_ptr_add_usage
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Yiwei Zhang [Thu, 13 May 2021 22:57:44 +0000 (22:57 +0000)]
egl/android: check front rendering support for cros gralloc
Enable EGL_KHR_mutable_render_buffer when below conditions are met:
1. Driver part implementation of this extension is available
2. Loader part implementation of this extension is available
3. ClientAPIs must be OpenGL ES bits (ES, ES2 or ES3)
4. Gralloc is cros gralloc and it supports front render usage query
(4) is optional as long as another gralloc supports similar query.
Upon window surface creation, if the surface type has mutable render
buffer, then append the cached front rendering usage to the existing
usage and properly set to the ANativeWindow.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10685>
Yiwei Zhang [Thu, 13 May 2021 18:38:50 +0000 (18:38 +0000)]
gallium/dri: implement EGL_KHR_mutable_render_buffer
Tested with low-lantency stylus apps with this extension enabled, no
regression on the cts.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10685>
Yiwei Zhang [Thu, 13 May 2021 06:15:10 +0000 (06:15 +0000)]
gallium/st: add a back buffer fallback for front rendering
Unlike front buffer used by big GL API for front rendering,
EGL_KHR_mutable_render_buffer together with ES redirects GL_BACK to the
front buffer.
This patch adds a fallback to use back buffer and ensures no behavior
change for unrelated frontends.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10685>
Nanley Chery [Wed, 17 Feb 2021 22:49:11 +0000 (14:49 -0800)]
intel/isl: Fix HiZ+CCS comment about ambiguates
Note that CCS isn't ambiguated during a HiZ ambiguate. Dumping the CCS
surface after a HiZ ambiguate shows that the CCS is unchanged.
Fixes:
98dc7f56b7d ("intel/isl: Add a separate ISL_AUX_USAGE_HIZ_CCS_WT")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9112>
Nanley Chery [Fri, 21 May 2021 21:55:26 +0000 (14:55 -0700)]
anv,iris: Port the D16 workaround stalls to BLORP
Commit
cd40110420b added stalls before register writes that occur when
drivers emit depth stencil packets. However, it only did so for
non-BLORP draw calls. Since those packets are sometimes emitted during
BLORP calls, add stalls there too.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4574
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10939>
Nanley Chery [Fri, 21 May 2021 21:50:38 +0000 (14:50 -0700)]
intel: Limit the D16 workarounds to Gfx12.0
The workarounds introduced in
cd40110420b are no longer needed on
Gfx12.5.
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10939>
Andres Gomez [Tue, 18 May 2021 14:00:27 +0000 (17:00 +0300)]
ci: add VKD3D-Proton testsuite job for radv's Navy Flounder
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
Andres Gomez [Tue, 18 May 2021 13:54:54 +0000 (16:54 +0300)]
ci: add VKD3D-Proton testsuite runner
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
Andres Gomez [Wed, 10 Mar 2021 14:46:51 +0000 (16:46 +0200)]
ci: include VKD3D-Proton tests into the VK test container
Instead of installing the distribution package, build and install
locally, including the tests.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
Andres Gomez [Tue, 18 May 2021 12:22:18 +0000 (15:22 +0300)]
ci: add radv's trace job for Navy Flounder
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
Andres Gomez [Tue, 18 May 2021 11:59:37 +0000 (14:59 +0300)]
ci: uprev DXVK to 1.8.1
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
Andres Gomez [Tue, 18 May 2021 12:06:09 +0000 (15:06 +0300)]
ci: uprev apitrace to 10.0
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
Andres Gomez [Tue, 18 May 2021 12:21:55 +0000 (15:21 +0300)]
ci: remove radv's trace job for Polaris10
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
Andres Gomez [Tue, 18 May 2021 12:20:37 +0000 (15:20 +0300)]
ci: update radv's trace job tag for Raven
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
Chia-I Wu [Fri, 21 May 2021 20:41:40 +0000 (13:41 -0700)]
util/u_thread: fix u_thread_setname for long names
"WSI swapchain queue", set by vulkan/wsi/x11, is longer than 15
characters.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10935>
Marek Olšák [Thu, 20 May 2021 09:27:43 +0000 (05:27 -0400)]
radeonsi: remove DFSM after we discovered how bad it is
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 20 May 2021 09:05:15 +0000 (05:05 -0400)]
radeonsi: disable DFSM on gfx9 by default because it decreases performance a lot
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Tue, 27 Apr 2021 01:33:24 +0000 (21:33 -0400)]
radeonsi: implement threaded context callbacks for resource busy checking
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 6 May 2021 00:16:31 +0000 (20:16 -0400)]
radeonsi: generate buffer_id_unique for u_threaded_context
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 11:55:05 +0000 (07:55 -0400)]
radeonsi: allow changing the NGG subgroup size to 256 but don't change it yet
Currently, 128 seems to have the best performance.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 06:41:52 +0000 (02:41 -0400)]
radeonsi: rewrite the prefix sum computation for shader culling
Instead of storing the vertex mask per wave into LDS and then computing
the prefix sum, store 8-bit bitcounts (vertex counts) of the vertex masks
into LDS. This allows us to compute the sum using v_sad_u8, which computes
a sum of 4 i8vec4 components in one instruction.
Each i8vec4 of vertex counts is loaded in parallel threads (one dword
per thread) instead of all being loaded in thread 0, and readlane copies
them to SGPRs instead of readfirstlane.
LDS is no longer initialized before culling. Instead, the counts for
inactive waves are masked with AND later.
Incorrect old comments are also fixed.
This change removes 80 bytes from the code size, and it allows increasing
the workgroup size from 128 to 256. (which is the main motivation for this)
Now changing the workgroup size with wave64 has no effect on the code size.
Switching to wave32 with 8 waves even generates slightly smaller code than
wave64 with 4 waves.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Mon, 17 May 2021 15:02:54 +0000 (11:02 -0400)]
radeonsi: add missing threaded_resource_deinit calls in fail paths
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 13 May 2021 03:21:36 +0000 (23:21 -0400)]
radeonsi: add a gfx10 hw bug workaround with the barrier before gs_alloc_req
Fixes:
8845a23698c - amd: add NAVI10 PCI IDs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 22 Apr 2021 04:38:37 +0000 (00:38 -0400)]
radeonsi: remove 8 bytes from si_resource, turn other 4 bytes into padding
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 22 Apr 2021 04:31:28 +0000 (00:31 -0400)]
radeonsi: change si_resource::alignment to alignment_log2 for better packing
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sun, 9 May 2021 22:33:24 +0000 (18:33 -0400)]
radeonsi: improve generated culling code by adding optimization barriers
This removes a lot of instructions and 16 bytes from the code size.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Mon, 10 May 2021 11:44:42 +0000 (07:44 -0400)]
radeonsi: re-enable fast launch with indexed tri strips because it doesn't hang
I don't know which change fixed this, but I can't reproduce the hang anymore.
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Tue, 11 May 2021 00:31:19 +0000 (20:31 -0400)]
radeonsi: remove a twice duplicated workaround for VERT_GRP_SIZE
This enables better lane occupancy.
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Mon, 10 May 2021 10:53:46 +0000 (06:53 -0400)]
radeonsi: fix the fast launch vert/prim thread counts if they are trimmed
This fixes the case when the counts were out of sync because one of them
was decreased.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Tue, 11 May 2021 13:11:34 +0000 (09:11 -0400)]
radeonsi: don't use GS fast launch with small instances
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 03:52:19 +0000 (23:52 -0400)]
radeonsi: don't disable L2 caching for staging textures
Uncached access can be slow if the box is not aligned nicely.
Also, caching in L2 might enable bigger PCIe bursts.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 03:47:23 +0000 (23:47 -0400)]
radeonsi: always use the L2 LRU cache policy for faster clears and copies
Waves and CP DMA can finish sooner if L2 doesn't do any evictions, which
is hard to predict.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Tue, 11 May 2021 00:03:04 +0000 (20:03 -0400)]
radeonsi: fix a coherency issue when VS memory stores are not visible in PS
If a shader has no param exports (no varyings), the pixel shader can start
after the VS position is written before the vertex shader finishes.
The fix is to wait for the memory stores before the position export.
The code needs to be restructured. First prepare param exports to get
nr_param_exports, then emit position exports with the wait, and then
emit param exports.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 02:52:42 +0000 (22:52 -0400)]
radeonsi: add a gfx10 bug workaround for NOT_EOP
Fixes:
cc24ec8c077 - radeonsi: set NOT_EOP for back-to-back draws on gfx10+
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 22 Apr 2021 02:14:03 +0000 (22:14 -0400)]
radeonsi: handle PIPE_CAP_MAX_VERTEX_BUFFERS
no change in behavior because the value is the same as the default
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Thu, 6 May 2021 21:37:24 +0000 (17:37 -0400)]
radeonsi: remove unused SI_IMAGE_ACCESS_AS_BUFFER
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Fri, 7 May 2021 13:17:12 +0000 (09:17 -0400)]
winsys/amdgpu: don't hold a mutex while accessing is_shared
It adds overhead to amdgpu_bo_wait and I'm not sure whether the mutex
is even needed.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Wed, 12 May 2021 16:00:31 +0000 (12:00 -0400)]
ac/llvm: don't draw the primitive for the dummy export workaround for Navi1x
for conservative rasterization
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 10:14:15 +0000 (06:14 -0400)]
ac/llvm: set range metadata on mbcnt and deduplicate get_thread_id
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 08:24:58 +0000 (04:24 -0400)]
ac/llvm: allow ac_build_optimization_barrier with SGPRs, pointers, and metadata
sgpr=true prevents moving the value to a VGPR.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 09:26:04 +0000 (05:26 -0400)]
ac/llvm: expose set_range_metadata to more users
I sometimes use it for experiments. It will be used later.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Sat, 8 May 2021 04:34:05 +0000 (00:34 -0400)]
ac/llvm: set target features per function instead of per target machine
This is a cleanup that allows the removal of the wave32 target machine and
the wave32 pass manager.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Wed, 28 Apr 2021 03:51:24 +0000 (23:51 -0400)]
ac/gpu_info: set has_zero_index_buffer_bug for Navi12 too
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Fri, 7 May 2021 11:01:44 +0000 (07:01 -0400)]
amd: fix incorrect addrlib comment for HTILE equations
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Fri, 7 May 2021 08:09:16 +0000 (04:09 -0400)]
amd/registers: regenerate json files without 32-bit register fields
Only a few of those were used in drivers.
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Marek Olšák [Fri, 7 May 2021 07:57:36 +0000 (03:57 -0400)]
amd/registers: don't generate 32-bit register fields
This removes confusing register types due to deduplication, such as:
"name": "SQ_WAVE_TTMP10",
"type_ref": "SPI_SHADER_USER_DATA_PS_0"
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
Samuel Pitoiset [Wed, 19 May 2021 07:14:13 +0000 (09:14 +0200)]
radv: remove an useless TODO for dynamic line width
We can't do anything it seems.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10881>
Samuel Pitoiset [Wed, 19 May 2021 07:13:54 +0000 (09:13 +0200)]
radv: ignore dynamic blend constants if blend isn't enabled
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10881>
Timur Kristóf [Fri, 21 May 2021 12:14:33 +0000 (14:14 +0200)]
aco: Don't eliminate exec write when it's used by a copy later.
Fixes:
bc130497472cb4ec4ec60695ed99b169d6681118
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10920>
Alyssa Rosenzweig [Fri, 5 Mar 2021 20:59:39 +0000 (20:59 +0000)]
panfrost: Add message preload to pan_shader_info
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10967>
Alyssa Rosenzweig [Fri, 5 Mar 2021 15:55:47 +0000 (15:55 +0000)]
panfrost: Add Message Preload descriptor XML
New to v7, allows executing up to +LD_VAR_IMM or +VAR_TEX instructions
before starting the shader.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10967>
Alyssa Rosenzweig [Mon, 24 May 2021 14:04:44 +0000 (10:04 -0400)]
panfrost/ci: Run jobs with PAN_MESA_DEBUG=sync
This way if there's a fault, the pipeline won't accidentally pass
and let bugs slip into main. This seems to have occurred on both T720
and G72, leading to flakes on both. I want flakeless CI, so this is a
step in eliminating flakes before they hit the tree.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Fri, 21 May 2021 22:14:22 +0000 (18:14 -0400)]
panfrost/ci: Remove reference to dated flag
This was removed ages ago, nobody updated it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Mon, 24 May 2021 21:06:41 +0000 (17:06 -0400)]
panfrost/ci: Disable terrain trace
It's reliably faulting in CI but not locally, and I can't figure out
what the difference could possibly be. Regardless I can't fix the fault
otherwise, and faultless CI matters more than losing a single trace
(from an app I manually test anyway).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Mon, 24 May 2021 15:07:11 +0000 (11:07 -0400)]
panfrost: Increase tiler_heap max allocation to 64MB
We previously allocated only 16MB, but this isn't always enough. Now
that we have growable (heap) on recent kernels, there's not much reason
to try to shrink this allocation.
Fixes OUT_OF_MEMORY fault on furmark trace.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Fri, 21 May 2021 21:42:19 +0000 (17:42 -0400)]
panfrost: Remove minimal mode
Superseded by abort-on-fault. It didn't work correctly in the presence
of MMU faults anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Fri, 21 May 2021 21:38:00 +0000 (17:38 -0400)]
panfrost: Abort on faults in SYNC mode
This allows failing fast (optionally still tracing, if set with
PAN_MESA_DEBUG=trace) when a GPU fault is introduced. This is better
behaviour for both use cases:
1. When debugging a known fault, setting this mode together with trace
will stop the driver as soon as a buggy command stream is submitted,
and the offending stream will be the last trace file.
2. When running test suites (particularly in CI), setting this mode
will detect faults and crash, causing the pipeline to fail fast as
opposed to incorrectly marking the run green if the test happens to
pass despite the faults and slow downs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Alyssa Rosenzweig [Fri, 21 May 2021 21:30:34 +0000 (17:30 -0400)]
panfrost: Lower max inputs again
Due to Midgard ABI silliness. We could fix this properly but I'm not
aware of any app that needs more than 16, so let's just revert to the
behaviour matching the DDK.
Fixes:
fdbf8c96fe2 ("panfrost: Use natural shader limits")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Lucas Stach [Fri, 13 Nov 2020 14:05:55 +0000 (15:05 +0100)]
etnaviv: flush used render buffers on context flush when neccessary
Some resources like backbuffers are explicitly flushed by the frontend
at the appropriate time, others however won't get flushed explicitly.
Remember those resources when they get emitted as a render buffer and
flush them on a context flush to make their content visible to other
entities sharing the buffer.
We still keep the optimized path for most resources where the frontend
promises to do the flushing for us and only enable implicit flushing
when a buffer handle is exported/imported without the
PIPE_HANDLE_USAGE_EXPLICIT_FLUSH flag set.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7603>
Lucas Stach [Fri, 13 Nov 2020 14:03:37 +0000 (15:03 +0100)]
etnaviv: remove double assigment of surface->texture
surf->base.texture is already assigned earlier via a proper
pipe_resource_reference call. Remove the superfluous assignement.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7603>
Lucas Stach [Fri, 13 Nov 2020 13:59:52 +0000 (14:59 +0100)]
frontend/dri: add EXPLICIT_FLUSH hint in dri2_resource_get_param
dri2_resource_get_param() is called from two different places right now.
Only one of them adds the EXPLICIT_FLUSH hint to the handle usage, which
may disable the optimizations provided by this hint without a reason.
Make sure to always add this hint when appropriate.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7603>
Lionel Landwerlin [Fri, 21 May 2021 15:36:31 +0000 (18:36 +0300)]
intel/perf: rename metric descriptions
There is an effort to drop the "Gen" prefix from much of our codebase.
This just applies this to the metrics.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
Lionel Landwerlin [Fri, 21 May 2021 15:35:46 +0000 (18:35 +0300)]
intel/perf: update Gen9/11 programming for AsyncCompute
Adding a register, similar to what was done for RenderBasic.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
Lionel Landwerlin [Fri, 21 May 2021 15:35:07 +0000 (18:35 +0300)]
intel/perf: add EHL availability condition to HDCAndSF counters
The availability of those counters depends on the topology.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
Lionel Landwerlin [Fri, 21 May 2021 15:34:41 +0000 (18:34 +0300)]
intel/perf: update Gen11 RenderBasic programming
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10930>
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