Craig Topper [Fri, 30 Dec 2022 00:33:18 +0000 (16:33 -0800)]
[RISCV] RISCVDAGToDAGISel::selectShiftMask to shift by (sub size-1, X).
If the shift amount is (sub C, X) where C is -1 modulo the size of
the shift, we can replace the sub with a NOT.
We could also use XORI X, size-1, but NOT would work better with
c.not from the future Zce extension.
Matt Arsenault [Mon, 28 Nov 2022 22:26:14 +0000 (17:26 -0500)]
AMDGPU/clang: Remove target features from address space test builtins
It turns out we can codegen these on targets without flat addressing,
although the runtime probably didn't put anything useful there. The
proper diagnostic would be to disallow flat pointer uses or languages
with them, not this one edge case. Allows removing one of the special
cases requiring subtarget support in the device libraries.
Lei Zhang [Thu, 29 Dec 2022 23:27:29 +0000 (15:27 -0800)]
[mlir][spirv] Fail vector.bitcast conversion with different bitwidth
Depending on the target environment, we may need to emulate certain
types, which can cause issue with bitcast.
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D140437
Matt Arsenault [Thu, 29 Dec 2022 23:11:14 +0000 (18:11 -0500)]
libclc: Add parentheses to silence warning
Fixes #59209
Dmitry Borisenkov [Thu, 29 Dec 2022 23:04:55 +0000 (18:04 -0500)]
DAG: Prevent store value forwarding to distinct addrspace load
DAGCombiner replaces (load const_addr1) directly chained with (store
(val, const_addr2)) with val if address space stripped const_addr1 ==
const_addr2. The patch fixes the issue by checking address spaces as
well. However, it might makes sense to not to chain together side
effects that belong to different address spaces in the first place and
make SelectionDAG::root address space aware.
Craig Topper [Thu, 29 Dec 2022 22:45:04 +0000 (14:45 -0800)]
[RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to bypass adds with constant.
If the shift amount is (add X, C) where C is 0 modulo the size of
the shift, we can bypass the add.
Similar to other targets like AArch64 and X86.
Matt Arsenault [Thu, 18 Jun 2020 01:46:28 +0000 (21:46 -0400)]
AMDGPU/clang: Add builtins for llvm.amdgcn.ballot
Use explicit _w32/_w64 suffixes for the wave size to be consistent
with the existing other wave dependent intrinsics. Also start
diagnosing trying to use both wave32 and wave64.
I would have preferred to avoid the +wavefrontsize64 spam on targets
where that's the only option, but avoiding this seems to be more work
than I expected.
Roman Lebedev [Thu, 29 Dec 2022 22:43:20 +0000 (01:43 +0300)]
[NFC][Codegen][X86] zero_extend_vector_inreg.ll: add SSE4.2 runline
Roman Lebedev [Thu, 29 Dec 2022 15:02:02 +0000 (18:02 +0300)]
[DAGCombiner] Try to partition ISD::EXTRACT_VECTOR_ELT to accomodate it's ISD::BUILD_VECTOR users
This mainly cleans up a few patterns that are legalized by scalarization
from a wide-element vector, but then are further split apart to build
a more narrow-sized-element vector. In particular this happens in some
cases for illegal ISD::ZERO_EXTEND_VECTOR_INREG.
Given a ISD::EXTRACT_VECTOR_ELT, which is a glorified bit sequence extract,
recursively analyse all of it's users. and try to model themselves as
bit sequence extractions. If all of them agree on the new, narrower element
type, and all of them can be modelled as ISD::EXTRACT_VECTOR_ELT's of that
new element type, do that, but only if unmodelled users are ISD::BUILD_VECTOR.
Craig Topper [Thu, 29 Dec 2022 21:58:46 +0000 (13:58 -0800)]
[TargetLowering] Teach BuildUDIV to take advantage of leading zeros in the dividend.
If the dividend has leading zeros, we can use them to reduce the
size of the multiplier and avoid the fixup cases.
This patch is for scalars only, but we might be able to do this
for vectors in a follow up.
Differential Revision: https://reviews.llvm.org/D140750
Gulfem Savrun Yeniceri [Thu, 29 Dec 2022 20:37:57 +0000 (20:37 +0000)]
[instrprof] Fix issue in binary-ids-padding.test
https://reviews.llvm.org/D135929 caused a failure in
binary-ids-padding.test in big endian configurations:
https://lab.llvm.org/buildbot/#/builders/231/builds/6709
binary-ids-padding.test writes the profile in little-endian format.
This patch changes the raw profile reader to use getDataEndianness()
instead of llvm::support::endian::system_endianness() to fix the issue.
Mehdi Amini [Thu, 22 Dec 2022 19:53:45 +0000 (19:53 +0000)]
Apply clang-tidy fixes for performance-for-range-copy in Vectorization.cpp (NFC)
Mehdi Amini [Sat, 10 Dec 2022 14:16:17 +0000 (14:16 +0000)]
Apply clang-tidy fixes for readability-identifier-naming in TestDialect.cpp (NFC)
serge-sans-paille [Thu, 29 Dec 2022 15:24:58 +0000 (16:24 +0100)]
[clang] Use try_emplace instead of insert when getting new identifier
This is both less verbose and slightly faster, according to:
https://llvm-compile-time-tracker.com/compare.php?from=
d9ab3e82f30d646deff054230b0c742704a1cf26&to=
73405077ad913f634797ffc7a7bbb110ac9cae99&stat=instructions:u
No functional change intended :-)
Eugene Zhulenev [Wed, 28 Dec 2022 20:45:17 +0000 (12:45 -0800)]
[mlir] Add constBuilderCall to DictionaryAttr
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D140740
Aart Bik [Thu, 29 Dec 2022 18:55:01 +0000 (10:55 -0800)]
[mlir][sparse] layout fixes (NFC)
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D140761
Fangrui Song [Thu, 29 Dec 2022 20:16:20 +0000 (12:16 -0800)]
[ProfileData] Fix msan -fsanitize-memory-param-retval after D135929
test/tools/llvm-cov/load-multiple-objects.test calls
IndexedInstrProfReader::readBinaryIds with uninitialized BinaryIdsStart.
Markus Böck [Thu, 29 Dec 2022 19:47:29 +0000 (20:47 +0100)]
[llvm][AsmPrinter][NFC] Cleanup `GCMetadataPrinters` field
The field is currently `void*`, which was originlly chosen in 2010 to not need to include `DenseMap`. Since then, `DenseMap` has been included in the header file anyways, so there is no more need to for the indirection via `void*` and the cruft around it can be removed.
Differential Revision: https://reviews.llvm.org/D140758
Sanjay Patel [Thu, 29 Dec 2022 19:23:25 +0000 (14:23 -0500)]
[InstCombine] avoid miscompile in sinkNotIntoLogicalOp()
Fixes #59704
Sanjay Patel [Thu, 29 Dec 2022 19:19:15 +0000 (14:19 -0500)]
[InstCombine] add test for miscompile from sinkNotIntoLogicalOp(); NFC
issue #59704
Valery N Dmitriev [Thu, 29 Dec 2022 19:30:10 +0000 (11:30 -0800)]
[SLP] Fix debug print for cost in tryToVectorizeList - NFC.
Actual VF was confused with local variable named "VF".
Eduard Zingerman [Thu, 29 Dec 2022 18:29:44 +0000 (10:29 -0800)]
[BPF] Use SectionForGlobal() for section names computation in BTF
Use function TargetLoweringObjectFile::SectionForGlobal() to compute
section names for globals described in BTF_KIND_DATASEC records.
This fixes a discrepancy in section name computation between
BTFDebug::processGlobals and the rest of the LLVM pipeline.
Specifically, the following example illustrates the discrepancy
before this commit:
struct Foo {
int i;
} __attribute__((aligned(16)));
struct Foo foo = { 0 };
The initializer for 'foo' looks as follows:
%struct.Foo { i32 0, [12 x i8] undef }
TargetLoweringObjectFile::SectionForGlobal() classifies 'foo' as
a part of '.bss' section, while BTFDebug::processGlobals
classified it as a part of '.data' section because of the
following expression:
SecName = Global.getInitializer()->isZeroValue() ? ".bss" : ".data"
The isZeroValue() returns false because of the undef tail of the
initializer, while SectionForGlobal() allows such patterns in '.bss'.
Differential Revision: https://reviews.llvm.org/D140505
Valery N Dmitriev [Thu, 29 Dec 2022 19:02:36 +0000 (11:02 -0800)]
[SLP] A couple of minor improvements for slp graph view - NFC.
Show ScatterVectorize nodes in frames of blue color
and print vectorize tree indices.
Gulfem Savrun Yeniceri [Thu, 13 Oct 2022 00:50:10 +0000 (00:50 +0000)]
[profile] Add binary ids into indexed profiles
This patch adds support for including binary ids in an indexed profile.
It adds a new field into the header that points to the offset of the
binary id section. The binary id section consists of a size of the
section, and a list of binary ids (if they are present) that consist
of two parts: length and data.
This patch guarantees that indexed profile is backwards compatible
after adding binary ids.
Differential Revision: https://reviews.llvm.org/D135929
Fangrui Song [Thu, 29 Dec 2022 18:30:41 +0000 (10:30 -0800)]
[test] Fix dfsan/stack_trace.c
Craig Topper [Thu, 29 Dec 2022 17:35:34 +0000 (09:35 -0800)]
[Support] Fix what I think is an off by 1 bug in UnsignedDivisionByConstantInfo.
The code in Hacker's Delight says
`nc = -1 - (-d)%d;`
But we have
`NC = AllOnes - (AllOnes-D)%D`
The Hacker's Delight code is written for the LeadingZeros==0 case.
`AllOnes - D` is not the same as `-d` from Hacker's Delight.
This patch changes the code to
`NC = AllOnes - (AllOnes+1-D)%D`
This will increment AllOnes to 0 in the LeadingZeros==0 case. This
will make it equivalent to -D. I believe this is also correct for
LeadingZeros>0.
At least for i8, i16, and i32 the only divisor that changes is
((1 << (BitWidth-1)) | 1). Or 127 for i8, 32769 for i16, and
2147483649
for i32. These are all large enough that the quotient is 0 or 1 so
InstCombine replaces them with an icmp and zext before SelectionDAG.
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D140636
Peter Klausler [Mon, 19 Dec 2022 20:41:25 +0000 (12:41 -0800)]
[flang] Restore checking for some optional values before use
Recent commits (
2098ad7f00324ee0f2a6538f418a6f81dfdd2edb and
15a9a72ee68166c0cff3f036cacd3c82be66c729) replaced usage of "o.value()"
on optionals with "*o". Those optional values are expected to be
present -- but now, if it ever turns out that they're not,
compilation will proceed with garbage data rather than crashing
immediately (and more debuggably) with an uncaught exception.
Add asserts for presence to restore the previous level of safety.
(I could have revert these patches so as to resume used of .value()
but I didn't want to just have them get broken again.)
Differential Revision: https://reviews.llvm.org/D140340
Sanjay Patel [Thu, 29 Dec 2022 14:55:59 +0000 (09:55 -0500)]
[InstSimplify] fold exact divide to poison if it is known to not divide evenly
This is related to the discussion in D140665. I was looking over the demanded
bits implementation in IR and noticed that we just bail out of a potential
fold if a udiv is exact:
https://github.com/llvm/llvm-project/blob/
82be8a1d2b00f6e89096b86f670a8be894c7b9e6/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp#L799
Also, see tests added with
7f0c11509e8f.
Then, I saw that we could lose a fold to poison if we zap the exact with that
transform, so this patch tries to catch that as a preliminary step.
Alive2 proofs:
https://alive2.llvm.org/ce/z/zCjKM7
https://alive2.llvm.org/ce/z/-tz_RK (trailing zeros must be "less-than")
https://alive2.llvm.org/ce/z/c9CMsJ (general proof and specific example)
Differential Revision: https://reviews.llvm.org/D140733
Benjamin Kramer [Thu, 29 Dec 2022 15:05:33 +0000 (16:05 +0100)]
Detemplate llvm::EmitGEPOffset and move it into a cpp file. NFC.
Mike Hommey [Thu, 29 Dec 2022 14:47:13 +0000 (14:47 +0000)]
[MC] [llvm-ml] Add support for the extrn keyword
It is the same as the already supported `extern` keyword.
https://learn.microsoft.com/en-us/cpp/assembler/masm/extrn?view=msvc-170
Fixes: https://github.com/llvm/llvm-project/issues/59712
Reviewed By: epastor
Differential Revision: https://reviews.llvm.org/D140679
Sanjay Patel [Thu, 29 Dec 2022 14:19:53 +0000 (09:19 -0500)]
[InstSimplify] fix formatting and add bool function argument comments; NFC
Make existing code conform with proposed additions in D140733.
Hsiangkai Wang [Fri, 23 Dec 2022 03:05:10 +0000 (03:05 +0000)]
[RISCV] Add fmin/fmax scalar instructions to isAssociativeAndCommutative
Follow-up patch of D140530.
We can add FMIN, FMAX to isAssociativeAndCommutative to
increase instruction-level parallelism by the existing MachineCombiner
pass.
Differential Revision: https://reviews.llvm.org/D140602
Hsiangkai Wang [Thu, 22 Dec 2022 07:07:37 +0000 (07:07 +0000)]
[RISCV] Add integer scalar instructions to isAssociativeAndCommutative
Inspired by D138107.
We can add ADD, AND, OR, XOR, MUL, MIN[U]/MAX[U] to isAssociativeAndCommutative
to increase instruction-level parallelism by the existing MachineCombiner pass.
Differential Revision: https://reviews.llvm.org/D140530
Christian Sigg [Thu, 29 Dec 2022 11:02:58 +0000 (12:02 +0100)]
[mlir] NFC: work around gcc-aarch64 v8.3 compilation issue in getRegionBranchSuccessorOperands implementation.
https://reviews.llvm.org/rG25671db3d343 didn't quite do it because the underlying issue was that the specific compiler chokes on the second standard conversion sequence after the user-defined `MutableOperandRange::operator OperandRange() const` conversion (see https://en.cppreference.com/w/cpp/language/implicit_conversion).
Brad Smith [Thu, 29 Dec 2022 09:54:39 +0000 (04:54 -0500)]
[M68k] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Fixes #58974
Reviewed By: myhsu, glaubitz, 0x59616e
Differential Revision: https://reviews.llvm.org/D140695
Andrzej Warzynski [Thu, 29 Dec 2022 09:11:33 +0000 (09:11 +0000)]
[mlir] Add a newline character in the Linalg debug macro
Differential Revision: https://reviews.llvm.org/D140752
Chenbing Zheng [Thu, 29 Dec 2022 09:30:49 +0000 (17:30 +0800)]
[InstCombine] Fold (X << Z) / (X * Y) -> (1 << Z) / Y
Alive2: https://alive2.llvm.org/ce/z/CBJLeP
Jonas Hahnfeld [Thu, 29 Dec 2022 08:44:19 +0000 (09:44 +0100)]
Fix build of nvptx-arch with CLANG_LINK_CLANG_DYLIB
The function clang_target_link_libraries must only be used with real
Clang libraries; with CLANG_LINK_CLANG_DYLIB, it will instead link in
clang-cpp. We must use the standard CMake target_link_libraries for
the CUDA library.
Yeting Kuo [Tue, 27 Dec 2022 11:34:29 +0000 (03:34 -0800)]
[RISCV] Add Svpbmt extension support.
Spec of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/master/src/supervisor.tex#L2399
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D140692
Craig Topper [Thu, 29 Dec 2022 07:38:12 +0000 (23:38 -0800)]
[RISCV] Add SH1ADD/SH2ADD/SH3ADD to RISCVDAGToDAGISel::hasAllNBitUsers.
eopXD [Tue, 27 Dec 2022 09:42:31 +0000 (01:42 -0800)]
[Clang][RISCV] Use poison instead of undef
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D140687
Amir Ayupov [Thu, 29 Dec 2022 04:49:30 +0000 (20:49 -0800)]
[BOLT] Respect -function-order in lite mode
Process functions listed in -function-order file even in lite mode.
Reviewed By: #bolt, maksfb
Differential Revision: https://reviews.llvm.org/D140435
Craig Topper [Thu, 29 Dec 2022 03:43:18 +0000 (19:43 -0800)]
[RISCV] Prefer ADDI over ORI if the known bits are disjoint.
There is no compressed form of ORI but there is a compressed form
for ADDI.
This also works for XORI since DAGCombine will turn Xor with disjoint
bits in Or.
Note: The compressed forms require a simm6 immediate, but I'm doing
this for the full simm12 range.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D140674
Weining Lu [Thu, 29 Dec 2022 03:37:46 +0000 (11:37 +0800)]
[DFSan] Add `zeroext` attribute for callbacks with 8bit shadow variable arguments
Add `zeroext` attribute for below callbacks' first parameter
(8bit shadow variable arguments) to conform to many platforms'
ABI calling convention and some compiler behavior.
- __dfsan_load_callback
- __dfsan_store_callback
- __dfsan_cmp_callback
- __dfsan_conditional_callback
- __dfsan_conditional_callback_origin
- __dfsan_reaches_function_callback
- __dfsan_reaches_function_callback_origin
The type of these callbacks' first parameter is u8 (see the
definition of `dfsan_label`). First, many platforms' ABI
requires unsigned integer data types (except unsigned int)
are zero-extended when stored in general-purpose register.
Second, the problem is that compiler optimization may assume
the arguments are zero-extended and, if not, misbehave, e.g.
it uses an `i8` argument to index into a jump table. If the
argument has non-zero high bits, the output executable may
crash at run-time. So we need to add the `zeroext` attribute
when declaring and calling them.
Reviewed By: browneee, MaskRay
Differential Revision: https://reviews.llvm.org/D140689
Fangrui Song [Thu, 29 Dec 2022 02:08:29 +0000 (18:08 -0800)]
[XRay] Unsupport version<2 sled entry
For many features we expect clang and compiler-rt to have a version lock
relation, yet for XRaySledEntry we have kept version<2 compatibility for more
than 2 years (I migrated away the last user mips in 2020-09 (D87977)).
I think it's fair to call an end to version<2 now. This should discourage more
work on version<2 (e.g. D140725).
Reviewed By: ianlevesque
Differential Revision: https://reviews.llvm.org/D140739
Ben Shi [Thu, 29 Dec 2022 00:54:01 +0000 (08:54 +0800)]
Revert "[MLIR][Arith] Remove unused assertions"
This reverts commit
50e6c306b1cb03fe398aebc41d1bef5b6c9d9bb0.
Roman Lebedev [Wed, 28 Dec 2022 23:09:57 +0000 (02:09 +0300)]
[NFC][Codegen][X86] Add exhaustive-ish test coverage for ZERO_EXTEND_VECTOR_INREG
It should be possible to deduplicate AVX2 and AVX512F checklines,
but i'm not sure which combination of check prefixes would do that.
https://godbolt.org/z/sndT9n1nz
Jacques Pienaar [Thu, 29 Dec 2022 00:02:08 +0000 (16:02 -0800)]
[mlir][py] Add StrAttr convenience builder.
Fangrui Song [Wed, 28 Dec 2022 23:35:09 +0000 (15:35 -0800)]
[dfsan][test] Replace REQUIRES: x86_64-target-arch with lit.cfg.py check
Make it easier to support a new architecture.
Reviewed By: #sanitizers, vitalybuka
Differential Revision: https://reviews.llvm.org/D140744
Craig Topper [Wed, 28 Dec 2022 23:16:13 +0000 (15:16 -0800)]
[RISCV] Fix mistakes in fixed-vectors-vreductions-mask.ll command lines. NFC
There were 4 RUN lines, but only 2 of them were unique. I believe
we were trying to test LMUL=1 and LMUL=8 with riscv32 and riscv64.
But put riscv32 on both LMUL=1 lines and riscv64 on both LMUL=8 lines.
Craig Topper [Wed, 28 Dec 2022 21:39:33 +0000 (13:39 -0800)]
[RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers.
Brad Smith [Wed, 28 Dec 2022 22:51:52 +0000 (17:51 -0500)]
[Clang] Move AMDGPU IAS enabling to Generic_GCC::IsIntegratedAssemblerDefault, NFC
Reviewed By: scott.linder
Differential Revision: https://reviews.llvm.org/D140657
Mehdi Amini [Sat, 10 Dec 2022 12:53:27 +0000 (12:53 +0000)]
Apply clang-tidy fixes for readability-identifier-naming in InferTypeOpInterface.cpp (NFC)
Mehdi Amini [Sat, 10 Dec 2022 12:25:09 +0000 (12:25 +0000)]
Apply clang-tidy fixes for readability-simplify-boolean-expr in BufferizableOpInterfaceImpl.cpp (NFC)
Craig Topper [Wed, 28 Dec 2022 21:08:28 +0000 (13:08 -0800)]
[RISCV] Support SRLI in hasAllNBitUsers.
We can recursively look through SRLI if the shift amount is less
than the demanded bits. We can reduce the demanded bit count by
the shift amount and check the users of the SRLI.
Craig Topper [Wed, 28 Dec 2022 19:41:01 +0000 (11:41 -0800)]
[RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC
Move to RISCVInstrInfo since we need RISCVSubtarget now.
Instead of asking if only the lower 32 bits are used we can now
ask if the lower N bits are used. This will be needed by a future
patch.
Fangrui Song [Wed, 28 Dec 2022 20:48:13 +0000 (12:48 -0800)]
CodingStandards: restrict CamelCase variable names guideline to llvm/clang/clang-tools-extra/polly/bolt
See https://discourse.llvm.org/t/top-level-clang-tidy-options-and-variablename-suggestion-on-codingstandards/58783 ,
the CamelCase variable names guideline does not reflect the truth:
flang, libc, libclc, libcxx, libcxxabi, libunwind, lld, mlir, openmp,
and pstl use camelCase. lldb uses snake_case.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D140585
Uday Bondhugula [Wed, 28 Dec 2022 20:06:21 +0000 (01:36 +0530)]
[MLIR][Affine] Make fusion helper check method significantly more efficient
The `hasDependencePath` method in affine fusion is quite inefficient as
it does a DFS on the complete graph for what is a small part of the
checks before fusion can be performed. Make this efficient by using the
fact that the nodes involved are all at the top-level of the same block.
With this change, for large graphs with about 10,000 nodes, the check
runs in a few seconds instead of not terminating even in a few hours.
This is NFC from a functionality standpoint; it only leads to an
improvement in pass running time on large IR.
Differential Revision: https://reviews.llvm.org/D140522
Fangrui Song [Wed, 28 Dec 2022 20:03:09 +0000 (12:03 -0800)]
[XRay] Fix Hexagon sled version
D113638 emitted version 0 for XRaySledEntry, which will lead to an incorrect
address computation in the runtime.
While here, improve the test.
Shilei Tian [Wed, 28 Dec 2022 19:40:46 +0000 (14:40 -0500)]
[OpenMP][JIT] Fixed a couple of issues in the initial implementation of JIT
This patch fixes a couple of issues:
1. Instead of using `llvm_unreachable` for those base virtual functions, unknown
value will be returned. The previous method could cause runtime error for those
targets where the image is not compatible but JIT is not implemented.
2. Fixed the type in CMake that causes the `Target` CMake variable is undefined.
Reviewed By: ye-luo
Differential Revision: https://reviews.llvm.org/D140732
Craig Topper [Wed, 28 Dec 2022 19:07:31 +0000 (11:07 -0800)]
[RISCV] Add const qualifiers to some function arguments. NFC
Thomas Köppe [Wed, 28 Dec 2022 19:14:39 +0000 (11:14 -0800)]
[X86] Emit RIP-relative access to local function in PIC medium code model
Currently, the medium code model for x86_64 emits position-dependent relocations (R_X86_64_64) for local functions, regardless of PIC or no-PIC mode. (This means generically that code compiled with the medium model cannot be linked into a position-independent executable.)
Example:
```
static int g(int n) {
return 2 * n + 3;
}
void f(int(**p)(int)) {
*p = g;
}
```
This results in:
```
Disassembly of section .text:
0000000000000000 <f>:
0: 48 b8 00 00 00 00 00 00 00 00 movabs rax, 0x0
a: 48 89 07 mov qword ptr [rdi], rax
d: c3 ret
```
```
Relocation section '.rela.text' at offset 0xf0 contains 1 entries:
Offset Info Type Symbol's Value Symbol's Name + Addend
0000000000000002 0000000200000001 R_X86_64_64
0000000000000000 .text + 10
```
This patch changes the behaviour to unconditionally emit a RIP-relative access, both in PIC and non-PIC mode. This fixes PIC mode, and is perhaps an improvement in non-PIC mode, too, since it results in a shorter instruction. A 32-bit relocation should suffice since the medium memory model demands that all code fit within 2GiB.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D140593
Sanjay Patel [Wed, 28 Dec 2022 17:06:57 +0000 (12:06 -0500)]
[InstSimplify] add tests for div exact; NFC
Sanjay Patel [Wed, 28 Dec 2022 16:04:02 +0000 (11:04 -0500)]
[InstCombine] add tests for udiv-by-constant demanded bits; NFC
Mark de Wever [Wed, 7 Dec 2022 16:43:59 +0000 (17:43 +0100)]
[libc++][CI] Improves clang-(tidy|query) selection.
Hardcode the version of the tools used in the test feature script
instead of the tests. By changing the hard-coded location it's
easier to make the location flexible in the future.
Drive-by change
- The minimum required version for clang-query is now 15, which matches
our future idea as outlined in the Dockerfile.
- The minimum required version for clang-tidy is now 16, which enables
the new clang-tidy ADL plugin. This plugin is disabled for C++03
due to false positives when using `noexcept`, which is not an operator
in C++03.
Reviewed By: ldionne, #libc
Differential Revision: https://reviews.llvm.org/D139545
Fangrui Song [Wed, 28 Dec 2022 18:46:45 +0000 (10:46 -0800)]
[lld] Fix iwyu problems after
83d59e05b201760e3f364ff6316301d347cbad95
The commit transitively includes lld/include/lld/Common/ErrorHandler.h into
lld/include/lld/Common/Driver.h, which is not intended.
Pavel Kopyl [Wed, 28 Dec 2022 15:17:07 +0000 (18:17 +0300)]
[NVPTX] Emit .noreturn directive
Differential Revision: https://reviews.llvm.org/D140238
Owen Anderson [Sat, 24 Dec 2022 04:22:36 +0000 (21:22 -0700)]
Handle simple diamond CFG hoisting in DivRemPairs.
Previous we only handled triangle CFGs. This patch expands that
to support diamonds, where the div and rem appear in the then/else
sides of a condition. In that case, we can hoist the div into the
shared predecessor.
This could be generalized further to use nearest common ancestors,
but some of the conditions for hoisting would then require
post-dominator information.
Reviewed By: nikic, lebedev.ri
Differential Revision: https://reviews.llvm.org/D140647
Pavel Iliin [Wed, 28 Dec 2022 16:55:16 +0000 (16:55 +0000)]
[AArch64] Fix AArch64TargetParser.def includes for standalone builds.
Mark de Wever [Wed, 28 Dec 2022 17:10:39 +0000 (18:10 +0100)]
[NFC][libc++] Replaces tabs by spaces.
Jordan Rupprecht [Wed, 28 Dec 2022 16:43:04 +0000 (08:43 -0800)]
[test] Exclude //llvm/unittests:llvm_exegesis_tests due to buildkite environment.
Buildkite does not allow user perf monitoring and fails: https://buildkite.com/llvm-project/upstream-bazel/builds/49579.
```
[ RUN ] PerfHelperTest.FunctionalTest
Unable to open event. ERRNO: Permission denied. Make sure your kernel allows user space perf monitoring.
You may want to try:
$ sudo sh -c 'echo -1 > /proc/sys/kernel/perf_event_paranoid'
llvm_exegesis_tests: external/llvm-project/llvm/tools/llvm-exegesis/lib/PerfHelper.cpp:111: llvm::exegesis::pfm::Counter::Counter(llvm::exegesis::pfm::PerfEvent &&): Assertion `FileDescriptor != -1 && "Unable to open event"' failed.
```
bixia1 [Tue, 27 Dec 2022 20:28:29 +0000 (12:28 -0800)]
[mlir][sparse] Use DLT in the mangled function names for insertion.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D140484
Jordan Rupprecht [Wed, 28 Dec 2022 16:13:20 +0000 (08:13 -0800)]
[bazel] Restore libpfm as a conditional dependency for exegesis.
We used to have `pfm` built into exegesis, although since it's an external dependency we marked it as a manual target. Because of this we didn't have buildbot coverage and so we removed it in D134510 after we had a few breakages that weren't caught. This adds it back, but with three possible states similar to the story with `mpfr`, i.e. it can either be disabled, built from external sources (git/make), or use whatever `-lpfm` is installed on the system.
This change is modeled after D119547. Like that patch, the default is off (matching the status quo), but unlike that patch we don't enable it for CI because IIRC we don't have the package installed there, and building from source might be expensive. We could enable it later either after installing it on buildbot machines or by measuring build cost and deeming it OK.
Reviewed By: GMNGeoffrey
Differential Revision: https://reviews.llvm.org/D138470
Mark de Wever [Wed, 28 Dec 2022 16:04:43 +0000 (17:04 +0100)]
[NFC][libc++] Fixes ADL calls.
Sanjay Patel [Wed, 28 Dec 2022 15:28:23 +0000 (10:28 -0500)]
[InstCombine] preserve signbit semantics of NAN with fold to fabs
As discussed in issue #59279, we want fneg/fabs to conform to the
IEEE-754 spec for signbit operations - quoting from section 5.5.1
of IEEE-754-2008:
"negate(x) copies a floating-point operand x to a destination in
the same format, reversing the sign bit"
"abs(x) copies a floating-point operand x to a destination in the
same format, setting the sign bit to 0 (positive)"
"The operations treat floating-point numbers and NaNs alike."
So we gate this transform with "nnan" in addition to "nsz":
(X > 0.0) ? X : -X --> fabs(X)
Without that restriction, we could have for example:
(+NaN > 0.0) ? +NaN : -NaN --> -NaN
(because an ordered compare with NaN is always false)
That would be different than fabs(+NaN) --> +NaN.
More fabs/fneg patterns demonstrated here:
https://godbolt.org/z/h8ecc659d
(without any FMF, these are correct independently of this patch -
no fabs should be created)
The code change is a one-liner, but we have lots of tests diffs
because there are many variations of the basic pattern.
Differential Revision: https://reviews.llvm.org/D139785
Alexey Bataev [Wed, 21 Dec 2022 21:44:30 +0000 (13:44 -0800)]
[SLP]Use ShuffleInstructionBuilder for vector shrinking.
We can use ShuffleInstructionBuilder now for shrinking shuffle emission.
It allows to remove extra shuffle from the emitted code and reuse
original vector.
Part of D110978
Differential Revision: https://reviews.llvm.org/D140499
Roman Lebedev [Wed, 28 Dec 2022 13:56:20 +0000 (16:56 +0300)]
[NFC][exegesis] By default, don't dump objects to disk
It's a strictly-developer feature, which is useless most of the time.
Fixes https://github.com/llvm/llvm-project/issues/59082
Reviewed By: RKSimon, gchatelet
Differential Revision: https://reviews.llvm.org/D140700
v1nh1shungry [Wed, 28 Dec 2022 12:34:41 +0000 (13:34 +0100)]
[clangd] Fix action `RemoveUsingNamespace` for inline namespace
Existing version ignores symbols declared in an inline namespace `ns`
when removing `using namespace ns`
Reviewed By: tom-anders
Differential Revision: https://reviews.llvm.org/D138028
Christian Sigg [Wed, 28 Dec 2022 11:08:37 +0000 (12:08 +0100)]
[mlir] NFC: work around gcc-aarch64 v8.3 compilation issue in getRegionBranchSuccessorOperands implementation.
Timm Bäder [Wed, 28 Dec 2022 11:08:29 +0000 (12:08 +0100)]
[clang][Interp][NFC] Fix typo in comment
Hsiangkai Wang [Wed, 28 Dec 2022 03:42:53 +0000 (03:42 +0000)]
[RISCV][NFC] Remove redundant setOperationAction.
ISD::INSERT_VECTOR_ELT is already set above.
Differential Revision: https://reviews.llvm.org/D140716
Freddy Ye [Wed, 28 Dec 2022 08:44:54 +0000 (16:44 +0800)]
[X86] Rename CMPCCXADD intrinsics.
"__cmpccxadd_epi*" -> "_cmpccxadd_epi*"
This is to align with other intrinsics to follow single leading "_" style. Gcc
and intrinsic guide website will also apply this change.
Reviewed By: LuoYuanke, skan
Differential Revision: https://reviews.llvm.org/D140281
Jie Fu [Wed, 28 Dec 2022 08:32:44 +0000 (16:32 +0800)]
[RISCV] Fix typos in RISCVUsage.rst
Fix typos `riscv-toolchai-convention` --> `riscv-toolchain-convention`
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D140717
Qiu Chaofan [Wed, 28 Dec 2022 06:23:32 +0000 (14:23 +0800)]
Fix failure of ldst-16-byte.mir
Qiu Chaofan [Wed, 28 Dec 2022 06:06:01 +0000 (14:06 +0800)]
[PowerPC] Enable track-subreg-liveness by default
This option helps some MMA related cases to reduce unnecessary copies.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D108902
Jacques Pienaar [Wed, 28 Dec 2022 05:56:58 +0000 (21:56 -0800)]
[mlir][py] Fix negative cached value in attribute builder
Previously this was incorrectly assigning py::none to where function was
expected which resulted in failure if one used a non-attribute for
attribute without registered builder.
Yonghong Song [Wed, 28 Dec 2022 03:57:30 +0000 (19:57 -0800)]
[MC][BPF] Add bpf guard for MC test data-section-prefix.ll
Commit
f27c4903c43b ("MC: Add .data. and .rodata. prefixes to MCContext
section classification") added a test assuming bpf target. But it
is possible bpf target is not configured in the clang build.
Let us add explicit bpf-target requirement for the test
so the test can be ingored properly for clang build without enabling
bpf target.
jacquesguan [Tue, 27 Dec 2022 04:45:06 +0000 (12:45 +0800)]
[mlir][vector] Fix typo, NFC.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D140681
Shilei Tian [Wed, 28 Dec 2022 03:18:57 +0000 (22:18 -0500)]
[OpenMP] Introduce basic JIT support to OpenMP target offloading
This patch adds the basic JIT support for OpenMP. Currently it only works on Nvidia GPUs.
The support for AMDGPU can be extended easily by just implementing three interface functions. However, the infrastructure requires a small extra extension (add a pre process hook) to support portability for AMDGPU because the AMDGPU backend reads target features of functions. https://github.com/shiltian/llvm-project/commit/
02bc7effccc6ff2f5ab3fe5218336094c0485766#diff-321c2038035972ad4994ff9d85b29950ba72c08a79891db5048b8f5d46915314R432 shows how it roughly works.
As for the test, even though I added the corresponding code in CMake files, the test still cannot be triggered because some code is missing in the new plugin CMake file, which has nothing to do with this patch. It will be fixed later.
In order to enable JIT mode, when compiling, `-foffload-lto` is needed, and when linking, `-foffload-lto -Wl,--embed-bitcode` is needed. That implies that, LTO is required to enable JIT mode.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D139287
Shilei Tian [Wed, 28 Dec 2022 02:52:07 +0000 (21:52 -0500)]
Revert "[OpenMP] Introduce basic JIT support to OpenMP target offloading"
This reverts commit
58906e4901ec5b7ed230d7fa96123654f6a974af because it breaks AMD's buildbot.
Michael Maitland [Fri, 16 Dec 2022 21:44:52 +0000 (13:44 -0800)]
[LV] Remove duplicate name set of vector header basic block. NFC
The preheader was named explicitly in
256c6b0ba14e8a7ab6373b61b7193ea8c0a3651c
which makes setting the name in prior commit
95b2aa511eea1f31e183a2a3aed4d2aa852d089c
unnecessary.
Differential Revision: https://reviews.llvm.org/D140246
Hui Li [Wed, 28 Dec 2022 01:12:09 +0000 (09:12 +0800)]
[LLDB][LoongArch] Optimize EmulateInstructionLoongArch related code
This is a code optimization patch that does not include feature additions
or deletions.
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D140616
Aart Bik [Tue, 27 Dec 2022 23:47:02 +0000 (15:47 -0800)]
[mlir][sparse] move emitter ownership into environment
last bits and pieces of the environment refactoring
Reviewed By: Peiming
Differential Revision: https://reviews.llvm.org/D140709
Florian Hahn [Wed, 28 Dec 2022 00:09:52 +0000 (00:09 +0000)]
[SCEV] Properly clean up duplicated FoldCacheUser ID entries.
The current code did not properly handled duplicated FoldCacheUser ID
entries when overwriting an existing entry in the FoldCache.
This triggered verification failures reported by @uabelho and #59721.
The patch fixes that by removing stale IDs when overwriting an existing
entry in the cache.
Fixes #59721.
Shilei Tian [Wed, 28 Dec 2022 00:07:24 +0000 (19:07 -0500)]
[OpenMP] Introduce basic JIT support to OpenMP target offloading
This patch adds the basic JIT support for OpenMP. Currently it only works on Nvidia GPUs.
The support for AMDGPU can be extended easily by just implementing three interface functions. However, the infrastructure requires a small extra extension (add a pre process hook) to support portability for AMDGPU because the AMDGPU backend reads target features of functions. https://github.com/shiltian/llvm-project/commit/
02bc7effccc6ff2f5ab3fe5218336094c0485766#diff-321c2038035972ad4994ff9d85b29950ba72c08a79891db5048b8f5d46915314R432 shows how it roughly works.
As for the test, even though I added the corresponding code in CMake files, the test still cannot be triggered because some code is missing in the new plugin CMake file, which has nothing to do with this patch. It will be fixed later.
In order to enable JIT mode, when compiling, `-foffload-lto` is needed, and when linking, `-foffload-lto -Wl,--embed-bitcode` is needed. That implies that, LTO is required to enable JIT mode.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D139287
Dave Marchevsky [Tue, 27 Dec 2022 23:56:47 +0000 (15:56 -0800)]
MC: Add .data. and .rodata. prefixes to MCContext section classification
Commit
463da422f019 ("MC: make section classification a bit more
thorough") changed MCContext::getELFSection section classification logic
to default to SectionKind::getText (previously default was
SectionKind::getReadOnly) and added some matching based on section name
to determine internal section classification.
The BPF runtime implements global variables using 'BPF map'
datastructures, specifically the arraymap BPF map type. Global variables
in a section are placed in a single arraymap value at predictable byte
offsets. Variables in different sections are placed in separate
arraymaps, so in this example:
#define SEC(name) __attribute__((section(name)))
SEC(".data.A") u32 one;
SEC(".data.A") u32 two;
SEC(".data.B") u32 three;
SEC(".data.B") u32 four;
variables one and two would correspond to some byte offsets (probably 0
and 4) in one arraymap, while three and four would be in a separate
arraymap. Variables of a bpf_spin_lock type are considered to protect
next-generation BPF datastructure types in the same arraymap value and
there can only be a single bpf_spin_lock variable per arraymap value -
and thus per section.
As a result it's necessary to keep bpf_spin_locks and the datastructures
they guard in separate data sections. Before the aforementioned commit,
a section whose name starts with ".data." - like ".data.A" - would be
classified as SectionKind::getReadOnly, whereas after it is
SectionKind::getText. If 4-byte padding is required in such a section due to
alignment of some symbol within it, classification of the section as
SectionKind::getText will result in compilation of those variables to
BPF backend failing with an error like "unable to write nop sequence of
4 bytes". This is due to nop instruction emitted in
BPFAsmBackend::writeNopData being 8 bytes, so the function fails since
it cannot emit a 4-byte nop instruction.
Let's follow the pattern of matching section names starting with ".bss."
and ".tbss." prefixes resulting in proper classification of the section
as data by adding similar matches for ".data." and ".rodata." prefixes.
This will bring padding behavior for these sections back to what it was
before that commit and fix the crash.
Differential Revision: https://reviews.llvm.org/D138477
Weverything [Tue, 27 Dec 2022 23:23:28 +0000 (15:23 -0800)]
[libc++] Remove self-include from header file NFC
Florian Hahn [Tue, 27 Dec 2022 23:24:21 +0000 (23:24 +0000)]
[IVUsers] Precommit test for zext SCEV invalidation issue.
Test case for issue reported by @uabelho and #59721
Florian Hahn [Tue, 27 Dec 2022 23:01:40 +0000 (23:01 +0000)]
[LV] Convert a few tests to use opaque pointers (NFC).
Pavel Iliin [Wed, 21 Dec 2022 11:29:53 +0000 (11:29 +0000)]
Reland "[AArch64] FMV support and necessary target features dependencies."
This relands commits
e43924a75145d2f9e722f74b673145c3e62bfd07,
a43f36142c501e2d3f4797ef938db4e0c5e0eeec,
bf94eac6a3f7c5cd8941956d44c15524fa3751bd with MSan buildbot
https://lab.llvm.org/buildbot/#/builders/5/builds/30139
use-of-uninitialized-value errors fixed.
Differential Revision: https://reviews.llvm.org/D127812