Chia-I Wu [Mon, 15 Jun 2015 04:01:29 +0000 (12:01 +0800)]
ilo: add ilo_state_sample_pattern
Move sample pattern initialization from ilo_render to
ilo_state_sample_pattern.
Chia-I Wu [Mon, 15 Jun 2015 03:57:10 +0000 (11:57 +0800)]
ilo: add 3DSTATE_AA_LINE_PARAMETERS to ilo_state_raster
Utilize ilo_state_raster to avoid redundant state change.
Marek Olšák [Sun, 10 May 2015 18:35:15 +0000 (20:35 +0200)]
gallium/util: add util_last_bit64
This will be needed by radeonsi.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Marek Olšák [Sat, 6 Jun 2015 12:12:34 +0000 (14:12 +0200)]
glsl: fix "tesselation" typo
Trivial.
Marek Olšák [Fri, 5 Jun 2015 17:09:21 +0000 (19:09 +0200)]
r600g: handle TGSI input/output array declarations correctly
Most of this code could be removed if r600g used tgsi_shader_info.
Chia-I Wu [Wed, 10 Jun 2015 23:36:28 +0000 (07:36 +0800)]
ilo: merge ilo_state_3d*.[ch] to ilo_state.[ch]
With most code replaced to ilo_state_*, what was left did not belong there
anymore.
Chia-I Wu [Fri, 12 Jun 2015 07:08:02 +0000 (15:08 +0800)]
ilo: add ilo_state_ps to ilo_shader_cso
Chia-I Wu [Fri, 12 Jun 2015 06:47:02 +0000 (14:47 +0800)]
ilo: add ilo_state_{vs,hs,ds,gs} to ilo_shader_cso
Chia-I Wu [Tue, 2 Jun 2015 15:09:53 +0000 (23:09 +0800)]
ilo: embed ilo_state_sbe in ilo_shader
Chia-I Wu [Tue, 2 Jun 2015 06:57:48 +0000 (14:57 +0800)]
ilo: embed ilo_state_vf in ilo_ve_state
Chia-I Wu [Thu, 28 May 2015 05:43:56 +0000 (13:43 +0800)]
ilo: embed ilo_state_urb in ilo_state_vector
Chia-I Wu [Fri, 29 May 2015 07:25:13 +0000 (15:25 +0800)]
ilo: embed ilo_state_sol in ilo_shader
Chia-I Wu [Mon, 11 May 2015 11:48:52 +0000 (19:48 +0800)]
ilo: embed ilo_state_cc in ilo_blend_state
Chia-I Wu [Fri, 5 Jun 2015 02:23:24 +0000 (10:23 +0800)]
ilo: embed ilo_state_raster in ilo_rasterizer_state
Chia-I Wu [Sun, 17 May 2015 16:00:37 +0000 (00:00 +0800)]
ilo: embed ilo_state_viewport in ilo_viewport_state
Chia-I Wu [Thu, 21 May 2015 09:18:37 +0000 (17:18 +0800)]
ilo: replace ilo_sampler_cso with ilo_state_sampler
Chia-I Wu [Wed, 20 May 2015 13:44:30 +0000 (21:44 +0800)]
ilo: replace ilo_view_surface with ilo_state_surface
Chia-I Wu [Mon, 18 May 2015 15:32:10 +0000 (23:32 +0800)]
ilo: replace ilo_zs_surface with ilo_state_zs
Chia-I Wu [Fri, 12 Jun 2015 06:56:56 +0000 (14:56 +0800)]
ilo: add ilo_state_ps
We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs,ps}.
Chia-I Wu [Fri, 29 May 2015 16:58:51 +0000 (00:58 +0800)]
ilo: add ilo_state_{vs,hs,ds,gs}
We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs} and ps
payload.
Chia-I Wu [Fri, 12 Jun 2015 06:02:37 +0000 (14:02 +0800)]
ilo: add ilo_state_sbe
We want to replace ilo_kernel_routing with ilo_state_sbe.
Chia-I Wu [Sat, 30 May 2015 16:00:49 +0000 (00:00 +0800)]
ilo: add ilo_state_vf
We want to replace ilo_ve_state with ilo_state_vf.
Chia-I Wu [Thu, 28 May 2015 05:21:02 +0000 (13:21 +0800)]
ilo: add ilo_state_urb
Chia-I Wu [Fri, 29 May 2015 05:08:18 +0000 (13:08 +0800)]
ilo: add ilo_state_sol
Chia-I Wu [Mon, 11 May 2015 06:23:49 +0000 (14:23 +0800)]
ilo: add ilo_state_cc
We want to replace ilo_dsa_state and ilo_blend_state with ilo_state_cc.
Chia-I Wu [Sun, 10 May 2015 05:52:21 +0000 (13:52 +0800)]
ilo: add ilo_state_raster
We want to replace ilo_rasterizer_state with ilo_state_raster.
Chia-I Wu [Tue, 12 May 2015 15:43:50 +0000 (23:43 +0800)]
ilo: add ilo_state_viewport
We want to replace ilo_viewport_cso and ilo_scissor_state with
ilo_state_viewport.
Chia-I Wu [Wed, 13 May 2015 05:10:54 +0000 (13:10 +0800)]
ilo: add ilo_state_sampler
We want to replace ilo_sampler_cso with ilo_state_sampler.
Chia-I Wu [Thu, 14 May 2015 01:46:42 +0000 (09:46 +0800)]
ilo: add ilo_state_surface
We want to replace ilo_view_surface with ilo_state_surface.
Chia-I Wu [Sat, 16 May 2015 00:27:24 +0000 (08:27 +0800)]
ilo: add ilo_state_zs
We want to replace ilo_zs_surface with ilo_state_zs. One noteworthy
difference is that ilo_state_zs always aligns level 0 to 8x4 when HiZ is
enabled. HiZ will not be enabled for 1D surfaces as a result.
Chia-I Wu [Sat, 9 May 2015 13:39:34 +0000 (21:39 +0800)]
ilo: update genhw headers
Generate these new enums
enum gen_reorder_mode;
enum gen_clip_mode;
enum gen_front_winding;
enum gen_fill_mode;
enum gen_cull_mode;
enum gen_pixel_location;
enum gen_sample_count;
enum gen_inputattr_select;
enum gen_msrast_mode;
enum gen_prefilter_op;
Correct the type of GEN6_SAMPLER_DW0_BASE_LOD. Rename gen_logicop_function,
gen_sampler_mip_filter, gen_sampler_map_filter, gen_sampler_aniso_ratio, and
others.
Chia-I Wu [Fri, 22 May 2015 06:21:22 +0000 (14:21 +0800)]
ilo: add ilo_image_disable_aux()
When aux bo allocation fails, ilo_image_disable_aux() should be called to
disable aux buffer.
Chia-I Wu [Tue, 26 May 2015 07:46:44 +0000 (15:46 +0800)]
ilo: add array_size and level_count to ilo_image
We will use them for bound checking.
Chia-I Wu [Sun, 17 May 2015 03:55:05 +0000 (11:55 +0800)]
ilo: add pipe_texture_target to ilo_image
Save the target in ilo_image instead of passing it around.
Chia-I Wu [Fri, 15 May 2015 02:39:05 +0000 (10:39 +0800)]
ilo: fix "Render Cache Read Write Mode"
It needs be set to R/W only when using certain messages via DP render cache.
Since we only use RT wrties with the render cache, we never need to set it.
Chia-I Wu [Thu, 21 May 2015 08:30:03 +0000 (16:30 +0800)]
ilo: avoid resource owning in core
It is up to the users whether to reference count the BOs or not.
Chia-I Wu [Fri, 22 May 2015 05:49:20 +0000 (13:49 +0800)]
ilo: assert core objects are zero-initialized
Core objects are usually embedded inside calloc()'ed objects and we expect
them to be zero-initialized.
Tom Stellard [Thu, 11 Jun 2015 15:42:25 +0000 (15:42 +0000)]
radeon/llvm: Handle LLVM backend rename from R600 to AMDGPU
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tom Stellard [Wed, 27 May 2015 23:51:43 +0000 (16:51 -0700)]
gallivm: Only build lp_profile() body when PROFILE is defined
The only use of lp_profile() is wrapped in #if defined(PROFILE),
so there is no reason to build it unless this macro is defined.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Timothy Arceri [Wed, 10 Jun 2015 08:35:08 +0000 (18:35 +1000)]
glsl: fix compile error message
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ben Widawsky [Thu, 14 May 2015 16:28:37 +0000 (09:28 -0700)]
i965/gen8+: Add aux buffer alignment assertions
This helped find the incorrect HALIGN values from the previous patches.
v2: Add PRM references for assertions (Chad)
v3: Remove duplicated part of commit message, assert num_samples > 1, instead of
num_samples > 0. (Chad)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Ben Widawsky [Fri, 22 May 2015 22:57:37 +0000 (15:57 -0700)]
i965/gen9: Set HALIGN_16 for all aux buffers
Just like the previous patch, but for the GEN9 constraints.
v2:
bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address
this, move the check to where the gen8 check is, and do the appropriate
conditional there.
v3:
Remove stray whitespace introduced in v2 (Chad)
Rework comment to show AUX_CCS and AUX_MCS specifically. Remove misworded part
about gen7 (Chad).
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (v1)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Reviewed-by: Chad Versace <chad.versace@intel.com>
Ben Widawsky [Thu, 14 May 2015 16:30:02 +0000 (09:30 -0700)]
i965/gen8: Correct HALIGN for AUX surfaces
This restriction was attempted in this commit:
commit
47053464630888f819ef8cc44278f1a1220159b9
Author: Anuj Phogat <anuj.phogat@gmail.com>
Date: Fri Feb 13 11:21:21 2015 -0800
i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT
However, the commit itself doesn't achieve the desired goal as determined by the
asserts which the next patch adds. mcs_mt is NULL (never set) we're in the
process of allocating the mcs_mt miptree when we get to this function. I didn't
check, but perhaps this would work with blorp, however, meta clears allocate the
miptree structure (which AFAICT needs the alignment also) way before it
allocates using meta clears where the renderbuffer is allocated way before the
aux buffer.
The restriction is referenced in a few places, but the most concise one [IMO]
from the spec is for Gen9. Gen8 loosens the restriction in that it only requires
this for non-msrt surface.
When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must
be used.
With the code before the miptree layout flag rework (patches preceding this),
accomplishing this workaround is very difficult.
v2:
bugfix: Don't set HALIGN16 for gens before 8 (Chad)
v3:
non-trivial rebase
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Ben Widawsky [Fri, 22 May 2015 05:47:37 +0000 (22:47 -0700)]
i965: Extract tiling from fast clear decision
There are several constraints when determining if one can fast clear a surface.
Some of these are alignment, pixel density, tiling formats, and others that vary
by generation. The helper function which exists today does a suitable job,
however it conflates "BO properties" with "Miptree properties" when using
tiling. I consider the former to be attributes of the physical surface, things
which are determined through BO allocation, and the latter being attributes
which are derived from the API, and having nothing to do with the underlying
surface.
Determining tiling properties and creating miptrees are related operations
(when we allocate a BO for a miptree) with some disjoint constraints. By
extracting the decisions into two distinct choices (tiling vs. miptree
properties), we gain flexibility throughout the code to make determinations
about when we can or cannot fast clear strictly on the miptree.
To signify this change, I've also renamed the function to indicate it is a
distinction made on the miptree. I am torn as to whether or not it was a good
idea to remove "non_msrt" since it's a really nice thing for grep.
v2:
Reword some comments (Chad)
intel_is_non_msrt_mcs_tile_supported->intel_tiling_supports_non_msrt_mcs (Chad)
Make full if ladder for gens in above function (Chad)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Ben Widawsky [Sat, 23 May 2015 01:13:24 +0000 (18:13 -0700)]
i965/gen9: Only allow Y-Tiled MCS buffers
For GEN9, much of the logic to use X-Tiled buffers has been stripped out. It is
still supported in some places, but it's never desirable. Unfortunately we don't
yet have the ability to have Y-Tiled scanout (see:
http://patchwork.freedesktop.org/patch/46984/),
NOTE: This patch shouldn't actually do anything since SKL doesn't yet use fast
clears (they are disabled because they are causing regressions). THerefore, the
only case we can get to this function on SKL is by way of
intel_update_winsys_renderbuffer_miptree.
v2: Update commit message to be more clear that the NOTE is for SKL only.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ben Widawsky [Thu, 21 May 2015 23:04:43 +0000 (16:04 -0700)]
i965: Consolidate certain miptree params to flags
I think pretty much everyone agrees that having more than a single bool as a
function argument is bordering on a bad idea. What sucks about the current
code is in several instances it's necessary to propagate these boolean
selections down to lower layers of the code. This requires plumbing (mechanical,
but still churn) pretty much all of the miptree functions each time. By
introducing the flags paramater, it is possible to add miptree constraints very
easily.
The use of this, as is already the case, is sometimes we have some information
at the time we create the miptree that needs to be known all the way at the
lowest levels of the create/allocation, disable_aux_buffers is currently one
such example. There will be another example coming up in a few patches.
v2:
Tab fix. (Ben)
Long line fixes (Topi)
Use anonymous enum instead of #define for layout flags (Chad)
Use 'X != 0' instead of !!X (everyone except Chad)
v3:
Some non-trivial conflict resolution on top of Anuj's patches.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: "Pohjolainen, Topi" <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Timothy Arceri [Wed, 10 Jun 2015 09:40:07 +0000 (19:40 +1000)]
glsl: enforce restriction on AoA interface blocks in GLSL ES 3.10
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Timothy Arceri [Fri, 12 Jun 2015 06:03:56 +0000 (16:03 +1000)]
glsl: enforce fragment shader input restrictions in GLSL ES 3.10
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Timothy Arceri [Wed, 10 Jun 2015 08:46:22 +0000 (18:46 +1000)]
glsl: enforce output variable rules for GLSL ES 3.10
Some rules are already applied this just adds the missing ones.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Jordan Justen [Fri, 13 Mar 2015 19:03:52 +0000 (12:03 -0700)]
i965/nir: Support barrier intrinsic function
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Jordan Justen [Wed, 27 Aug 2014 18:32:08 +0000 (11:32 -0700)]
i965/fs: Implement support for ir_barrier
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Jordan Justen [Wed, 5 Nov 2014 02:11:37 +0000 (18:11 -0800)]
i965: Add brw_barrier to emit a Gateway Barrier SEND
This will be used to implement the Gateway Barrier SEND needed to implement
the barrier function.
v2:
* notify => gateway_notify (Ken)
* combine short lines of brw_barrier proto/decl (mattst88)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Jordan Justen [Wed, 5 Nov 2014 02:05:04 +0000 (18:05 -0800)]
i965: Add brw_WAIT to emit wait instruction
This will be used to implement the barrier function.
v2:
* Rename to brw_WAIT (mattst88)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jordan Justen [Wed, 5 Nov 2014 01:52:42 +0000 (17:52 -0800)]
i965: Add notification register
This will be used by the wait instruction when implementing the barrier()
function.
v2:
* Changes suggested by mattst88
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jordan Justen [Wed, 5 Nov 2014 01:51:19 +0000 (17:51 -0800)]
i965: Disassemble Gateway SEND messages
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Jordan Justen [Wed, 5 Nov 2014 02:07:52 +0000 (18:07 -0800)]
i965/inst: Add gateway_notify and gateway_subfuncid fields
These fields will be used when emitting a send for the barrier function.
Reference: IVB PRM Volume 4, Part 2, Section 1.1.1 Message Descriptor
v2:
* notify => gateway_notify (Ken)
* define bits for gen4-gen6 (bwidawsk, Ken)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 5 Nov 2014 01:48:44 +0000 (17:48 -0800)]
i965: Add GATEWAY_SFID definitions
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Jordan Justen [Fri, 13 Mar 2015 19:03:15 +0000 (12:03 -0700)]
nir: Add barrier intrinsic function
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Chris Forbes [Sun, 7 Sep 2014 07:29:50 +0000 (19:29 +1200)]
glsl: Add builtin barrier() function
[jordan.l.justen@intel.com: Add CS support]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Forbes [Sun, 7 Sep 2014 07:24:15 +0000 (19:24 +1200)]
glsl: Add ir node for barrier
v2:
* Changes suggested by mattst88
[jordan.l.justen@intel.com: Add nir support]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Jordan Justen [Thu, 11 Jun 2015 16:44:54 +0000 (09:44 -0700)]
i965/cs: Use exec all for CS terminate
This prevents an assertion from being hit with SIMD16:
Assertion `inst->exec_size == dispatch_width() || force_writemask_all' failed.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Chad Versace [Wed, 10 Jun 2015 16:50:47 +0000 (09:50 -0700)]
i965/fs: Fix unused variable warning
Annotate offset_components with attribute 'unused'.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Wed, 10 Jun 2015 22:50:21 +0000 (23:50 +0100)]
vc4: automake: enable subdir-objects
Silence the warnings about the future incompatibility with automake 2.0
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Erik Faye-Lund [Wed, 10 Jun 2015 22:35:04 +0000 (23:35 +0100)]
mesa: build xmlconfig to a separate static library
As we use the file from both the dri modules and loader, we end up with
multiple definition of the symbols provided in our gallium dri modules.
Additionally we compile the file twice.
Resolve both issues, effectively enabling the build on toolchains which
don't support -Wl,--allow-multiple-definition.
v2: [Emil Velikov]
- Fix the Scons/Android build.
- Resolve libgbm build issues (bring back the missing -lm)
Cc: Julien Isorce <j.isorce@samsung.com>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90310
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90905
Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Wed, 15 Apr 2015 13:34:00 +0000 (14:34 +0100)]
targets/nine: link against libnir/libglsl_util
Based on commit
101142c4010(xa: support for drivers which use NIR)
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90466
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Wed, 15 Apr 2015 11:46:30 +0000 (12:46 +0100)]
pipe-loader: add libnir and libglsl_util to the link
Based on commit
101142c4010(xa: support for drivers which use NIR)
Cc: Rob Clark <robclark@freedesktop.org>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90466
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Wed, 15 Apr 2015 12:40:55 +0000 (13:40 +0100)]
mesa; add a dummy _mesa_error_no_memory() symbol to libglsl_util
Rather than forcing everyone to provide their own definition of the symbol
provide a common (dummy) one.
This helps us resolve the build of the standalone pipe-drivers (amongst
others), which are missing the symbol.
Cc: Rob Clark <robclark@freedesktop.org>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Wed, 15 Apr 2015 10:42:55 +0000 (11:42 +0100)]
gallium: use $(top_builddir) when referencing static archives
Just like every other place in gallium.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Wed, 15 Apr 2015 10:28:38 +0000 (11:28 +0100)]
freedreno: use CXX linker rather than explicit link against libstdc++
Cc: Rob Clark <robclark@freedesktop.org>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 12:08:00 +0000 (13:08 +0100)]
egl/haiku: coding style fixes
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 12:07:08 +0000 (13:07 +0100)]
egl/haiku: plug some obvious memory leaks
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 11:33:55 +0000 (12:33 +0100)]
egl/haiku: minor surface management cleanups
Drop the stub/unused function haiku_create_surface() and add some basic implementation for destroy_surface()
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 11:22:28 +0000 (12:22 +0100)]
egl/haiku: kill off haiku_log()
It's an incomplete copy of the default _eglLog() implementation. Just
use the default logger.
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 11:20:34 +0000 (12:20 +0100)]
egl/haiku: we don't use src/loader, drop all the references to it
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 11:18:35 +0000 (12:18 +0100)]
egl/haiku: remove unused variables in struct haiku_egl_driver
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 11:17:23 +0000 (12:17 +0100)]
egl/haiku: handle memory allocation failure
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 11:02:45 +0000 (12:02 +0100)]
egl/haiku: use CALL/TRACE/ERROR over _eglLog() for haiku specifics
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 10:31:40 +0000 (11:31 +0100)]
egl/haiku: remove commented out code
It serves little to no purpose. As the driver gets updated, one can
look at the existing implementation (dri2) for reference rather than
letting the commented functions bitrot.
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 10:24:17 +0000 (11:24 +0100)]
egl/haiku: use correct version variable
Earlier commit folded the two separate variables into one, but forgot to
update the haiku driver.
Fixes:
0e4b564ef28(egl: combine VersionMajor and VersionMinor into one
variable)
Cc: Marek Olšák <marek.olsak@amd.com>>
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Jose Fonseca [Fri, 12 Jun 2015 11:13:41 +0000 (12:13 +0100)]
trace: Add missing p_compiler.h include.
For boolean.
Trivial.
Francisco Jerez [Wed, 10 Jun 2015 11:40:33 +0000 (14:40 +0300)]
i965/fs: Remove one more fixed brw_null_reg() from the visitor.
Instead use fs_builder::null_reg_f() which has the correct register
width. Avoids the assertion failure in fs_builder::emit() hit by the
"ES3-CTS.shaders.loops.for_dynamic_iterations.unconditional_break_fragment"
GLES3 conformance test introduced by
4af4cfba9ee1014baa4a777660fc9d53d57e4c82.
Reported-and-reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Tue, 9 Jun 2015 16:20:58 +0000 (09:20 -0700)]
Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."
This reverts commit
f3b709c0ac073cd0ec90a3a0d91d1ee94668e043.
The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4.
interpolation.lines_wide" test appears to be broken on Cherryview when
we expose line widths greater than 12.0. I'm not sure why.
For now, just go back to the limits we used on older platforms.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902
Acked-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 10 Jun 2015 08:46:13 +0000 (01:46 -0700)]
i965: Re-index SSA definitions before printing NIR code.
This makes the SSA definitions use sequential numbers (0, 1, 2, ...)
instead of seemingly random ones. There's not much point normally,
but it makes debug output much easier to read.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Brian Paul [Wed, 10 Jun 2015 16:59:37 +0000 (10:59 -0600)]
gallium: remove explicit values from PIPE_CAP_ enums
The other PIPE_CAPF_ and PIPE_SHADER_CAP_ enums don't have explicit values.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Jose Fonseca [Thu, 11 Jun 2015 12:32:21 +0000 (13:32 +0100)]
mesa/main: Don't use ONCE_FLAG_INIT as a r-value.
It should only be used as an initializer expression.
Trivial, and fixes Windows builds.
Nevertheless, overwriting an once_flag like this seems dangerous and
should be revised.
Iago Toral Quiroga [Thu, 11 Jun 2015 06:49:46 +0000 (08:49 +0200)]
i965/gen8: Fix antialiased line rendering with width < 1.5
The same fix Marius implemented for gen6 (commit
a9b04d8a) and
gen7 (commit
24ecf37a).
Also, we need the same code to handle special cases of line width
in gen6, gen7 and now gen8, so put that in the helper function
we use to compute the line width.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Martin Peres [Tue, 26 May 2015 12:32:21 +0000 (15:32 +0300)]
glsl: fix constructing a vector from a matrix
Without this patch, the following constructs (not an extensive list)
would crash mesa:
- mat2 foo = mat2(1); vec4 bar = vec4(foo);
- mat3 foo = mat3(1); vec4 bar = vec4(foo);
- mat3 foo = mat3(1); ivec4 bar = ivec4(foo);
The first case is explicitely allowed by the GLSL spec, as seen on
page 101 of the GLSL 4.40 spec:
"vec4(mat2) // the vec4 is column 0 followed by column 1"
The other cases are implicitely allowed also.
The actual changes are quite minimal. We first split each column of
the matrix to a list of vectors and then use them to initialize the
vector. An additional check to make sure that we are not trying to
copy 0 elements of a vector fix the (i)vec4(mat3) case as the last
vector (3rd column) is not needed at all.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
Tapani Pälli [Wed, 6 May 2015 10:43:54 +0000 (13:43 +0300)]
mesa/es3.1: enable DRAW_INDIRECT_BUFFER_BINDING for gles3.1
(increases ES31-CTS.draw_indirect.basic.* passing tests)
v2: only expose DRAW_INDIRECT_BUFFER_BINDING for GL core + ES3.1
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Juha-Pekka Heikkila [Fri, 20 Mar 2015 13:40:26 +0000 (15:40 +0200)]
mesa/main: avoid null access in format_array_table_init()
If _mesa_hash_table_create failed we'd get null pointer. Report
error and go away.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Juha-Pekka Heikkila [Fri, 20 Mar 2015 13:13:14 +0000 (15:13 +0200)]
mesa/main: Remove _mesa_HashClone()
I didn't find this being used anywhere.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Alexander Monakov [Tue, 9 Jun 2015 17:58:22 +0000 (20:58 +0300)]
i965: do_blit_drawpixels: decode array formats
Correct a regression introduced by commit
922c0c9fd526 by converting "array
format", if received from _mesa_format_from_format_and_type, to mesa_format.
References: https://bugs.freedesktop.org/show_bug.cgi?id=90839
Signed-off-by: Alexander Monakov <amonakov@gmail.com>
Tested-by: AnAkkk <anakin.cs@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Iago Toral Quiroga [Wed, 10 Jun 2015 07:07:32 +0000 (09:07 +0200)]
i965: do not round line width when multisampling or antialiaing are enabled
In commit
fe74fee8fa721a we rounded the line width to the nearest integer to
match the GLES3 spec requirements stated in section 13.4.2.1, but that seems
to break a dEQP test that renders wide lines in some multisampling scenarios.
Ian noted that the Open 4.4 spec has the following similar text:
"The actual width of non-antialiased lines is determined by rounding the
supplied width to the nearest integer, then clamping it to the
implementation-dependent maximum non-antialiased line width."
and suggested that when ES removed antialiased lines, they removed
"non-antialised" from that paragraph but probably should not have.
Going by that note, this patch restricts the quantization implemented in
fe74fee8fa721a only to regular aliased lines. This seems to keep the
tests fixed with that commit passing while fixing the broken test.
v2:
- Drop one of the clamps (Ken, Marius)
- Add a rule to prevent advertising line widths that when rounded go beyond
the limits allowed by the hardware (Ken)
- Update comments in the code accordingly (Ian)
- Put the code in a utility function (Ian)
Fixes:
dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90749
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Tue, 9 Jun 2015 21:33:47 +0000 (14:33 -0700)]
i965: Momentarily pretend to support ARB_texture_stencil8 for blits.
Broadwell's stencil blitting code attempts to bind a renderbuffer as a
texture, using dd->BindRenderbufferTexImage().
This calls _mesa_init_teximage_fields(), which then attempts to set
img->_BaseFormat = _mesa_base_tex_format(ctx, internalFormat), which
assert fails if internalFormat is GL_STENCIL_INDEX8 but
ARB_texture_stencil8 is unsupported.
To work around this, just pretend to support the extension momentarily,
during the blit. Meta has already munged a variety of other things in
the context (including the API!), so it's not that much worse than what
we're already doing.
Fixes regressions since commit
f7aad9da20b13c98f77d6a690b327716f39c0a47
(mesa/teximage: use correct extension for accept stencil texture.).
v2: Add an XXX comment explaining the situation (requested by Jason
Ekstrand and Martin Peres), and an assert that we don't support
the extension so we remember to remove this hack (requested by
Neil Roberts).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Brian Paul [Wed, 10 Jun 2015 13:28:40 +0000 (07:28 -0600)]
llvmpipe: simplify lp_resource_copy()
Just implement it in terms of util_resource_copy_region(). Both the
original code and util_resource_copy_region() boil down to mapping,
calling util_copy_box() and unmapping.
No piglit regressions. This will also help to implement GL_ARB_copy_image.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Tapani Pälli [Tue, 9 Jun 2015 09:26:48 +0000 (12:26 +0300)]
mesa: add GL_RED, GL_RG support for floating point textures
Mesa supports EXT_texture_rg and OES_texture_float. This patch adds
support for using unsized enums GL_RED and GL_RG for floating point
targets and writes proper checks for internalformat when format is
GL_RED or GL_RG and type is of GL_FLOAT or GL_HALF_FLOAT.
Later, internalformat will get adjusted by adjust_for_oes_float_texture
after these checks.
v2: simplify to check vs supported enums
v3: follow the style and break out if internalFormat ok (Kenneth)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tapani Pälli [Mon, 8 Jun 2015 11:53:26 +0000 (14:53 +0300)]
mesa: allow unsized formats GL_RG, GL_RED for GLES 3.0 with half float
v2: && -> ||, we enable on gles3 or if ARB_texture_rg is enabled
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 9 Jun 2015 06:53:55 +0000 (16:53 +1000)]
glsl: remove restriction on unsized arrays in GLSL ES 3.10
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Dave Airlie [Wed, 10 Jun 2015 03:51:59 +0000 (13:51 +1000)]
st/dri: check pscreen is valid before querying param
we don't check the validity of pscreen until dri_init_screen_helper
hit this trying to init glamor on a device with no driver (udl).
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 10 Jun 2015 03:26:56 +0000 (13:26 +1000)]
nouveau: set imported buffers to what the kernel gives us
When we import a dma-buf fd from another driver the kernel
gives us the right info, and this trashes it.
Convert the kernel bo flags into the domain flags.
This helps getting reverse prime and glamor working.
Cc: mesa-stable@lists.freedesktop.org
Acked-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Sun, 7 Jun 2015 19:02:02 +0000 (12:02 -0700)]
vc4: Drop qir include from vc4_screen.h
We didn't need any of it except for the list header, and qir.h pulls in
nir.h, which is not really interesting to winsys.