v3dv: fix pool descriptor count for inline uniform buffers

Fixes VK_ERROR_OUT_OF_POOL_MEMORY in the inlineuniformblocks
sample from Sascha Willems.

Fixes: ea3223e7a46 ('v3dv: implement VK_EXT_inline_uniform_block')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17311>

vulkan/wsi: Disable dma-buf sync file if ENOSYS is returned

ENOSYS is commented as "Invalid system call number". This is returned
by qemu-user for unbridged ioctls.

Fixes: 30b57f10b36d ("vulkan/wsi: Signal semaphores and fences from the dma-buf")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17325>

dzn: Mark transition barriers as executed when we execute barriers

It was previously done dzn_cmd_buffer_flush_transition_barriers(),
leaving the queue+flush case unhandled. Let's fix that by moving
this piece of code to dzn_cmd_buffer_exec_transition_barriers().

Fixes: 35356b1173e ("dzn: Cache and pack transition barriers")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17314>

broadcom/rpi4-skips: drop duplicated lines

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17312>

glsl: drop non-nir path for atan in builtin functions

All drivers now use NIR. Here we drop the non NIR path and rename
the NIR path to drop the extra "_op" chars from the function names.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17308>

intel/fs: Opportunistically split SEND message payloads

While we've taken advantage of split-sends in select situations, there
are many other cases (such as sampler messages, framebuffer writes, and
URB writes) that have never received that treatment, and continued to
use monolithic send payloads.

This commit introduces a new optimization pass which detects SEND
messages with a single payload, finds an adjacent LOAD_PAYLOAD that
produces that payload, splits it two, and updates the SEND to use both
of the new smaller payloads.

In places where we manually used split SENDS, we rely on underlying
knowledge of the message to determine a natural split point.  For
example, header and data, or address and value.

In this pass, we instead infer a natural split point by looking at the
source registers.  Often times, consecutive LOAD_PAYLOAD sources may
already be grouped together in a contiguous block, such as a texture
coordinate.  Then, there is another bit of data, such as a LOD, that
may come from elsewhere.  We look for the point where the source list
switches VGRFs, and split it there.  (If there is a message header, we
choose to split there, as it will naturally come from elsewhere.)

This not only reduces the payload sizes, alleviating register pressure,
but it means that we may be able to eliminate some payload construction
altogether, if we have a contiguous block already and some extra data
being tacked on to one side or the other.

shader-db results for Icelake are:

   total instructions in shared programs: 19602513 -> 19369255 (-1.19%)
   instructions in affected programs: 6085404 -> 5852146 (-3.83%)
   helped: 23650 / HURT: 15
   helped stats (abs) min: 1 max: 1344 x̄: 9.87 x̃: 3
   helped stats (rel) min: 0.03% max: 35.71% x̄: 3.78% x̃: 2.15%
   HURT stats (abs)   min: 1 max: 44 x̄: 7.20 x̃: 2
   HURT stats (rel)   min: 1.04% max: 20.00% x̄: 4.13% x̃: 2.00%
   95% mean confidence interval for instructions value: -10.16 -9.55
   95% mean confidence interval for instructions %-change: -3.84% -3.72%
   Instructions are helped.

   total cycles in shared programs: 848180368 -> 842208063 (-0.70%)
   cycles in affected programs: 599931746 -> 593959441 (-1.00%)
   helped: 22114 / HURT: 13053
   helped stats (abs) min: 1 max: 482486 x̄: 580.94 x̃: 22
   helped stats (rel) min: <.01% max: 78.92% x̄: 4.76% x̃: 0.75%
   HURT stats (abs)   min: 1 max: 94022 x̄: 526.67 x̃: 22
   HURT stats (rel)   min: <.01% max: 188.99% x̄: 4.52% x̃: 0.61%
   95% mean confidence interval for cycles value: -222.87 -116.79
   95% mean confidence interval for cycles %-change: -1.44% -1.20%
   Cycles are helped.

   total spills in shared programs: 8387 -> 6569 (-21.68%)
   spills in affected programs: 5110 -> 3292 (-35.58%)
   helped: 359 / HURT: 3

   total fills in shared programs: 11833 -> 8218 (-30.55%)
   fills in affected programs: 8635 -> 5020 (-41.86%)
   helped: 358 / HURT: 3

   LOST:   1 SIMD16 shader, 659 SIMD32 shaders
   GAINED: 65 SIMD16 shaders, 959 SIMD32 shaders

   Total CPU time (seconds): 1505.48 -> 1474.08 (-2.09%)

Examining these results: the few shaders where spills/fills increased
were already spilling significantly, and were only slightly hurt.  The
applications affected were also helped in countless other shaders, and
other shaders stopped spilling altogether or had 50% reductions.  Many
SIMD16 shaders were gained, and overall we gain more SIMD32, though many
close to the register pressure line go back and forth.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17018>

intel/compiler: Handle split-sends in EOT high-register pinning case

SEND messages with EOT need to use g112-g127 for their sources so that
the hardware is able to launch new threads while old ones are finishing
without worrying about register overlap when pushing payloads.  For the
newer split-send messages, this applies to both source registers.

Our special case for this in the register allocator was only considering
the first source.  This wasn't a problem because we hadn't ever tried to
use split-sends with EOT before.  However, my new optimization pass is
going to introduce some shortly, so we'll need to handle them properly.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17018>

aco: drop radv_shader.h include

This shouldn't be used anymore

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>

aco/radv: provide a vs prolog callback from aco to radv.

Avoid building the radv binary in aco, just callback with the
necessary info.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>

aco/radv: provide a callback from aco shader building to build binary

This moves the radv specific code into radv, and calls back from
aco into radv.

This should allow easier radeonsi integration later.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>

aco: refactor the radv binary builder out of the core aco fn.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>

intel/compiler: Convert brw_eu.cpp back to brw_eu.c

Now that we've removed the thread_local lookup tables using
pointer-to-member C++ features, this can go back to being a standard
C file, like it was in the past.  We just need to annotate a couple
of things with "struct".

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Remove use of thread_local for opcode tables

We had been using thread_local index -> opcode_desc tables to avoid
plumbing through a storage location throughout all the code.  But now
we have done so with the new brw_isa_info structure.  So we can just
store the tables there, and initialize it with the compiler.

This fixes crashes in gtk4-demo on iris, and should help with some
programs on zink as well.  Something was going wrong with the
thread_local variables not being set up correctly.  While we might be
able to work around that issue, there's really no advantage to storing
these lookup tables in TLS (beyond it being simpler to do originally).
So let's simply stop doing so.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6728
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6229
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Introduce a new brw_isa_info structure

This structure will contain the opcode mapping tables in the next
commit.  For now, this is the mechanical change to plumb it into all
the necessary places, and it continues simply holding devinfo.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Move opcode_desc handling to a separate header

This patch creates a new header file, brw_isa_info.h, which will
contains all the functions related to opcode encoding on various
generations.  Opcode numbers may have different meanings on different
hardware, so we remap them between an enum we can easily work with
and the hardware encoding.

We move the brw_inst setters and getters to brw_inst.h.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/tools: Stop malloc'ing device info in i965_disasm

There's not really any point, a stack allocated struct works fine.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Split 3DPRIM_* defines out to a separate header.

These clash with genxml and will become a problem shortly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Fix brw_gfx_ver_enum.h to be a proper header file

This header file didn't include normal guards against being included
multiple times.  It also defined a function in a header file without
marking it static inline.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Stop including src/mesa/main/config.h

src/mesa/main includes are for Mesa's OpenGL implementation, and the
compiler is used in Vulkan drivers and other tools.  We really only
needed one #define, which is that we offer 32 samplers.  It probably
makes more sense to have our own defined limit for that rather than
importing a project-wide value which theoretically could be adjusted,
so swap MAX_SAMPLERS for a new BRW_MAX_SAMPLERS and call it a day.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

crocus: Use PIPE_* defines rather than ones from main/config.h

Gallium drivers shouldn't be including src/mesa/main headers, but we're
picking up a rogue main/config.h via the compiler, so this code I ported
over from i965 kept compiling.  Use the PIPE_* defines instead so that
we can stop including that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

iris: Use PIPE_* defines rather than ones from main/config.h

Gallium drivers shouldn't be including src/mesa/main headers, but we're
picking up a rogue main/config.h via the compiler, so this code I ported
over from i965 kept compiling.  Use the PIPE_* defines instead so that
we can stop including that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

zink: enforce viewport depth clamping

VUID-VkViewport-minDepth-01234 specifies that depth must be in the range [0.0, 1.0],
so the viewport must always be clamped to this range

this affects texture clears using u_blitter, as this expects to be able
to use the GL range of [-1.0, 1.0], so pass the depth value as though it's
been de-converted back to a GL z coordinate to account for viewport transform

cc: mesa-stable

fixes #6757

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17319>

lavapipe: don't remove xfb outputs

cc: mesa-stable

fixes:
dEQP-VK.transform_feedback.simple.multiquery_omit_write_1
dEQP-VK.transform_feedback.simple.multiquery_omit_write_3
dEQP-VK.transform_feedback.simple.query_omit_write_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_4_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_4_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_250_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_250_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_508_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_508_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_124_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_124_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_248_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_248_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_4_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_4_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_508_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_508_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_249_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_249_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_507_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_507_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_246_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_246_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_504_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_504_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_250_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_250_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_508_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_508_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_6_64bits

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17299>

zink: disable turnip traces temporarily

this needs a libX11 update

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17313>

venus: use narrow range to match up with mesa EGL

This matches up with the native gl drivers as well as the media stack.

Test: android.graphics.cts.MediaVulkanGpuTest
Test: android.media.cts.EncodeDecodeTest

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17306>

radv/ci: re-enable vega10 fossils testing

Should work now.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17295>

aco/ra: update register file when updating phi definition

update_renames() fills in the wrong temp id.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 302cb5c9001 ("aco/ra: remove some redundant code")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17295>

docs: update calendar and link releases notes for 22.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17318>

docs: add sah256sum for mesa 22.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17318>

docs: add release notes for 22.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17318>

ci: Remove the trailing "when: never"s from rules.

This avoids the risks of concatenating our rulesets missing out on some
file list because of a "never" in the middle.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci/zink: Simplify lavapipe rules setup, and clarify what the rules are for.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci/zink: Reuse anv-rules.

This makes it so that we respect collabora farm disables.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci/freedreno: Filter when we run test jobs for VK or GL changes.

Not only runs less testing when only one driver is impacted, but also
makes sure zink+turnip is turned off when the farm is.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Split core GL from core VK-or-GL rules.

Now editing src/glx won't rerun Vulkan testing.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Simplify vulkan rules using !references.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci/freedreno: Use !references to clean up restricted traces rules.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Pull common zink frontend rules to a shared rule list.

This drops the mesa/gallium lists from some build rules, since zink common
rules brings them in already.  If we do more driver common rules, we might
end up with those core lists appearing in the yaml multiple times, but
that seems like a small price to pay for not being able to forget some.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Pull out farm disables to a reused rule.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Use "!references" to manage scheduled pipeline rules.

Because !references merging happens after yaml parsing, this lets us
remove a duplicated definition between .test-source-dep.yml and
.gitlab-ci.yml.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

dozen: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

microsoft: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

intel: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

d3d12: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

nir: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

radv: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

nir: Add a nir_test_mask helper

nir_ine_imm(b, nir_iand_imm(b, x, mask), 0) and
nir_i2b(b, nir_iand_imm(b, x, mask)) are common
patterns which become quite messy when they are
part of a larger expression. Clang-format does
not improve things either and we can end up with
some rather interesting looking code.
(RADV ray tracing pipeline and query lowering)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

radv: reorder some NIR passes

Totals from 6171 (4.57% of 134913) affected shaders: (GFX10.3)
CodeSize: 61916968 -> 61916676 (-0.00%); split: -0.01%, +0.01%
Instrs: 11473620 -> 11473797 (+0.00%); split: -0.01%, +0.01%
Latency: 161997216 -> 161997029 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 29075944 -> 29075862 (-0.00%); split: -0.00%, +0.00%
VClause: 199793 -> 199790 (-0.00%); split: -0.01%, +0.00%
SClause: 418180 -> 418013 (-0.04%)
Copies: 786921 -> 786884 (-0.00%); split: -0.06%, +0.06%
Branches: 348058 -> 348106 (+0.01%); split: -0.04%, +0.06%
PreSGPRs: 604400 -> 604396 (-0.00%)
PreVGPRs: 469415 -> 469430 (+0.00%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17279>

radv: fix swizzles after nir_opt_algebraic_late

Fixes: 2e895f8b0496f9f15359a5d98ef722d3d9753bc4 ('radv: vectorize nir_op_fabs')
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17279>

ac/nir/ngg: Refactor LDS instructions in NGG GS vertex emit and export.

Change NGG GS emit vertex code to emit combined shared stores,
also change the export vertex code to emit combined shared loads.
This results in more optimal code generation, ie. fewer LDS
instructions are generated.

GS vertices are stored using an odd stride to minimize the chance
of bank conflicts, which means that unfortunately
we still can't use an alignment higher than 4 here,
so the best we can get are some ds_read2_b32 instructions.

Fossil DB stats on Navi 21 (formerly Sienna Cichlid):

Totals from 135 (0.10% of 128653) affected shaders:
VGPRs: 6416 -> 6512 (+1.50%)
CodeSize: 529436 -> 503792 (-4.84%)
MaxWaves: 2952 -> 2924 (-0.95%)
Instrs: 93384 -> 90176 (-3.44%)
Latency: 290283 -> 293611 (+1.15%); split: -0.36%, +1.50%
InvThroughput: 81218 -> 82598 (+1.70%)
Copies: 6603 -> 6606 (+0.05%)
PreVGPRs: 5037 -> 5076 (+0.77%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11425>

zink: don't increment screen->num_contexts for copy context

this otherwise may trigger unwanted perf regressions

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17315>

zink: store context flags

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17315>

nv50/ir/ra: Fix copying compound for moves

In order to reduce moves when coalescing multiple registers into a
larger register, RA will try to coalesce MERGE instructions with their
definitions. For example, for something like this in GLSL:

uint a = ...;
uint b = ...;
uint64 x = packUint2x32(a, b);

The compiler will try to coalesce x with a and b, in the same way as
something like:

uint a = ...;
uint b = ...;
...
uint x = phi(a, b);

with the crucial difference that the definitions of a and b only clobber
part of the register, instead of the whole thing. This information is
carried through the compound flag and compMask bitmask. If compound is
set, then the value has been coalesced in such a way that not all the
defs clobber the entire register. The compMask bitmask describes which
subregister each def clobbers, although it does it in a slightly
convoluted way. It's an invariant that once compound is set on one def,
it must be set for all the defs in a given coalesced value.

In more detail, the constraints pass will first create extra moves:

uint a = ...;
uint b = ...;
uint a' = a;
uint b' = b;
uint64 x = packUint2x32(a', b');

and then RA will merge values involved in MERGE/SPLIT instructions,
merging x with a' and b' and making the combined value compound -- this
is relatively simple, and will always succeed since we just created a'
and b', so they never interfere with x, and x has no other definitions,
since we haven't started coalescing moves yet. Basically, we just replaced
the MERGE instruction with an equivalent sequence of partial writes to the
destination. The tricky part comes when we try to merge a' with a
and b' with b. We need to transfer the compound information from a' to a
and b' to b, which copyCompound() does, but we also need to transfer it
to any defs coalesced with a and b, which the code failed to do. Similarly,
if x is the argument to a phi instruction, then when we try to merge it
with other arguments to the same phi by coalescing moves, we'd have
problems guaranteeing that all the other merged defs stay up-to-date.

One tricky part of fixing this is that in order to properly propagate
the information from a' to a, we need to do it before the defs for a and
a' are merged in coalesceValues(), since we need to know which defs are
merged with a but not a' -- after coalesceValues() returns, all the defs
have been combined, so we don't know which is which. I took the approach
of calling copyCompound() inside coalesceValues(), instead of
afterwards.

v2: (mhenning) This now loops over mergedDefs in copyCompound, to update
    it for changes made in bcf6a9ec

Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Karol Herbst <kherbst@redhat.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17115>

zink: remove the workaround for depth_clip_enable on turnip

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>

turnip: keep the depth_clip_disable state at the pipeline builder.

So we could later decide whether to enable Z_CLIP_DISABLE on not.

Closes: #6732

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>

freedreno,ir3: rename Z_CLAMP_ENABLE to Z_CLIP_DISABLE

UNK5 of GRAS_CL_CNTL is still unclear though.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>

nir/types: fix glsl_matrix_type_is_row_major() assert

interface blocks can have row_major set

cc: mesa-stable

affects (zink):
dEQP-GLES2.functional.shaders*

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17238>

zink: workaround depth sampler border color when z24 is z32

If there is a z24 unorm depth buffer, but it's the hw is using
a z32, the border color needs to be clamped appropriately.

This creates a second sampler with the clamped border color,
and uses it if needed. The checks might need some tightening up.

Fixes: zink on radv
dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth
dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth_uint_stencil_sample_depth

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17305>

ci: Remove -Wno-error=maybe-uninitialized

It is not needed anymore.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17121>

svga: Clear query before usage

Fixes the following compiler warning:
  svga_pipe_query.c:1295:17: warning: 'result.u64' may be used uninitialized [-Werror=maybe-uninitialized]

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17121>

r600: Switch to unreachable(..)

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17121>

gtest: Fix maybe-uninitialized compiler warning

This is a cherry-pick from upstream - 4679637f ("Fix warning maybe-uninitialized").

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17121>

vulkan: Depend on vk_pipeline_layout in vk_cmd_enqueue

Now that we have a common pipeline layout with reference counting, we
don't need these driver hooks for reference counting anymore.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

dzn: Use the vk_pipeline_layout base struct

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

dzn: Use the vk_descriptor_set_layout base struct

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

panvk: Use the vk_pipeline_layout base struct

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

panvk: Use the vk_descriptor_set_layout base struct

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

lavapipe: Use the vk_pipeline_layout base struct

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

lavapipe: Use the vk_descriptor_set_layout base struct

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

vulkan: Add a common implementation of pipeline layouts

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

vulkan: Add a base struct for descriptor set layouts

There's some tricky stuff in here with properly handling Vulkan
allocation scopes and reference counting.  Probably best to do it once.
Also, this means that common code can now take references to descriptor
set layouts which seems useful.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

vulkan: Fix a comment

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17286>

util/xmlconfig: fix -Wmaybe-uninitialized warning

```
xmlconfig.c:570:7: warning: 'userData.name' may be used uninitialized [-Wmaybe-uninitialized]
```

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16912>

dzn: Fix -Wswitch warnings

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

dzn: Fix {back,front}_wr_uses_ref assignment

We're lacking parens, as reported by clang.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

dzn: Fix printf() format in dxgi_get_factory() error message

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

dzn: Fix 'statement with no effect' warning

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

dzn: Fix unused var warnings

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

dzn: Fix copies of block-based formats

D3D12 wants Width, Height and Depth to be aligned on the block width,
height and depth size. But Vulkan allows the width, height or depth to
be unaligned at the image boundary if image.{width,height,depth} is
not aligned.

Let's explicitly align things in the copy paths.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

dzn: Allow shaders to read from depth/stencil attachments

D3D12_RESOURCE_STATE_DEPTH_READ only provides access for fixed-function
depth/stencil test. If we want the shaders to be able to read the
depth/stencil attachment, we need to combine
D3D12_RESOURCE_STATE_DEPTH_READ and
D3D12_RESOURCE_STATE_PIXEL_SHADER_RESOURCE.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

dzn: Introduce dzn_cmd_buffer_queue_image_range_state_transition()

Sometimes there's no obvious mappings between a VkImageLayout and
a D3D12_RESOURCE_STATE, so let's just provide a helper that takes
before/after resource states instead of old/new layouts, and use it
to fix the resolve case.

Fixes: 35356b1173ee ("dzn: Cache and pack transition barriers")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

dzn: Rename dzn_cmd_buffer_queue_image_subres_range_transition()

We are about to introduce the same function taking D3D12_RESOURCE_STATES
arguments instead of VkImageLayout ones. Let's rename the function
accordingly.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

dzn: Don't call dzn_cmd_buffer_queue_transition_barriers() prematurely

We want to pack ResourceBarriers() call as much as we can, so let's
not dzn_cmd_buffer_queue_transition_barriers() when we could still queue
new barriers.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17250>

v3d/ci: Add flake test

This test works when executed alone, but fails when running the full
GLES3 CTS.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17300>

dzn: Cache and pack transition barriers

Some Vulkan -> D3D12 API mismatches force us to do behind-the-scene
transitions to get resources in the right state when executing
non-native operations. In this case, caching the transition until the
resource is actually used might save us unneeded transitions.

The packing aspect is mostly useful to limit the ExecuteBarriers()
call overhead. Right now we do per-resource packing, and any hole
in the subresource range will trigger several ExecuteBarriers()
calls. This can be improved by collecting barriers in a separate
array, and flushing the collected transition barriers just before
executing the operation using the subresources pointed by those
barriers. While not impossible, it'd be more verbose than what we
have right now, so I'm not entirely convinced it's worth it.

Caching could be improved to avoid any unnecessary flush when we do
blit or copy operations and transition the resources back to their
original state, since the user might decide to transition the image to
a new layout just after that. But doing that would require keeping
track of all resources used by dispatch/draw operations, which in turn
implies keeping info about which of the descriptor set resources are
used by the graphics/compute pipelines. Not sure the it's worth the
extra complexity given D3D12 enhanced barriers are just around the
corner, and those map pretty nicely to the vulkan barrier+image-layout
model.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17274>

turnip: fix wrong size for lrz cs when lrz_track_quirk is enabled.

Fixes: 4b5f0d98fd5 ("tu: Overhaul LRZ, implement on-GPU dir tracking and
LRZ fast-clear")

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17289>

anv: remove device features handling now in runtime

v2: Keep VkPhysicalDeviceBufferDeviceAddressFeaturesEXT (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17272>

lima: fix buffer overallocation for index, vertex and constant buffers

24be0119016f ("lima: wire up MSAA 4x support") switched to aligning all the
buffers to tile size and it resulted in allocating 16x more memory for
index, vertex and constant buffers.

We only want to align textures and render targets to tile size, not
other buffers, so restore old logic, but relax it.

Fixes: 24be0119016f ("lima: wire up MSAA 4x support")
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17283>

radv: do not emit SQTT user data packets on the SDMA queue

They aren't supported and lead to GPU hangs.

Reported-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17256>

anv: disable non uniform indexing of UBOs

The feature we wanted to enable in 710393b3aa4a was
descriptorBindingUniformBufferUpdateAfterBind.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 710393b3aa4a ("anv: enable UBO indexing")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17200>

draw/cliptest: add support for guard band + full Z

This is hit using lavapipe with zink on top running
dEQP-GL45-ES31.functional.primitive_bounding_box.wide_points.global_state.vertex_tessellation_fragment.default_framebuffer_bbox_equal

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17270>

lavapipe: streamline xfb shader setup

this is a bit easier to read

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17268>

lavapipe: break out part of shader optimization into function

used in (distant) future work

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17268>

zink: set PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY for device-local resources

these can't be mapped, so ensure tc doesn't try to pass UNSYNCHRONIZED
maps and break the resources

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17187>

mesa/st: Fix border color type for stencil sampling

When the stencil aspect of a depth+stencil texture is sampled, it's
actually integer. Also fixup st_translate_color() that assumed it was
float. This fixes the border color on zink+turnip.

v2: Add "|| texBaseFormat == GL_STENCIL_INDEX" to catch the case where
S8 is emulated as D24S8.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>

tu: Fix stencil border color with has_z24uint_s8uint

On a650+ we use the new Z24UINT_S8UINT format to sample the stencil
aspect of D24S8, which returns stencil in the second component and also
uses the second integer component for the border color. However Vulkan
mandates that the first component is used for the stencil border color.
There's no workaround we know of, so we have to fall back to the old
behavior where there is a workaround. If we know the format, we can
fixup the border color ourselves though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>

freedreno/a6xx: Fix border color with Z24UINT_S8UINT

With this special format the border color is in the second component of
the f16 member (that's also used for 8-bit and 16-bit integer formats).
This means we have to fix it up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>

freedreno/fdl: Note border color constraints

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>

freedreno/a6xx: Use fdl format swizzle

This makes sure that we use a consistent swizzle between computing the
border color and the texture descriptor, and lets us delete the gallium
version.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>

freedreno/a6xx: Fix border color swizzling

From the API's point of view, border color replacement looks like this:

       --------------------
       | API Border Color |
       --------------------
               |
-----------    |    ----------------      ----------
| API fmt |-------->| User Swizzle |----->| Shader |
-----------         ----------------      ----------

From the HW point of view, it looks like this:

                    -------------------
                    | HW Border Color |
                    -------------------
                             |
----------     -----------   |   ---------------      ----------
| HW fmt |-----| HW swap |------>| Tex Swizzle |----->| Shader |
----------     -----------       ---------------      ----------

When the HW fmt + HW swap isn't enough to represent an API format, we
need to prepend our own swizzle to the the user's swizzle, so the tex
swizzle is a "format swizzle" composed with the user swizzle. However,
we don't want this format swizzle to be applied to border colors, so
there's a workaround in freedreno which is meant to undo the format
swizzle so that the HW border color with the format swizzle applied
equals the API border color, and everything is ok. However, on a6xx at
least it was incorrectly undoing the entire tex swizzle. This broke
border color with a user swizzle, because it was now effectively not
getting applied for the border color. It also made it seem like the user
swizzle is required for the workaround, which would have implications
for VK_EXT_border_color_swizzle with turnip, but it's not.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>