Bjorn Helgaas [Fri, 5 Nov 2021 16:28:53 +0000 (11:28 -0500)]
Merge branch 'remotes/lorenzo/pci/vmd'
- Assign a number to each VMD controller to distinguish them in
/proc/interrupts (Chunguang Xu)
- Don't disable VMD MSI-X remapping if IOMMU remapping is enabled (Adrian
Huang)
- Add Kconfig dependency on !UML for allyesconfig build issue (Johannes
Berg)
* remotes/lorenzo/pci/vmd:
PCI: vmd: depend on !UML
PCI: vmd: Do not disable MSI-X remapping if interrupt remapping is enabled by IOMMU
PCI: vmd: Assign a number to each VMD controller
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:52 +0000 (11:28 -0500)]
Merge branch 'pci/host/rcar'
- Remove unneeded includes (Geert Uytterhoeven)
* pci/host/rcar:
PCI: rcar-host: Remove unneeded includes
PCI: rcar-ep: Remove unneeded includes
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:52 +0000 (11:28 -0500)]
Merge branch 'remotes/lorenzo/pci/qcom'
- Add Qualcomm PCIe Endpoint controller driver and DT binding (Manivannan
Sadhasivam)
- Add qcom struct for device-specific details in match data (Prasad
Malisetty)
- Switch pcie_1_pipe_clk_src from TCXO to pipe clock after PHY init in
SC7280 (Prasad Malisetty)
- Add .compatible device ID for SC8180x platform (Bjorn Andersson)
* remotes/lorenzo/pci/qcom:
PCI: qcom: Add sc8180x compatible
PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
PCI: qcom: Replace ops with struct pcie_cfg in pcie match data
MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding
PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver
dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:51 +0000 (11:28 -0500)]
Merge branch 'pci/host/mt7621'
- Add MediaTek MT7621 SoC PCIe host controller (moved from staging) (Sergio
Paracuellos)
* pci/host/mt7621:
MAINTAINERS: Add Sergio Paracuellos as MT7621 PCIe maintainer
PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
dt-bindings: PCI: Add MT7621 SoC PCIe host controller
# Conflicts:
# drivers/pci/controller/Kconfig
# drivers/pci/controller/Makefile
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:51 +0000 (11:28 -0500)]
Merge branch 'pci/host/kirin'
- Reorganize to separate out PHY logic (Mauro Carvalho Chehab)
- Add support for external PHY in addition to the internal PHY (Mauro
Carvalho Chehab)
- Use regmap so both kirin driver and PHY can access APB registers (Mauro
Carvalho Chehab)
- Add support for per-lane PERST# GPIOs on HiKey970 external PEX 8606 PCI
bridge (Mauro Carvalho Chehab)
- Add "hisilicon,kirin970-pcie" compatible string (Mauro Carvalho Chehab)
- Add MODULE_* macros (Mauro Carvalho Chehab)
- Allow building as a module (Mauro Carvalho Chehab)
- Add power_off support for Kirin 960 PHY (Mauro Carvalho Chehab)
- Disable clkreq during poweroff sequence (Mauro Carvalho Chehab)
- De-init the dwc driver during remove (Mauro Carvalho Chehab)
- Allow removal of kirin driver (Mauro Carvalho Chehab)
* pci/host/kirin:
PCI: kirin: Allow removing the driver
PCI: kirin: De-init the dwc driver
PCI: kirin: Disable clkreq during poweroff sequence
PCI: kirin: Move the power-off code to a common routine
PCI: kirin: Add power_off support for Kirin 960 PHY
PCI: kirin: Allow building it as a module
PCI: kirin: Add MODULE_* macros
PCI: kirin: Add Kirin 970 compatible
PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge
PCI: kirin: Use regmap for APB registers
PCI: kirin: Add support for a PHY layer
PCI: kirin: Reorganize the PHY logic inside the driver
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:50 +0000 (11:28 -0500)]
Merge branch 'remotes/lorenzo/pci/imx6'
- Remove unused assignment (Krzysztof Wilczyński)
* remotes/lorenzo/pci/imx6:
PCI: imx6: Remove unused assignment to variable ret
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:50 +0000 (11:28 -0500)]
Merge branch 'remotes/lorenzo/pci/endpoint'
- Use sysfs_emit() in "show" functions instead of sprintf() to avoid buffer
overruns (Kunihiko Hayashi)
* remotes/lorenzo/pci/endpoint:
PCI: endpoint: Use sysfs_emit() in "show" functions
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:49 +0000 (11:28 -0500)]
Merge branch 'pci/host/dwc'
- Export dw_pcie_ep_reset_bar(), dw_pcie_link_up() so more drivers can be
modular (Luca Ceresoli)
- Allow dra7xx host and endpoint drivers to be modules (Luca Ceresoli)
- Enable dra7xx optional external clock if present (Luca Ceresoli)
- Clean up Kconfig dependencies for PCIE_DW_HOST- and PCIE_DW_EP-based
drivers (Andy Shevchenko)
- Remove visconti redundant dev_err() after platform_get_irq_byname()
failure (Krzysztof Wilczyński)
- Run dwc .host_init() method before registering MSI interrupt handler so
we have a chance to deal with pending interrupts left by bootloader
(Bjorn Andersson)
- Serialize uniphier INTx masking/unmasking (Kunihiko Hayashi)
* pci/host/dwc:
PCI: uniphier: Serialize INTx masking/unmasking and fix the bit operation
PCI: dwc: Perform host_init() before registering msi
PCI: visconti: Remove surplus dev_err() when using platform_get_irq_byname()
PCI: dwc: Clean up Kconfig dependencies (PCIE_DW_EP)
PCI: dwc: Clean up Kconfig dependencies (PCIE_DW_HOST)
PCI: dra7xx: Get an optional clock
PCI: dra7xx: Remove unused include
PCI: dra7xx: Make it a kernel module
PCI: dwc: Export more symbols to allow modular drivers
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:49 +0000 (11:28 -0500)]
Merge branch 'remotes/lorenzo/pci/dt'
- Add Rockchip SoC PCIe controller DT bindings (Simon Xue)
* remotes/lorenzo/pci/dt:
dt-bindings: rockchip: Add DesignWare based PCIe controller
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:49 +0000 (11:28 -0500)]
Merge branch 'pci/host/cadence'
- Disable PHY when j721e_pcie_probe() fails after initializing it
(Christophe JAILLET)
- Return success when cdns-pcie probe succeeds instead of doing error
cleanup (Li Chen)
* pci/host/cadence:
PCI: cadence: Add cdns_plat_pcie_probe() missing return
PCI: j721e: Fix j721e_pcie_probe() error path
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:48 +0000 (11:28 -0500)]
Merge branch 'pci/host/apple'
- Make of_phandle_args_to_fwspec() generally available (Marc Zyngier)
- Allow matching of interrupt-maps local to interrupt controller or PCI
device (Marc Zyngier)
- Add Apple SoC (e.g., M1) PCIe host controller driver, which enables
access to USB type-A, Ethernet, Wi-Fi, Bluetooth devices; these require
additional drivers of their own (Alyssa Rosenzweig)
- Add apple INTx, per-port, and MSI interrupt support (Marc Zyngier)
- Configure apple Requester-ID-to-Stream-ID mapper for IOMMU (DART) support
(Marc Zyngier)
* pci/host/apple:
PCI: apple: Configure RID to SID mapper on device addition
iommu/dart: Exclude MSI doorbell from PCIe device IOVA range
PCI: apple: Implement MSI support
PCI: apple: Add INTx and per-port interrupt support
PCI: apple: Set up reference clocks when probing
PCI: apple: Add initial hardware bring-up
PCI: of: Allow matching of an interrupt-map local to a PCI device
of/irq: Allow matching of an interrupt-map local to an interrupt controller
irqdomain: Make of_phandle_args_to_fwspec() generally available
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:48 +0000 (11:28 -0500)]
Merge branch 'remotes/lorenzo/pci/aardvark'
- Define macros for PCI_EXP_DEVCTL_PAYLOAD_* (Pali Rohár)
- Set Max Payload Size to 512 bytes per Marvell spec (Pali Rohár)
- Downgrade PIO Response Status messages to debug level (Marek Behún)
- Preserve CRS SV (Config Request Retry Software Visibility) bit in
emulated Root Control register (Pali Rohár)
- Fix issue in configuring reference clock (Pali Rohár)
- Don't clear status bits for masked interrupts (Pali Rohár)
- Don't mask unused interrupts (Pali Rohár)
- Avoid code repetition in advk_pcie_rd_conf() (Marek Behún)
- Retry config accesses on CRS response (Pali Rohár)
- Simplify emulated Root Capabilities initialization (Pali Rohár)
- Fix several link training issues (Pali Rohár)
- Fix link-up checking via LTSSM (Pali Rohár)
- Fix reporting of Data Link Layer Link Active (Pali Rohár)
- Fix emulation of W1C bits (Marek Behún)
- Fix MSI domain .alloc() method to return zero on success (Marek Behún)
- Read entire 16-bit MSI vector in MSI handler, not just low 8 bits (Marek
Behún)
- Clear Root Port I/O Space, Memory Space, and Bus Master Enable bits at
startup; PCI core will set those as necessary (Pali Rohár)
- When operating as a Root Port, set class code to "PCI Bridge" instead of
the default "Mass Storage Controller" (Pali Rohár)
- Add emulation for PCI_BRIDGE_CTL_BUS_RESET since aardvark doesn't
implement this per spec (Pali Rohár)
- Add emulation of option ROM BAR since aardvark doesn't implement this per
spec (Pali Rohár)
* remotes/lorenzo/pci/aardvark:
PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge
PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge
PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge
PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge
PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REG
PCI: aardvark: Fix return value of MSI domain .alloc() method
PCI: pci-bridge-emul: Fix emulation of W1C bits
PCI: aardvark: Fix reporting Data Link Layer Link Active
PCI: aardvark: Fix checking for link up via LTSSM state
PCI: aardvark: Fix link training
PCI: aardvark: Simplify initialization of rootcap on virtual bridge
PCI: aardvark: Implement re-issuing config requests on CRS response
PCI: aardvark: Deduplicate code in advk_pcie_rd_conf()
PCI: aardvark: Do not unmask unused interrupts
PCI: aardvark: Do not clear status bits of masked interrupts
PCI: aardvark: Fix configuring Reference clock
PCI: aardvark: Fix preserving PCI_EXP_RTCTL_CRSSVE flag on emulated bridge
PCI: aardvark: Don't spam about PIO Response Status
PCI: aardvark: Fix PCIe Max Payload Size setting
PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:47 +0000 (11:28 -0500)]
Merge branch 'pci/misc'
- Tidy setup-irq.c comments (Pranay Sanghai)
- Fix misspellings (Krzysztof Wilczyński)
- Fix sprintf(), sscanf() format mismatches (Krzysztof Wilczyński)
- Tidy cpqphp code formatting (Krzysztof Wilczyński)
- Remove unused pci_pool wrappers, which have been replaced by dma_pool
(Cai Huoqing)
- Remove a redundant initialization in __pci_reset_function_locked() (Colin
Ian King)
- Use 'unsigned int' instead of 'unsigned' (Krzysztof Wilczyński)
- Update PCI subsystem information in MAINTAINERS (Krzysztof Wilczyński)
- Include generic <linux/> headers instead of <asm/> for cpqphp and vmd
(Krzysztof Wilczyński)
* pci/misc:
PCI: vmd: Drop redundant includes of <asm/device.h>, <asm/msi.h>
PCI: cpqphp: Use <linux/io.h> instead of <asm/io.h>
MAINTAINERS: Update PCI subsystem information
PCI: Prefer 'unsigned int' over bare 'unsigned'
PCI: Remove redundant 'rc' initialization
PCI: Remove unused pci_pool wrappers
PCI: cpqphp: Format if-statement code block correctly
PCI: Use unsigned to match sscanf("%x") in pci_dev_str_match_path()
PCI: hv: Remove unnecessary use of %hx
PCI: Correct misspelled and remove duplicated words
PCI: Tidy comments
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:47 +0000 (11:28 -0500)]
Merge branch 'pci/vpd'
- Add pci_read_vpd_any(), pci_write_vpd_any() to access VPD at arbitrary
offsets (Heiner Kallweit)
- Use VPD API to replace custom code in cxgb3 driver (Heiner Kallweit)
* pci/vpd:
cxgb3: Remove seeprom_write and use VPD API
cxgb3: Use VPD API in t3_seeprom_wp()
cxgb3: Remove t3_seeprom_read and use VPD API
PCI/VPD: Use pci_read_vpd_any() in pci_vpd_size()
PCI/VPD: Add pci_read/write_vpd_any()
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:46 +0000 (11:28 -0500)]
Merge branch 'pci/virtualization'
- Avoid bus resets on Atheros QCA6174, since they hang (Ingmar Klein)
- Use store and forward mode on Pericom PI7C9X2G switches to avoid ACS
erratum with ACS P2P Request Redirect (Nathan Rossi)
* pci/virtualization:
PCI: Add ACS quirk for Pericom PI7C9X2G switches
PCI: Mark Atheros QCA6174 to avoid bus reset
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:46 +0000 (11:28 -0500)]
Merge branch 'pci/sysfs'
- Check for CAP_SYS_ADMIN before validating sysfs user input, not after
(Krzysztof Wilczyński)
- Always return -EINVAL from sysfs "store" functions for invalid user input
instead of -EINVAL sometimes and -ERANGE others (Krzysztof Wilczyński)
- Use kstrtobool() directly instead of the strtobool() wrapper (Krzysztof
Wilczyński)
* pci/sysfs:
PCI: Use kstrtobool() directly, sans strtobool() wrapper
PCI/sysfs: Return -EINVAL consistently from "store" functions
PCI/sysfs: Check CAP_SYS_ADMIN before parsing user input
# Conflicts:
# drivers/pci/iov.c
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:45 +0000 (11:28 -0500)]
Merge branch 'pci/switchtec'
- Return error to application when command execution fails because an
out-of-band reset has cleared the device BARs, Memory Space Enable, etc
(Kelvin Cao)
- Fix MRPC error status handling issue (Kelvin Cao)
- Mask out other bits when reading of management VEP instance ID (Kelvin
Cao)
- Return EOPNOTSUPP instead of ENOTSUPP from sysfs show functions (Kelvin
Cao)
- Add check of event support (Logan Gunthorpe)
* pci/switchtec:
PCI/switchtec: Add check of event support
PCI/switchtec: Replace ENOTSUPP with EOPNOTSUPP
PCI/switchtec: Update the way of getting management VEP instance ID
PCI/switchtec: Fix a MRPC error status handling issue
PCI/switchtec: Error out MRPC execution when MMIO reads fail
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:45 +0000 (11:28 -0500)]
Merge branch 'pci/resource'
- Coalesce host bridge contiguous apertures to allow P2P bridge windows
that span several contiguous host bridge apertures (Kai-Heng Feng)
* pci/resource:
PCI: Coalesce host bridge contiguous apertures
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:45 +0000 (11:28 -0500)]
Merge branch 'pci/portdrv'
- Don't setup portdrv IRQs if there are no port drivers that use them, to
conserve vectors and avoid spurious events (Jan Kiszka)
* pci/portdrv:
PCI/portdrv: Do not setup up IRQs if there are no users
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:44 +0000 (11:28 -0500)]
Merge branch 'pci/p2pdma'
- Apply bus offset correctly in DMA address calculation, which used the
wrong sign before (Wang Lu)
* pci/p2pdma:
PCI/P2PDMA: Apply bus offset correctly in DMA address calculation
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:44 +0000 (11:28 -0500)]
Merge branch 'pci/msi'
- Document sysfs "irq" attribute, which contains either the INTx IRQ (the
intended behavior) or the first MSI IRQ (historical mistake retained for
backwards compatibility) (Barry Song)
- Rework "irq" sysfs show function to explicitly fetch first MSI IRQ
instead of depending on core to put it in dev->irq, to enable future core
cleanup (Barry Song)
* pci/msi:
PCI/sysfs: Explicitly show first MSI IRQ for 'irq'
PCI: Document /sys/bus/pci/devices/.../irq
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:43 +0000 (11:28 -0500)]
Merge branch 'pci/hotplug'
- Ignore Link Down/Up caused by error-induced Hot Reset so endpoint driver
can remain bound to device during error recovery (Lukas Wunner)
- Remove unused resume err_handler (Lukas Wunner)
- Remove unused pcie_port_bus_{,un}register() declarations (Lukas Wunner)
- Skip compiling err.c when CONFIG_PCIEAER not set (Lukas Wunner)
* pci/hotplug:
PCI/ERR: Reduce compile time for CONFIG_PCIEAER=n
PCI/portdrv: Remove unused pcie_port_bus_{,un}register() declarations
PCI/portdrv: Remove unused resume err_handler
PCI: pciehp: Ignore Link Down/Up caused by error-induced Hot Reset
PCI/portdrv: Rename pm_iter() to pcie_port_device_iter()
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:43 +0000 (11:28 -0500)]
Merge branch 'pci/driver'
- Drop the struct pci_dev.driver pointer, which is redundant with the
struct device.driver pointer (Uwe Kleine-König)
* pci/driver:
PCI: Remove struct pci_dev->driver
PCI: Use to_pci_driver() instead of pci_dev->driver
x86/pci/probe_roms: Use to_pci_driver() instead of pci_dev->driver
perf/x86/intel/uncore: Use to_pci_driver() instead of pci_dev->driver
powerpc/eeh: Use to_pci_driver() instead of pci_dev->driver
usb: xhci: Use to_pci_driver() instead of pci_dev->driver
cxl: Use to_pci_driver() instead of pci_dev->driver
cxl: Factor out common dev->driver expressions
xen/pcifront: Use to_pci_driver() instead of pci_dev->driver
xen/pcifront: Drop pcifront_common_process() tests of pcidev, pdrv
nfp: use dev_driver_string() instead of pci_dev->driver->name
mlxsw: pci: Use dev_driver_string() instead of pci_dev->driver->name
net: marvell: prestera: use dev_driver_string() instead of pci_dev->driver->name
net: hns3: use dev_driver_string() instead of pci_dev->driver->name
crypto: hisilicon - use dev_driver_string() instead of pci_dev->driver->name
powerpc/eeh: Use dev_driver_string() instead of struct pci_dev->driver->name
ssb: Use dev_driver_string() instead of pci_dev->driver->name
bcma: simplify reference to driver name
crypto: qat - simplify adf_enable_aer()
scsi: message: fusion: Remove unused mpt_pci driver .probe() 'id' parameter
PCI/ERR: Factor out common dev->driver expressions
PCI: Drop pci_device_probe() test of !pci_dev->driver
PCI: Drop pci_device_remove() test of pci_dev->driver
PCI: Return NULL for to_pci_driver(NULL)
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:42 +0000 (11:28 -0500)]
Merge branch 'pci/enumeration'
- Rename pcibios_add_device() to pcibios_device_add() since it's called
from pci_device_add() (Oliver O'Halloran)
- Don't try to enable AtomicOps on VFs, since they can only be enabled on
the PF (Selvin Xavier)
* pci/enumeration:
PCI: Do not enable AtomicOps on VFs
PCI: Rename pcibios_add_device() to pcibios_device_add()
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:42 +0000 (11:28 -0500)]
Merge branch 'pci/aspm'
- Re-enable LTR in Downstream Ports after it has been disabled by reset or
hotplug to allow use of ASPM L1.2 again and prevent Unsupported Request
errors when Endpoint sends LTR messages (Mingchuang Qiao)
* pci/aspm:
PCI: Re-enable Downstream Port LTR after reset or hotplug
Bjorn Helgaas [Fri, 5 Nov 2021 16:28:42 +0000 (11:28 -0500)]
Merge branch 'pci/acpi'
- Simplify _OSC negotiation with platform for control of PCIe features
(Joerg Roedel)
* pci/acpi:
PCI/ACPI: Check for _OSC support in acpi_pci_osc_control_set()
PCI/ACPI: Move _OSC query checks to separate function
PCI/ACPI: Move supported and control calculations to separate functions
PCI/ACPI: Remove OSC_PCI_SUPPORT_MASKS and OSC_PCI_CONTROL_MASKS
Nathan Rossi [Fri, 10 Sep 2021 02:58:23 +0000 (02:58 +0000)]
PCI: Add ACS quirk for Pericom PI7C9X2G switches
The Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 PCIe switches have an
erratum for ACS P2P Request Redirect behaviour when used in the cut-through
forwarding mode. The recommended work around for this issue is to use the
switch in store and forward mode. The erratum results in packets being
queued and not being delivered upstream, which can be observed as very poor
downstream device performance and/or dropped device-generated
data/interrupts.
Add a fixup so that when enabling or resuming the downstream port we check
if it has enabled ACS P2P Request Redirect, and if so, change the device
(via the upstream port) to use the store and forward operating mode.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=177471
Link: https://lore.kernel.org/r/20210910025823.196508-1-nathan@nathanrossi.com
Tested-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Nathan Rossi <nathan.rossi@digi.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Marc Zyngier [Wed, 29 Sep 2021 16:38:42 +0000 (17:38 +0100)]
PCI: apple: Configure RID to SID mapper on device addition
The Apple PCIe controller doesn't directly feed the endpoint's Requester ID
to the IOMMU (DART), but instead maps RIDs onto Stream IDs (SIDs). The DART
and the PCIe controller must thus agree on the SIDs that are used for
translation (by using the 'iommu-map' property).
For this purpose, parse the 'iommu-map' property each time a device gets
added, and use the resulting translation to configure the PCIe RID-to-SID
mapper. Similarly, remove the translation if/when the device gets removed.
This is all driven from a bus notifier which gets registered at probe time.
Hopefully this is the only PCI controller driver in the whole system.
[bhelgaas: squash indentation from Zhaoyu Liu <zackary.liu.pro@gmail.com>:
https://lore.kernel.org/r/
20211031135544.GA1616@pc]
Link: https://lore.kernel.org/r/20210929163847.2807812-10-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Marc Zyngier [Wed, 29 Sep 2021 16:38:41 +0000 (17:38 +0100)]
iommu/dart: Exclude MSI doorbell from PCIe device IOVA range
The MSI doorbell on Apple HW can be any address in the low 4GB range.
However, the MSI write is matched by the PCIe block before hitting the
iommu. It must thus be excluded from the IOVA range that is assigned to any
PCIe device.
Link: https://lore.kernel.org/r/20210929163847.2807812-9-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Marc Zyngier [Wed, 29 Sep 2021 16:38:40 +0000 (17:38 +0100)]
PCI: apple: Implement MSI support
Probe for the 'msi-ranges' property, and implement the MSI support in the
form of the usual two-level hierarchy.
Note that contrary to the wired interrupts, MSIs are shared among all the
ports.
Link: https://lore.kernel.org/r/20210929163847.2807812-8-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Marc Zyngier [Wed, 29 Sep 2021 16:38:39 +0000 (17:38 +0100)]
PCI: apple: Add INTx and per-port interrupt support
Add support for the per-port interrupt controller that deals with both INTx
signalling and management interrupts.
This allows the Link-up/Link-down interrupts to be wired, allowing the
bring-up to be synchronised (and provide debug information). The framework
can further be used to handle the rest of the per port events if and when
necessary.
Likewise, INTx signalling is implemented so that end-points can actually be
used.
Link: https://lore.kernel.org/r/20210929163847.2807812-7-maz@kernel.org
Link: https://lore.kernel.org/r/20211004150552.3844830-1-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:20 +0000 (11:45 +0100)]
PCI: kirin: Allow removing the driver
Now that everything is in place at the poweroff sequence, this driver can
use module_platform_driver(), which allows it to be removed.
Link: https://lore.kernel.org/r/53b40494252444a9b830827922c4e3a301b8f863.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:19 +0000 (11:45 +0100)]
PCI: kirin: De-init the dwc driver
The logic under .remove ops is missing a call to dw_pcie_host_deinit(). Add
it, in order to allow the DWC core to be properly cleaned up.
Link: https://lore.kernel.org/r/838621e1c84ebaac153ccd9c36ea5e1254c61ead.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:18 +0000 (11:45 +0100)]
PCI: kirin: Disable clkreq during poweroff sequence
The logic at kirin_pcie_gpio_request() enables some clkreq GPIO lines.
Disable them during power-off.
Link: https://lore.kernel.org/r/f403e590843de1a581cade2d534d34715706f54e.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:17 +0000 (11:45 +0100)]
PCI: kirin: Move the power-off code to a common routine
Instead of having two copies of the same logic, place the power-off logic
in a separate function.
No functional changes.
Link: https://lore.kernel.org/r/64f6e8da3e5fff38b6c8fcb208ace46efe6555bb.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:16 +0000 (11:45 +0100)]
PCI: kirin: Add power_off support for Kirin 960 PHY
In order to prepare for module unload, add a power_off method for HiKey
960.
Link: https://lore.kernel.org/r/b095818b0d7fadae4cae200f481caf7a66e61fb4.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:15 +0000 (11:45 +0100)]
PCI: kirin: Allow building it as a module
There's nothing preventing this driver from being loaded as a module.
Change its config from bool to tristate.
Link: https://lore.kernel.org/r/b5e7cfe9df09b492750bd6db0f0c911eaae8c2d4.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:14 +0000 (11:45 +0100)]
PCI: kirin: Add MODULE_* macros
This driver misses the MODULE_* macros. Add them.
Link: https://lore.kernel.org/r/f7a951d0c2009f5765214fc2e83e24cf41585023.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:13 +0000 (11:45 +0100)]
PCI: kirin: Add Kirin 970 compatible
Now that everything is in place, add a compatible for Kirin 970.
Link: https://lore.kernel.org/r/ac8c730c0300b90d96bdaaf387d458d8949241a9.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:11 +0000 (11:45 +0100)]
PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge
On HiKey970, there's a PEX 8606 PCI bridge on its PHY with 6 lanes. Only 4
lanes are connected:
lane 0 - connected to Kirin 970 (upstream)
lane 4 - M.2 slot
lane 5 - mini PCIe slot
lane 6 - on-board Ethernet controller
Each lane has its own PERST# GPIO pin and needs a clock request.
Add support to parse a DT schema containing the above data.
HiKey 970 requires a little more waiting time for the PCI bridge - which is
outside the SoC - to finish the PERST# reset, and then initialize the eye
diagram.
Increase the waiting time for the PERST# signals accordingly.
[bhelgaas: squash refcount fix from Wan Jiabing <wanjiabing@vivo.com>:
https://lore.kernel.org/r/
20211103062518.25695-1-wanjiabing@vivo.com
and drop "parent" refcount per
https://lore.kernel.org/all/
20211103143059.GA683503@bhelgaas/]
Link: https://lore.kernel.org/r/bb391a0e0f0863b66e645048315fab1a4f63f277.1634812676.git.mchehab+huawei@kernel.org
Link: https://lore.kernel.org/all/9a365cffe5af9ec5a1f79638968c3a2efa979b65.1634622716.git.mchehab+huawei@kernel.org/
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Alyssa Rosenzweig [Wed, 29 Sep 2021 16:38:38 +0000 (17:38 +0100)]
PCI: apple: Set up reference clocks when probing
Apple's PCIe controller requires clocks to be configured in order to
bring up the hardware. Add the register pokes required to do so.
Adapted from Corellium's driver via Mark Kettenis's U-Boot patches.
Co-developed-by: Stan Skowronek <stan@corellium.com>
Link: https://lore.kernel.org/r/20210929163847.2807812-6-maz@kernel.org
Signed-off-by: Stan Skowronek <stan@corellium.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Alyssa Rosenzweig [Wed, 29 Sep 2021 16:38:37 +0000 (17:38 +0100)]
PCI: apple: Add initial hardware bring-up
Add a minimal driver to bring up the PCIe bus on Apple system-on-chips,
particularly the Apple M1. This driver exposes the internal bus used for
the USB type-A ports, Ethernet, Wi-Fi, and Bluetooth. Bringing up the
radios requires additional drivers beyond what's necessary for PCIe itself.
Co-developed-by: Stan Skowronek <stan@corellium.com>
Link: https://lore.kernel.org/r/20210929163847.2807812-5-maz@kernel.org
Signed-off-by: Stan Skowronek <stan@corellium.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Marc Zyngier [Wed, 29 Sep 2021 16:38:36 +0000 (17:38 +0100)]
PCI: of: Allow matching of an interrupt-map local to a PCI device
Just as we now allow an interrupt map to be parsed when part of an
interrupt controller, there is no reason to ignore an interrupt map that
would be part of a pci device node such as a root port since we already
allow interrupt specifiers.
Allow the matching of such property when local to the node of a PCI
device, which allows the device itself to use the interrupt map for for
its own purpose.
Link: https://lore.kernel.org/r/20210929163847.2807812-4-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Marc Zyngier [Wed, 29 Sep 2021 16:38:35 +0000 (17:38 +0100)]
of/irq: Allow matching of an interrupt-map local to an interrupt controller
of_irq_parse_raw() has a baked assumption that if a node has an
interrupt-controller property, it cannot possibly also have an
interrupt-map property (the latter being ignored).
This seems to be an odd behaviour, and there is no reason why we should
avoid supporting this use case. This is specially useful when a PCI root
port acts as an interrupt controller for PCI endpoints, such as this:
pcie0: pcie@
690000000 {
[...]
port00: pci@0,0 {
device_type = "pci";
[...]
#address-cells = <3>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
<0 0 0 2 &port00 0 0 0 1>,
<0 0 0 3 &port00 0 0 0 2>,
<0 0 0 4 &port00 0 0 0 3>;
};
};
Handle it by detecting that we have an interrupt-map early in the parsing,
and special case the situation where the phandle in the interrupt map
refers to the current node (which is the interesting case here).
Link: https://lore.kernel.org/r/20210929163847.2807812-3-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Marc Zyngier [Wed, 29 Sep 2021 16:38:34 +0000 (17:38 +0100)]
irqdomain: Make of_phandle_args_to_fwspec() generally available
of_phandle_args_to_fwspec() can be generally useful to code extracting a DT
of_phandle and using an irq_fwspec to use the hierarchical irqdomain API.
Make it visible to the rest of the kernel, including modules.
Link: https://lore.kernel.org/r/20210929163847.2807812-2-maz@kernel.org
Tested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Selvin Xavier [Sat, 11 Sep 2021 10:03:05 +0000 (03:03 -0700)]
PCI: Do not enable AtomicOps on VFs
Host crashes when pci_enable_atomic_ops_to_root() is called for VFs with
virtual buses. The virtual buses added to SR-IOV have bus->self set to NULL
and host crashes due to this.
PID: 4481 TASK:
ffff89c6941b0000 CPU: 53 COMMAND: "bash"
...
#3 [
ffff9a9481713808] oops_end at
ffffffffb9025cd6
#4 [
ffff9a9481713828] page_fault_oops at
ffffffffb906e417
#5 [
ffff9a9481713888] exc_page_fault at
ffffffffb9a0ad14
#6 [
ffff9a94817138b0] asm_exc_page_fault at
ffffffffb9c00ace
[exception RIP: pcie_capability_read_dword+28]
RIP:
ffffffffb952fd5c RSP:
ffff9a9481713960 RFLAGS:
00010246
RAX:
0000000000000001 RBX:
ffff89c6b1096000 RCX:
0000000000000000
RDX:
ffff9a9481713990 RSI:
0000000000000024 RDI:
0000000000000000
RBP:
0000000000000080 R8:
0000000000000008 R9:
ffff89c64341a2f8
R10:
0000000000000002 R11:
0000000000000000 R12:
ffff89c648bab000
R13:
0000000000000000 R14:
0000000000000000 R15:
ffff89c648bab0c8
ORIG_RAX:
ffffffffffffffff CS: 0010 SS: 0018
#7 [
ffff9a9481713988] pci_enable_atomic_ops_to_root at
ffffffffb95359a6
#8 [
ffff9a94817139c0] bnxt_qplib_determine_atomics at
ffffffffc08c1a33 [bnxt_re]
#9 [
ffff9a94817139d0] bnxt_re_dev_init at
ffffffffc08ba2d1 [bnxt_re]
Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit in Device
Control 2 is reserved for VFs. The PF value applies to all associated VFs.
Return -EINVAL if pci_enable_atomic_ops_to_root() is called for a VF.
Link: https://lore.kernel.org/r/1631354585-16597-1-git-send-email-selvin.xavier@broadcom.com
Fixes:
35f5ace5dea4 ("RDMA/bnxt_re: Enable global atomic ops if platform supports")
Fixes:
430a23689dea ("PCI: Add pci_enable_atomic_ops_to_root()")
Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Gospodarek <gospo@broadcom.com>
Krzysztof Wilczyński [Wed, 13 Oct 2021 00:31:44 +0000 (00:31 +0000)]
PCI: vmd: Drop redundant includes of <asm/device.h>, <asm/msi.h>
We already include <linux/device.h> and <linux/msi.h>, which
include <asm/device.h> and <asm/msi.h>.
Drop the redundant includes of <asm/device.h> and <asm/msi.h>.
[bhelgaas: squash in fix from Wan Jiabing <wanjiabing@vivo.com>:
https://lore.kernel.org/r/
20211104063720.29375-1-wanjiabing@vivo.com]
Link: https://lore.kernel.org/r/20211013003145.1107148-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Derrick <jonathan.derrick@linux.dev>
Li Chen [Thu, 21 Oct 2021 02:50:19 +0000 (02:50 +0000)]
PCI: cadence: Add cdns_plat_pcie_probe() missing return
When cdns_plat_pcie_probe() succeeds, return success instead of falling
into the error handling code.
Fixes:
bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
Link: https://lore.kernel.org/r/DM6PR19MB40271B93057D949310F0B0EDA0BF9@DM6PR19MB4027.namprd19.prod.outlook.com
Signed-off-by: Xuliang Zhang <xlzhanga@ambarella.com>
Signed-off-by: Li Chen <lchen@ambarella.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Christophe JAILLET [Sun, 27 Jun 2021 11:46:24 +0000 (13:46 +0200)]
PCI: j721e: Fix j721e_pcie_probe() error path
If an error occurs after a successful cdns_pcie_init_phy() call, it must be
undone by a cdns_pcie_disable_phy() call, as already done above and below.
Update the goto to branch at the correct place of the error handling path.
Link: https://lore.kernel.org/r/db477b0cb444891a17c4bb424467667dc30d0bab.1624794264.git.christophe.jaillet@wanadoo.fr
Fixes:
49e0efdce791 ("PCI: j721e: Add support to provide refclk to PCIe connector")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Krzysztof Wilczyński [Wed, 13 Oct 2021 00:31:45 +0000 (00:31 +0000)]
PCI: cpqphp: Use <linux/io.h> instead of <asm/io.h>
Use the preferred generic header file linux/io.h that already includes the
corresponding asm/io.h file.
Link: https://lore.kernel.org/r/20211013003145.1107148-2-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Derrick <jonathan.derrick@linux.dev>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:10 +0000 (11:45 +0100)]
PCI: kirin: Use regmap for APB registers
The PHY layer need to access APB registers too, for Kirin 970. So place
them into a named regmap.
Link: https://lore.kernel.org/r/daf0e4bda5a69a5ac8484e70f09351a959805c8c.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:09 +0000 (11:45 +0100)]
PCI: kirin: Add support for a PHY layer
The pcie-kirin driver contains both PHY and generic PCI driver.
The best would be, instead, to support a PCI PHY driver, making the driver
more generic.
However, it is too late to remove the Kirin 960 PHY, as a change like that
would make the DT schema incompatible with past versions.
So, add support for an external PHY driver without removing the existing
Kirin 960 PHY from it.
Link: https://lore.kernel.org/r/f38361df2e9d0dc5a38ff942b631f7fef64cdc12.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Mauro Carvalho Chehab [Thu, 21 Oct 2021 10:45:08 +0000 (11:45 +0100)]
PCI: kirin: Reorganize the PHY logic inside the driver
The pcie-kirin PCIe driver contains internally a PHY interface for
Kirin 960.
As the next patches will add support for using an external PHY driver,
reorganize the driver in a way that the PHY part will be self-contained.
This could be moved to a separate PHY driver, but a change like that would
mean a non-backward-compatible DT schema change.
Link: https://lore.kernel.org/r/ad2f4aa6bbb71d5c9af0139704672f75f12644fc.1634812676.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Pali Rohár [Thu, 28 Oct 2021 18:56:59 +0000 (20:56 +0200)]
PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge
This register is exported at address offset 0x30.
Link: https://lore.kernel.org/r/20211028185659.20329-8-kabel@kernel.org
Fixes:
8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Pali Rohár [Thu, 28 Oct 2021 18:56:58 +0000 (20:56 +0200)]
PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge
Aardvark supports PCIe Hot Reset via PCIE_CORE_CTRL1_REG.
Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL
register on emulated bridge.
With this, the function pci_reset_secondary_bus() starts working and can
reset connected PCIe card. Custom userspace script [1] which uses setpci
can trigger PCIe Hot Reset and reset the card manually.
[1] https://alexforencich.com/wiki/en/pcie/hot-reset-linux
Link: https://lore.kernel.org/r/20211028185659.20329-7-kabel@kernel.org
Fixes:
8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Pali Rohár [Thu, 28 Oct 2021 18:56:57 +0000 (20:56 +0200)]
PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge
Aardvark controller has something like config space of a Root Port
available at offset 0x0 of internal registers - these registers are used
for implementation of the emulated bridge.
The default value of Class Code of this bridge corresponds to a RAID Mass
storage controller, though. (This is probably intended for when the
controller is used as Endpoint.)
Change the Class Code to correspond to a PCI Bridge.
Add comment explaining this change.
Link: https://lore.kernel.org/r/20211028185659.20329-6-kabel@kernel.org
Fixes:
8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Pali Rohár [Thu, 28 Oct 2021 18:56:56 +0000 (20:56 +0200)]
PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge
From very vague, ambiguous and incomplete information from Marvell we
deduced that the 32-bit Aardvark register at address 0x4
(PCIE_CORE_CMD_STATUS_REG), which is not documented for Root Complex mode
in the Functional Specification (only for Endpoint mode), controls two
16-bit PCIe registers: Command Register and Status Registers of PCIe Root
Port.
This means that bit 2 controls bus mastering and forwarding of memory and
I/O requests in the upstream direction. According to PCI specifications
bits [0:2] of Command Register, this should be by default disabled on
reset. So explicitly disable these bits at early setup of the Aardvark
driver.
Remove code which unconditionally enables all 3 bits and let kernel code
(via pci_set_master() function) to handle bus mastering of Root PCIe
Bridge via emulated PCI_COMMAND on emulated bridge.
Link: https://lore.kernel.org/r/20211028185659.20329-5-kabel@kernel.org
Fixes:
8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org # b2a56469d550 ("PCI: aardvark: Add FIXME comment for PCIE_CORE_CMD_STATUS_REG access")
Marek Behún [Thu, 28 Oct 2021 18:56:55 +0000 (20:56 +0200)]
PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REG
The PCIE_MSI_PAYLOAD_REG contains 16-bit MSI number, not only lower
8 bits. Fix reading content of this register and add a comment
describing the access to this register.
Link: https://lore.kernel.org/r/20211028185659.20329-4-kabel@kernel.org
Fixes:
8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Marek Behún [Thu, 28 Oct 2021 18:56:54 +0000 (20:56 +0200)]
PCI: aardvark: Fix return value of MSI domain .alloc() method
MSI domain callback .alloc() (implemented by advk_msi_irq_domain_alloc()
function) should return zero on success, since non-zero value indicates
failure.
When the driver was converted to generic MSI API in commit
f21a8b1b6837
("PCI: aardvark: Move to MSI handling using generic MSI support"), it
was converted so that it returns hwirq number.
Fix this.
Link: https://lore.kernel.org/r/20211028185659.20329-3-kabel@kernel.org
Fixes:
f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Marek Behún [Thu, 28 Oct 2021 18:56:53 +0000 (20:56 +0200)]
PCI: pci-bridge-emul: Fix emulation of W1C bits
The pci_bridge_emul_conf_write() function correctly clears W1C bits in
cfgspace cache, but it does not inform the underlying implementation
about the clear request: the .write_op() method is given the value with
these bits cleared.
This is wrong if the .write_op() needs to know which bits were requested
to be cleared.
Fix the value to be passed into the .write_op() method to have requested
W1C bits set, so that it can clear them.
Both pci-bridge-emul users (mvebu and aardvark) are compatible with this
change.
Link: https://lore.kernel.org/r/20211028185659.20329-2-kabel@kernel.org
Fixes:
23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Cc: Russell King <rmk+kernel@armlinux.org.uk>
Krzysztof Wilczyński [Wed, 27 Oct 2021 10:50:41 +0000 (10:50 +0000)]
MAINTAINERS: Update PCI subsystem information
Update the following information related to the PCI subsystem which
includes the PCI drivers, PCI native host bridge and endpoint drivers,
and the PCI endpoint sub-system:
- Sort fields as per preferred order
- Sort files in the alphabetical order
- Update old Patchwork URLs
- Update Git repository for the PCI endpoint subsystem
- Add Bugzilla link
- Add link to the official IRC channel
- Add files "drivers/pci/pci-bridge-emul.{c,h}" to the right
section so that proper ownership is returned for both files
from the get_maintainer.pl script
Link: https://lore.kernel.org/r/20211027105041.24087-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Krzysztof Wilczyński [Wed, 13 Oct 2021 01:41:36 +0000 (01:41 +0000)]
PCI: Prefer 'unsigned int' over bare 'unsigned'
The bare "unsigned" type implicitly means "unsigned int", but the preferred
coding style is to use the complete type name.
Update the bare use of "unsigned" to the preferred "unsigned int".
No change to functionality intended.
See
a1ce18e4f941 ("checkpatch: warn on bare unsigned or signed declarations
without int").
Link: https://lore.kernel.org/r/20211013014136.1117543-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Colin Ian King [Fri, 10 Sep 2021 16:14:17 +0000 (17:14 +0100)]
PCI: Remove redundant 'rc' initialization
The variable 'rc' is being initialized with a value that is never read.
Remove the redundant assignment.
Addresses-Coverity: ("Unused value")
Link: https://lore.kernel.org/r/20210910161417.91001-1-colin.king@canonical.com
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Heiner Kallweit [Fri, 10 Sep 2021 06:27:08 +0000 (08:27 +0200)]
cxgb3: Remove seeprom_write and use VPD API
Using the VPD API allows to simplify the code and completely get
rid of t3_seeprom_write().
Link: https://lore.kernel.org/r/a0291004-dda3-ea08-4d6c-a2f8826c8527@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jakub Kicinski <kuba@kernel.org>
Heiner Kallweit [Fri, 10 Sep 2021 06:25:49 +0000 (08:25 +0200)]
cxgb3: Use VPD API in t3_seeprom_wp()
Use standard VPD API to replace t3_seeprom_write(), this prepares for
removing this function. Chelsio T3 maps the EEPROM write protect flag
to an arbitrary place in VPD address space, therefore we have to use
pci_write_vpd_any().
Link: https://lore.kernel.org/r/f768fdbe-3a16-d539-57d2-c7c908294336@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jakub Kicinski <kuba@kernel.org>
Heiner Kallweit [Fri, 10 Sep 2021 06:24:07 +0000 (08:24 +0200)]
cxgb3: Remove t3_seeprom_read and use VPD API
Using the VPD API allows to simplify the code and completely get rid
of t3_seeprom_read(). Note that we don't have to use pci_read_vpd_any()
here because a VPD quirk sets dev->vpd.len to the full EEPROM size.
Tested with a T320 card.
Link: https://lore.kernel.org/r/68ef15bb-b6bf-40ad-160c-aaa72c4a70f8@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jakub Kicinski <kuba@kernel.org>
Heiner Kallweit [Fri, 10 Sep 2021 06:22:49 +0000 (08:22 +0200)]
PCI/VPD: Use pci_read_vpd_any() in pci_vpd_size()
Use new function pci_read_vpd_any() to simplify the code.
[bhelgaas: squash in fix for stack overflow reported & tested by
Qian [1] and Kunihiko [2]:
[1] https://lore.kernel.org/netdev/
e89087c5-c495-c5ca-feb1-
54cf3a8775c5@quicinc.com/
[2] https://lore.kernel.org/r/
2f7e3770-ab47-42b5-719c-
f7c661c07d28@socionext.com
Link: https://lore.kernel.org/r/6211be8a-5d10-8f3a-6d33-af695dc35caf@gmail.com
Reported-by: Qian Cai <quic_qiancai@quicinc.com>
Tested-by: Qian Cai <quic_qiancai@quicinc.com>
Reported-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Tested-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
]
Link: https://lore.kernel.org/r/049fa71c-c7af-9c69-51c0-05c1bc2bf660@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jakub Kicinski <kuba@kernel.org>
Sergio Paracuellos [Wed, 22 Sep 2021 05:00:35 +0000 (07:00 +0200)]
MAINTAINERS: Add Sergio Paracuellos as MT7621 PCIe maintainer
Add myself as maintainer of the PCIe Controller driver for MT7621 SoCs.
Link: https://lore.kernel.org/r/20210922050035.18162-4-sergio.paracuellos@gmail.com
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Sergio Paracuellos [Wed, 22 Sep 2021 05:00:34 +0000 (07:00 +0200)]
PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
Add driver for the PCIe controller of the MT7621 SoC.
[bhelgaas: rename from pci-mt7621.c to pcie-mt7621.c; also rename Kconfig
symbol from PCI_MT7621 to PCIE_MT7621]
Link: https://lore.kernel.org/r/20210922050035.18162-3-sergio.paracuellos@gmail.com
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Sergio Paracuellos [Wed, 22 Sep 2021 05:00:33 +0000 (07:00 +0200)]
dt-bindings: PCI: Add MT7621 SoC PCIe host controller
Add device tree binding documentation for PCIe in MT7621 SoCs.
Link: https://lore.kernel.org/r/20210922050035.18162-2-sergio.paracuellos@gmail.com
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Mingchuang Qiao [Tue, 12 Oct 2021 07:56:14 +0000 (15:56 +0800)]
PCI: Re-enable Downstream Port LTR after reset or hotplug
Per PCIe r5.0, sec 7.5.3.16, Downstream Ports must disable LTR if the link
goes down (the Port goes DL_Down status). This is a problem because the
Downstream Port's dev->ltr_path is still set, so we think LTR is still
enabled, and we enable LTR in the Endpoint. When it sends LTR messages,
they cause Unsupported Request errors at the Downstream Port.
This happens in the reset path, where we may enable LTR in
pci_restore_pcie_state() even though the Downstream Port disabled LTR
because the reset caused a link down event.
It also happens in the hot-remove and hot-add path, where we may enable LTR
in pci_configure_ltr() even though the Downstream Port disabled LTR when
the hot-remove took the link down.
In these two scenarios, check the upstream bridge and restore its LTR
enable if appropriate.
The Unsupported Request may be logged by AER as follows:
pcieport 0000:00:1d.0: AER: Uncorrected (Non-Fatal) error received: id=00e8
pcieport 0000:00:1d.0: PCIe Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, id=00e8(Requester ID)
pcieport 0000:00:1d.0: device [8086:9d18] error status/mask=
00100000/
00010000
pcieport 0000:00:1d.0: [20] Unsupported Request (First)
In addition, if LTR is not configured correctly, the link cannot enter the
L1.2 state, which prevents some machines from entering the S0ix low power
state.
[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20211012075614.54576-1-mingchuang.qiao@mediatek.com
Reported-by: Utkarsh H Patel <utkarsh.h.patel@intel.com>
Signed-off-by: Mingchuang Qiao <mingchuang.qiao@mediatek.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Barry Song [Wed, 25 Aug 2021 10:26:35 +0000 (18:26 +0800)]
PCI/sysfs: Explicitly show first MSI IRQ for 'irq'
The sysfs "irq" file contains the legacy INTx IRQ. Or, if the device has
MSI enabled, it contains the first MSI IRQ instead.
Previously this file showed the pci_dev.irq value directly. But we'd
prefer to use pci_dev.irq only for the INTx IRQ and decouple that from any
MSI or MSI-X IRQs.
If the device has MSI enabled, explicitly look up and show the first MSI
IRQ in the sysfs "irq" file. Otherwise, show the INTx IRQ.
This removes the requirement that msi_capability_init() set pci_dev.irq to
the first MSI IRQ when enabling MSI and pci_msi_shutdown() restore the INTx
IRQ when disabling MSI.
[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20210825102636.52757-3-21cnbao@gmail.com
Signed-off-by: Barry Song <song.bao.hua@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Barry Song [Wed, 25 Aug 2021 10:26:34 +0000 (18:26 +0800)]
PCI: Document /sys/bus/pci/devices/.../irq
Document /sys/bus/pci/devices/.../irq.
This file contains the IRQ of the INTx interrupt (or zero if the device
doesn't support INTx interrupts).
If the device has enabled MSI (not MSI-X), it contains the first MSI IRQ
instead. This is a historical mistake because devices may support several
MSI or MSI-X vectors, and this file can't contain them all. But we
preserve this behavior to avoid breaking userspace.
[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20210825102636.52757-2-21cnbao@gmail.com
Signed-off-by: Barry Song <song.bao.hua@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cai Huoqing [Mon, 18 Oct 2021 12:41:09 +0000 (20:41 +0800)]
PCI: Remove unused pci_pool wrappers
The pci_pool users have been converted to dma_pool. Remove the unused
pci_pool wrappers.
Link: https://lore.kernel.org/r/20211018124110.214-1-caihuoqing@baidu.com
Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Uwe Kleine-König [Mon, 4 Oct 2021 12:59:35 +0000 (14:59 +0200)]
PCI: Remove struct pci_dev->driver
There are no remaining uses of the struct pci_dev->driver pointer, so
remove it.
Link: https://lore.kernel.org/r/20211004125935.2300113-12-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Uwe Kleine-König [Tue, 12 Oct 2021 21:11:24 +0000 (16:11 -0500)]
PCI: Use to_pci_driver() instead of pci_dev->driver
Struct pci_driver contains a struct device_driver, so for PCI devices, it's
easy to convert a device_driver * to a pci_driver * with to_pci_driver().
The device_driver * is in struct device, so we don't need to also keep
track of the pci_driver * in struct pci_dev.
Replace pci_dev->driver with to_pci_driver(). This is a step toward
removing pci_dev->driver.
[bhelgaas: split to separate patch]
Link: https://lore.kernel.org/r/20211004125935.2300113-11-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Uwe Kleine-König [Tue, 12 Oct 2021 21:05:47 +0000 (16:05 -0500)]
x86/pci/probe_roms: Use to_pci_driver() instead of pci_dev->driver
Struct pci_driver contains a struct device_driver, so for PCI devices, it's
easy to convert a device_driver * to a pci_driver * with to_pci_driver().
The device_driver * is in struct device, so we don't need to also keep
track of the pci_driver * in struct pci_dev.
Replace pdev->driver with to_pci_driver(). This is a step toward removing
pci_dev->driver.
[bhelgaas: split to separate patch]
Link: https://lore.kernel.org/r/20211004125935.2300113-11-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Uwe Kleine-König [Tue, 12 Oct 2021 21:38:32 +0000 (16:38 -0500)]
perf/x86/intel/uncore: Use to_pci_driver() instead of pci_dev->driver
Struct pci_driver contains a struct device_driver, so for PCI devices, it's
easy to convert a device_driver * to a pci_driver * with to_pci_driver().
The device_driver * is in struct device, so we don't need to also keep
track of the pci_driver * in struct pci_dev.
Replace pdev->driver with to_pci_driver(). This is a step toward removing
pci_dev->driver.
[bhelgaas: split to separate patch]
Link: https://lore.kernel.org/r/20211004125935.2300113-11-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Uwe Kleine-König [Tue, 12 Oct 2021 21:37:55 +0000 (16:37 -0500)]
powerpc/eeh: Use to_pci_driver() instead of pci_dev->driver
Struct pci_driver contains a struct device_driver, so for PCI devices, it's
easy to convert a device_driver * to a pci_driver * with to_pci_driver().
The device_driver * is in struct device, so we don't need to also keep
track of the pci_driver * in struct pci_dev.
Replace pdev->driver with to_pci_driver(). This is a step toward removing
pci_dev->driver.
[bhelgaas: split to separate patch]
Link: https://lore.kernel.org/r/20211004125935.2300113-11-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Uwe Kleine-König [Tue, 12 Oct 2021 21:36:05 +0000 (16:36 -0500)]
usb: xhci: Use to_pci_driver() instead of pci_dev->driver
Struct pci_driver contains a struct device_driver, so for PCI devices, it's
easy to convert a device_driver * to a pci_driver * with to_pci_driver().
The device_driver * is in struct device, so we don't need to also keep
track of the pci_driver * in struct pci_dev.
Replace pdev->driver with to_pci_driver(). This is a step toward removing
pci_dev->driver.
[bhelgaas: split to separate patch]
Link: https://lore.kernel.org/r/20211004125935.2300113-11-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Uwe Kleine-König [Tue, 12 Oct 2021 21:03:39 +0000 (16:03 -0500)]
cxl: Use to_pci_driver() instead of pci_dev->driver
Struct pci_driver contains a struct device_driver, so for PCI devices, it's
easy to convert a device_driver * to a pci_driver * with to_pci_driver().
The device_driver * is in struct device, so we don't need to also keep
track of the pci_driver * in struct pci_dev.
Replace pdev->driver with to_pci_driver(). This is a step toward removing
pci_dev->driver.
[bhelgaas: split to separate patch]
Link: https://lore.kernel.org/r/20211004125935.2300113-11-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Tue, 12 Oct 2021 20:51:32 +0000 (15:51 -0500)]
cxl: Factor out common dev->driver expressions
Save the struct pci_driver and struct pci_error_handlers pointers from
pdev->driver instead of chasing the pointers several times. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Lukas Wunner [Sat, 31 Jul 2021 12:39:04 +0000 (14:39 +0200)]
PCI/ERR: Reduce compile time for CONFIG_PCIEAER=n
The sole non-static function in err.c, pcie_do_recovery(), is only
called from:
* aer.c (if CONFIG_PCIEAER=y)
* dpc.c (if CONFIG_PCIE_DPC=y, which depends on CONFIG_PCIEAER)
* edr.c (if CONFIG_PCIE_EDR=y, which depends on CONFIG_PCIE_DPC)
Thus, err.c need not be compiled if CONFIG_PCIEAER=n.
Also, pci_uevent_ers() and pcie_clear_device_status(), which are called
from err.c, can be #ifdef'ed away unless CONFIG_PCIEAER=y.
Since x86_64_defconfig doesn't enable CONFIG_PCIEAER, this change may
slightly reduce compile time for anyone doing a test build with that
config.
Link: https://lore.kernel.org/r/98f9041151268c1c035ab64cca320ad86803f64a.1627638184.git.lukas@wunner.de
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Lukas Wunner [Sat, 31 Jul 2021 12:39:03 +0000 (14:39 +0200)]
PCI/portdrv: Remove unused pcie_port_bus_{,un}register() declarations
Commit
c6c889d932bb ("PCI/portdrv: Remove pcie_port_bus_type link order
dependency") removed pcie_port_bus_{,un}register() but erroneously
retained their declarations in portdrv.h. Remove them as well.
Link: https://lore.kernel.org/r/7fd76b0591c37287ab94d911d8fd9ab9a2afcd16.1627638184.git.lukas@wunner.de
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Lukas Wunner [Sat, 31 Jul 2021 12:39:02 +0000 (14:39 +0200)]
PCI/portdrv: Remove unused resume err_handler
Commit
3e41a317ae45 ("PCI/AER: Remove unused aer_error_resume()")
removed the resume err_handler from AER. Since no other port service
implements the callback, support for it can be removed from portdrv.
It can be revived later if need be, preferably by re-using the
pcie_port_device_iter() iterator.
Link: https://lore.kernel.org/r/25334149b604e005058aeb0fdf51e01f991d5d74.1627638184.git.lukas@wunner.de
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Keith Busch <kbusch@kernel.org>
Lukas Wunner [Sat, 31 Jul 2021 12:39:01 +0000 (14:39 +0200)]
PCI: pciehp: Ignore Link Down/Up caused by error-induced Hot Reset
Stuart Hayes reports that an error handled by DPC at a Root Port results
in pciehp gratuitously bringing down a subordinate hotplug port:
RP -- UP -- DP -- UP -- DP (hotplug) -- EP
pciehp brings the slot down because the Link to the Endpoint goes down.
That is caused by a Hot Reset being propagated as a result of DPC.
Per PCIe Base Spec 5.0, section 6.6.1 "Conventional Reset":
For a Switch, the following must cause a hot reset to be sent on all
Downstream Ports: [...]
* The Data Link Layer of the Upstream Port reporting DL_Down status.
In Switches that support Link speeds greater than 5.0 GT/s, the
Upstream Port must direct the LTSSM of each Downstream Port to the
Hot Reset state, but not hold the LTSSMs in that state. This permits
each Downstream Port to begin Link training immediately after its
hot reset completes. This behavior is recommended for all Switches.
* Receiving a hot reset on the Upstream Port.
Once DPC recovers, pcie_do_recovery() walks down the hierarchy and
invokes pcie_portdrv_slot_reset() to restore each port's config space.
At that point, a hotplug interrupt is signaled per PCIe Base Spec r5.0,
section 6.7.3.4 "Software Notification of Hot-Plug Events":
If the Port is enabled for edge-triggered interrupt signaling using
MSI or MSI-X, an interrupt message must be sent every time the logical
AND of the following conditions transitions from FALSE to TRUE: [...]
* The Hot-Plug Interrupt Enable bit in the Slot Control register is
set to 1b.
* At least one hot-plug event status bit in the Slot Status register
and its associated enable bit in the Slot Control register are both
set to 1b.
Prevent pciehp from gratuitously bringing down the slot by clearing the
error-induced Data Link Layer State Changed event before restoring
config space. Afterwards, check whether the link has unexpectedly
failed to retrain and synthesize a DLLSC event if so.
Allow each pcie_port_service_driver (one of them being pciehp) to define
a slot_reset callback and re-use the existing pm_iter() function to
iterate over the callbacks.
Thereby, the Endpoint driver remains bound throughout error recovery and
may restore the device to working state.
Surprise removal during error recovery is detected through a Presence
Detect Changed event. The hotplug port is expected to not signal that
event as a result of a Hot Reset.
The issue isn't DPC-specific, it also occurs when an error is handled by
AER through aer_root_reset(). So while the issue was noticed only now,
it's been around since 2006 when AER support was first introduced.
[bhelgaas: drop PCI_ERROR_RECOVERY Kconfig, split pm_iter() rename to
preparatory patch]
Link: https://lore.kernel.org/linux-pci/08c046b0-c9f2-3489-eeef-7e7aca435bb9@gmail.com/
Fixes:
6c2b374d7485 ("PCI-Express AER implemetation: AER core and aerdriver")
Link: https://lore.kernel.org/r/251f4edcc04c14f873ff1c967bc686169cd07d2d.1627638184.git.lukas@wunner.de
Reported-by: Stuart Hayes <stuart.w.hayes@gmail.com>
Tested-by: Stuart Hayes <stuart.w.hayes@gmail.com>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org # v2.6.19+: ba952824e6c1: PCI/portdrv: Report reset for frozen channel
Cc: Keith Busch <kbusch@kernel.org>
Lukas Wunner [Fri, 15 Oct 2021 18:58:40 +0000 (13:58 -0500)]
PCI/portdrv: Rename pm_iter() to pcie_port_device_iter()
Rename pm_iter() to pcie_port_device_iter() and make it visible outside
CONFIG_PM and portdrv_core.c so it can be used for pciehp slot reset
recovery.
[bhelgaas: split into its own patch]
Link: https://lore.kernel.org/linux-pci/08c046b0-c9f2-3489-eeef-7e7aca435bb9@gmail.com/
Link: https://lore.kernel.org/r/251f4edcc04c14f873ff1c967bc686169cd07d2d.1627638184.git.lukas@wunner.de
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Uwe Kleine-König [Tue, 12 Oct 2021 21:35:34 +0000 (16:35 -0500)]
xen/pcifront: Use to_pci_driver() instead of pci_dev->driver
Struct pci_driver contains a struct device_driver, so for PCI devices, it's
easy to convert a device_driver * to a pci_driver * with to_pci_driver().
The device_driver * is in struct device, so we don't need to also keep
track of the pci_driver * in struct pci_dev.
Replace pdev->driver with to_pci_driver(). This is a step toward removing
pci_dev->driver.
[bhelgaas: split to separate patch]
Link: https://lore.kernel.org/r/20211004125935.2300113-11-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Uwe Kleine-König [Fri, 8 Oct 2021 23:22:08 +0000 (18:22 -0500)]
xen/pcifront: Drop pcifront_common_process() tests of pcidev, pdrv
pcifront_common_process() exits early if pcidev or pcidev->driver are NULL,
so simplify it by not checking them again.
[bhelgaas: split flag change to separate patch]
Link: https://lore.kernel.org/r/20211004125935.2300113-4-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Kunihiko Hayashi [Sat, 18 Sep 2021 00:22:59 +0000 (09:22 +0900)]
PCI: uniphier: Serialize INTx masking/unmasking and fix the bit operation
The condition register PCI_RCV_INTX is used in irq_mask() and irq_unmask()
callbacks. Accesses to register can occur at the same time without a lock.
Add a lock into each callback to prevent the issue.
And INTX mask and unmask fields in PCL_RCV_INTX register should only be
set/reset for each bit. Clearing by PCL_RCV_INTX_ALL_MASK should be
removed.
INTX status fields in PCL_RCV_INTX register only indicates each INTX
interrupt status, so the handler can't clear by writing 1 to the field.
The status is expected to be cleared by the interrupt origin.
The ack function has no meaning, so should remove it.
Suggested-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/1631924579-24567-1-git-send-email-hayashi.kunihiko@socionext.com
Fixes:
7e6d5cd88a6f ("PCI: uniphier: Add UniPhier PCIe host controller support")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Pali Rohár <pali@kernel.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Bjorn Andersson [Mon, 23 Aug 2021 15:49:58 +0000 (08:49 -0700)]
PCI: qcom: Add sc8180x compatible
The SC8180x platform comes with 4 PCIe controllers, typically used for
things such as NVME storage or connecting a SDX55 5G modem. Add a
compatible for this, that just reuses the 1.9.0 ops.
Link: https://lore.kernel.org/linux-arm-msm/20210725040038.3966348-4-bjorn.andersson@linaro.org/
Link: https://lore.kernel.org/r/20210823154958.305677-2-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[lorenzo.pieralisi@arm.com: updated match data structure]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Prasad Malisetty [Thu, 7 Oct 2021 17:48:43 +0000 (23:18 +0530)]
PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
On the SC7280, the clock source for gcc_pcie_1_pipe_clk_src must be the
TCXO while gdsc is enabled. After PHY init successful clock source should
switch to pipe clock for gcc_pcie_1_pipe_clk_src.
Link: https://lore.kernel.org/r/1633628923-25047-6-git-send-email-pmaliset@codeaurora.org
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Prasad Malisetty [Thu, 7 Oct 2021 17:48:42 +0000 (23:18 +0530)]
PCI: qcom: Replace ops with struct pcie_cfg in pcie match data
Add struct qcom_pcie_cfg as match data for all platforms. Assign
appropriate platform ops into struct qcom_pcie_cfg and read using
of_device_get_match_data() in qcom_pcie_probe().
Link: https://lore.kernel.org/r/1633628923-25047-5-git-send-email-pmaliset@codeaurora.org
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Logan Gunthorpe [Thu, 14 Oct 2021 14:18:59 +0000 (14:18 +0000)]
PCI/switchtec: Add check of event support
Not all events are supported by every gen/variant of the Switchtec
firmware. To solve this, since Gen4, a new bit in each event header
is introduced to indicate if an event is supported by the firmware.
Link: https://lore.kernel.org/r/20211014141859.11444-6-kelvin.cao@microchip.com
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kelvin Cao [Thu, 14 Oct 2021 14:18:58 +0000 (14:18 +0000)]
PCI/switchtec: Replace ENOTSUPP with EOPNOTSUPP
ENOTSUPP is not a SUSV4 error code, and the following checkpatch.pl
warning will be given for new patches which still use ENOTSUPP.
WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
See the link below for the discussion.
https://lore.kernel.org/netdev/
20200511165319.2251678-1-kuba@kernel.org/
Replace ENOTSUPP with EOPNOTSUPP to align with future patches which will
be using EOPNOTSUPP.
Link: https://lore.kernel.org/r/20211014141859.11444-5-kelvin.cao@microchip.com
Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kelvin Cao [Thu, 14 Oct 2021 14:18:57 +0000 (14:18 +0000)]
PCI/switchtec: Update the way of getting management VEP instance ID
Gen4 firmware adds DMA VEP and NVMe VEP support in VEP (virtual EP)
instance ID register in addtion to management EP, update the way of
getting management VEP instance ID.
Link: https://lore.kernel.org/r/20211014141859.11444-4-kelvin.cao@microchip.com
Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kelvin Cao [Thu, 14 Oct 2021 14:18:56 +0000 (14:18 +0000)]
PCI/switchtec: Fix a MRPC error status handling issue
If an error is encountered when executing a MRPC command, the firmware
will set the status register to SWITCHTEC_MRPC_STATUS_ERROR and return
the error code in the return value register.
Add handling of SWITCHTEC_MRPC_STATUS_ERROR on status register when
completing a MRPC command.
Link: https://lore.kernel.org/r/20211014141859.11444-3-kelvin.cao@microchip.com
Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kelvin Cao [Thu, 14 Oct 2021 14:18:55 +0000 (14:18 +0000)]
PCI/switchtec: Error out MRPC execution when MMIO reads fail
A firmware hard reset may be initiated by various mechanisms including a
UART interface, TWI sideband interface from BMC, MRPC command from
userspace, etc. The switchtec management driver is unaware of these
resets.
The reset clears PCI state including the BARs and Memory Space Enable
bits, so the device no longer responds to the MMIO accesses the driver
uses to operate it.
MMIO reads to the device will fail with a PCIe error. When the root
complex handles that error, it typically fabricates ~0 data to complete
the CPU read.
Check for this sort of error by reading the device ID from MMIO space.
This ID can never be ~0, so if we see that value, it probably means the
PCIe Memory Read failed and we should return an error indication to the
application using the switchtec driver.
Link: https://lore.kernel.org/r/20211014141859.11444-2-kelvin.cao@microchip.com
Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Johannes Berg [Wed, 11 Aug 2021 14:25:30 +0000 (16:25 +0200)]
PCI: vmd: depend on !UML
With UML having enabled (simulated) PCI on UML, VMD breaks
allyesconfig/allmodconfig compilation because it assumes
it's running on X86_64 bare metal, and has hardcoded API
use of ARCH=x86. Make it depend on !UML to fix this.
Link: https://lore.kernel.org/r/20210811162530.affe26231bc3.I131b3c1e67e3d2ead6e98addd256c835fbef9a3e@changeid
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Jon Derrick <jonathan.derrick@intel.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Simon Xue [Wed, 18 Aug 2021 09:34:06 +0000 (17:34 +0800)]
dt-bindings: rockchip: Add DesignWare based PCIe controller
Document DT bindings for PCIe controller found on Rockchip SoC.
Link: https://lore.kernel.org/r/20210818093406.157788-1-xxm@rock-chips.com
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>