Vinson Lee [Sun, 27 Mar 2022 21:05:00 +0000 (14:05 -0700)]
pvr: Remove duplicate variable queue_create.
Fix defect reported by Coverity Scan.
Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In queue_create = queue_create = &pCreateInfo->pQueueCreateInfos[0], queue_create is written twice with the same value.
Fixes:
8991e646411 ("pvr: Add a Vulkan driver for Imagination Technologies PowerVR Rogue GPUs")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15604>
Danylo Piliaiev [Thu, 24 Mar 2022 09:49:50 +0000 (11:49 +0200)]
turnip: enable has_ccu_flush_bug workaround for a660
It seems that a660 has the same bug. Without the workaround there
are a lot of flakes with depth-stencil tests, e.g. in:
dEQP-VK.pipeline.extended_dynamic_state.*
dEQP-VK.renderpass.depth_stencil_write_conditions.*
dEQP-VK.pipeline.stencil.format.d24_unorm_s8_uint.states.*
Or guaranteed failures like of:
dEQP-VK.pipeline.render_to_image.core.2d.huge.width.r8g8b8a8_unorm_d32_sfloat_s8_uint
Enabling the workaround fixes all of them.
cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15548>
Tales Lelo da Aparecida [Sun, 27 Mar 2022 01:08:30 +0000 (22:08 -0300)]
zink: validate and log errors on vulkan calls
This commit also replaces debug_printf with mesa_loge
Signed-off-by: Tales Lelo da Aparecida <tales.aparecida@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15601>
Mihai Preda [Mon, 28 Mar 2022 06:22:34 +0000 (09:22 +0300)]
radeonsi/tests: update baseline and flakes on vega20
The piglit suite was run on vega20, 10 times, on a 'debugoptimized' mesa build
at commit
582e7f15 . The inconsistent failures were added to the flakes file.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15487>
Mihai Preda [Mon, 28 Mar 2022 06:08:34 +0000 (09:08 +0300)]
radeonsi/tests: add flakes option to radeonsi-run-tests.py
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15487>
Mihai Preda [Mon, 28 Mar 2022 06:05:30 +0000 (09:05 +0300)]
radeonsi/tests: fix file left open in radeonsi-run-tests.py
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15487>
Mike Blumenkrantz [Mon, 28 Mar 2022 03:05:07 +0000 (23:05 -0400)]
zink: run piglit's gpu profile
increase coverage
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15606>
Konstantin Seurer [Mon, 28 Mar 2022 14:05:10 +0000 (16:05 +0200)]
venus: Use trivial common entrypoints
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15613>
Konstantin Seurer [Sun, 27 Mar 2022 20:28:24 +0000 (22:28 +0200)]
radv: Use common GetPhysicalDeviceMemoryProperties
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15613>
Mike Blumenkrantz [Tue, 22 Mar 2022 20:46:23 +0000 (16:46 -0400)]
lavapipe: run optimize loop before krangling pipeline layout
in scenarios like:
vec1 32 ssa_151 = deref_var &shadow_map (uniform sampler2D)
vec1 32 ssa_152 = deref_var &shadow_map (uniform sampler2D)
vec2 32 ssa_153 = vec2 ssa_151, ssa_152
vec1 32 ssa_154 = deref_var ¶m@4 (function_temp uvec2)
intrinsic store_deref (ssa_154, ssa_153) (wrmask=xy /*3*/, access=0)
vec1 32 ssa_160 = deref_var ¶m@4 (function_temp uvec2)
vec2 32 ssa_164 = intrinsic load_deref (ssa_160) (access=0)
vec1 32 ssa_167 = mov ssa_164.x
vec1 32 ssa_168 = deref_cast (texture2D *)ssa_167 (uniform texture2D) /* ptr_stride=0, align_mul=0, align_offset=0 */
vec1 32 ssa_169 = mov ssa_164.y
vec1 32 ssa_170 = deref_cast (sampler *)ssa_169 (uniform sampler) /* ptr_stride=0, align_mul=0, align_offset=0 */
vec1 32 ssa_172 = (float32)tex ssa_168 (texture_deref), ssa_170 (sampler_deref), ssa_171 (coord), ssa_166 (comparator)
the real variable is stored to a function_temp and then loaded back again,
which means it isn't a direct deref and lower_vri_instr_tex_deref() will
crash because the variable can't be found
BUT running only the passes needed to eliminate derefs will break other tests,
so just run the whole optimize loop again here to avoid such issues
for #5945
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15511>
Mike Blumenkrantz [Mon, 28 Mar 2022 21:47:42 +0000 (17:47 -0400)]
zink: add a couple flakes
unsure what caused these but they started a week ago and were first seen
in https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
19950494
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15621>
Yiwei Zhang [Mon, 28 Mar 2022 20:35:08 +0000 (20:35 +0000)]
venus: let vn_android use vn_BindImageMemory2 and directly use reqs
v2: remove an unused variable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15619>
Timur Kristóf [Mon, 28 Mar 2022 18:07:23 +0000 (20:07 +0200)]
radv: Use correct buffer offset for conditional rendering.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15615>
Georg Lehmann [Thu, 20 Jan 2022 19:50:15 +0000 (20:50 +0100)]
radv, aco: Packed iadd_sat/uadd_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15421>
Georg Lehmann [Sat, 20 Nov 2021 13:24:49 +0000 (14:24 +0100)]
radv: Lower 64bit iadd_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15421>
Georg Lehmann [Fri, 24 Dec 2021 14:12:17 +0000 (15:12 +0100)]
aco: Implement scalar iadd_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15421>
Georg Lehmann [Sat, 20 Nov 2021 15:29:50 +0000 (16:29 +0100)]
aco: Implement 64bit uadd_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15421>
Georg Lehmann [Sat, 20 Nov 2021 13:23:20 +0000 (14:23 +0100)]
nir: Add an option to lower 64bit iadd_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15421>
Georg Lehmann [Mon, 17 Jan 2022 17:11:27 +0000 (18:11 +0100)]
nir: Move lower_usub_sat64 to nir_lower_int64_options.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15421>
Georg Lehmann [Fri, 11 Feb 2022 00:10:14 +0000 (01:10 +0100)]
aco: Remove 0 data components from image stores.
Image stores always write a full texel.
The hardware writes zero for components not included in dmask.
Totals from 387 (0.29% of 134913) affected shaders: (GFX10.3)
VGPRs: 17216 -> 17136 (-0.46%)
CodeSize: 1987652 -> 1981504 (-0.31%)
MaxWaves: 9054 -> 9058 (+0.04%)
Instrs: 361883 -> 361115 (-0.21%); split: -0.21%, +0.00%
Latency: 5383187 -> 5381227 (-0.04%); split: -0.04%, +0.00%
InvThroughput: 1373830 -> 1372097 (-0.13%)
VClause: 9031 -> 9038 (+0.08%); split: -0.04%, +0.12%
Copies: 25923 -> 25153 (-2.97%); split: -2.98%, +0.01%
PreVGPRs: 14643 -> 14555 (-0.60%)
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14986>
Alejandro Piñeiro [Fri, 25 Mar 2022 23:39:20 +0000 (00:39 +0100)]
broadcom: update language on V3D_DEBUG options
Some typos, and bad grammar.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15593>
Alejandro Piñeiro [Fri, 25 Mar 2022 23:38:36 +0000 (00:38 +0100)]
docs: document v3d/v3dv envvars
As we are here we also update VC4_DEBUG option, in order to rely on
VC4_DEBUG=help
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15593>
Emma Anholt [Fri, 11 Feb 2022 23:11:59 +0000 (15:11 -0800)]
r600: Implement memoryBarrier() in the non-SFN path.
Previously we were just doing a group barrier for both membar and barrier.
This sometimes worked out, because atomics and reads waited for ack
already, but writes were not waiting for ack. Use the need_wait_ack
pattern that scratch writes used, with a little refactoring for
reusability.
The refactor also incidentally fixes the atomics waiting for outstanding
acks to be > 1 instead of > 0.
Cc: mesa-stable
Fixes: #6028
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14429>
Emma Anholt [Thu, 6 Jan 2022 17:58:46 +0000 (09:58 -0800)]
r600: Disable SB when INTERP_SAMPLE is used.
Avoids an assertion failure in the SB scheduler.
Cc: mesa-stable
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14429>
Emma Anholt [Thu, 6 Jan 2022 17:43:49 +0000 (09:43 -0800)]
r600: Disable SB in the presence of indirection on temp arrays.
Prevents several regressions when NIR-to-TGSI is enabled where it was
allocating arrays on top of each other.
Fixes vec3 fails on RV770,
dEQP-GLES3.functional.shaders.metamorphic.bubblesort_flag.variant_1 and 2
in general, and fixes another piglit but breaks two others. Still, this
seems to be a win.
Cc: mesa-stable
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14429>
Emma Anholt [Wed, 5 Jan 2022 23:45:37 +0000 (15:45 -0800)]
r600: Add a workaround and explanation for shadowcubearray TG4.
With the NIR-to-TGSI transition, we had fewer other immediates and would
end up dereffing past the end of the literals array.
Cc: mesa-stable
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14429>
Emma Anholt [Wed, 5 Jan 2022 22:53:42 +0000 (14:53 -0800)]
r600: Fix ordering of SSBO loads versus texturing.
The two types of instructions get added to the same CF list, but not the
same instr list within the CF list. So, if you SSBO fetched your
texcoord, the emission of the SSBO fetch would come *after* the texcoord
fetch.
Avoids regressions when NIR-to-TGSI starts optimizing more.
Cc: mesa-stable
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14429>
Emma Anholt [Tue, 28 Dec 2021 20:36:20 +0000 (12:36 -0800)]
r600: Drop unused debug options from the fork off of radeonsi.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14429>
Emma Anholt [Tue, 28 Dec 2021 03:50:53 +0000 (19:50 -0800)]
r600: Drop unused sbcl debug option.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14429>
Emma Anholt [Tue, 28 Dec 2021 20:31:36 +0000 (12:31 -0800)]
r600: Add shader-compiler debug knobs to the shader cache key.
Otherwise, you'll get cached results from the previous debug knob state.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14429>
Emma Anholt [Tue, 23 Nov 2021 18:55:06 +0000 (10:55 -0800)]
ci/r600: Check in some expectation files for rv770 and Turks.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14429>
Pavel Ondračka [Wed, 23 Mar 2022 10:03:21 +0000 (11:03 +0100)]
r300: respect output_semantic_index when writing colors
Right now we don't explicitly check it and we expect that the
output_semantic_index array is always ordered. Unfortunately,
this is not the case since
74c02d99b224fbc02132b54bf23e6ac1e117d805
Fixes corruption in Amnesia: the Dark Descent.
cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6179
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15523>
Emma Anholt [Thu, 6 Jan 2022 18:28:02 +0000 (10:28 -0800)]
r600: Add shader precompile and shader-db support.
This should reduce draw-time jank, and was useful for me in evaluating
NIR-to-TGSI's impact for r600.
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14427>
Emma Anholt [Fri, 7 Jan 2022 01:09:11 +0000 (17:09 -0800)]
r600: Update the PS state when MSAA-ness changes, too.
Avoids a regression when enabling shader precompilation, where the
precompile would happen with MSAA disabled (so no sample mask export) but
we'd never catch up to the shader being rendered with MSAA.
Doesn't fix any current testcases, though.
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14427>
Emma Anholt [Fri, 7 Jan 2022 00:27:34 +0000 (16:27 -0800)]
r600: Update the PS state before checking for cb_misc update.
The update_ps_state updates ps_shader->current->ps_color_export_mask, so
we could miss statechanges.
Cc: mesa-stable
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14427>
Emma Anholt [Thu, 6 Jan 2022 18:53:15 +0000 (10:53 -0800)]
r600: Drop nr_ps_max_color_exports
Prior to
b6521801070d ("r600g: don't snoop context state while building
shaders"), it fed into the shader key, but nothing does any more.
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14427>
Connor Abbott [Thu, 24 Mar 2022 19:06:26 +0000 (20:06 +0100)]
freedreno/ci: Fix skip comment
This test was never supposed to be skipped, and the referenced commit
just exposed a bug in turnip fixed by the previous commit. It was
hanging due to a CTS bug making the submit take way too long, which will
be fixed once the CTS change lands.
Also, add it to the a630 skips.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15563>
Connor Abbott [Thu, 24 Mar 2022 16:31:29 +0000 (17:31 +0100)]
tu: Correctly handle VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
In this case we should relax checks based on the format, since the user
will be responsible for them when creating an image view.
This gets dEQP-VK.image.sample_texture.*_bit_compressed_format_* not
skipping again after VK-GL-CTS
736eec57dc0c ("Fix checkSupport in
compressed texture sampling tests").
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15563>
Samuel Pitoiset [Mon, 28 Feb 2022 10:43:41 +0000 (11:43 +0100)]
radv: advertise VK_EXT_depth_clip_control
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6070
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15192>
Samuel Pitoiset [Mon, 28 Feb 2022 10:42:51 +0000 (11:42 +0100)]
radv: implement VK_EXT_depth_clip_control
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15192>
Danylo Piliaiev [Fri, 25 Mar 2022 13:26:52 +0000 (15:26 +0200)]
turnip: Fix the lack of WFM before indirect draws
We have to add WFM to pending bits when we are flushing into CP
for indirect draw to know when they should apply WFM workaround.
Fixes CTS tests:
dEQP-VK.draw.renderpass.indirect_draw.*_data_from_compute.indirect_draw_count*
Fixes:
abf0ae014a878d063132a4bf2f2515dc7052f069
("tu: Properly handle waiting on an earlier pipeline stage")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15577>
Gert Wollny [Fri, 18 Mar 2022 08:04:47 +0000 (09:04 +0100)]
virgl: re-enable PIPE_CAP_TGSI_TEXCOORD with new host versions
Also upreaf the virglrenderer version used in the CI.
v2: Update checksums of trace result images (0 pixels were different)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15446>
Samuel Pitoiset [Fri, 18 Mar 2022 09:15:41 +0000 (10:15 +0100)]
radv: lower adjusting gl_FragCoord.z for VRS in NIR
fossils-db (Sienna Cichlid):
Totals from 4432 (3.29% of 134913) affected shaders:
VGPRs: 231232 -> 231880 (+0.28%)
CodeSize:
24738224 ->
24718008 (-0.08%); split: -0.08%, +0.00%
MaxWaves: 93120 -> 93000 (-0.13%)
Instrs: 4540970 -> 4541062 (+0.00%); split: -0.01%, +0.01%
Latency:
49658353 ->
49641444 (-0.03%); split: -0.05%, +0.01%
InvThroughput: 9604328 -> 9603041 (-0.01%); split: -0.02%, +0.01%
VClause: 66497 -> 66498 (+0.00%)
SClause: 209530 -> 209532 (+0.00%); split: -0.01%, +0.01%
Copies: 276135 -> 276249 (+0.04%); split: -0.14%, +0.18%
PreSGPRs: 189409 -> 189415 (+0.00%)
PreVGPRs: 207368 -> 207458 (+0.04%)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15450>
Samuel Pitoiset [Thu, 10 Mar 2022 14:56:49 +0000 (15:56 +0100)]
radv: lower load_sample_mask_in in NIR
No fossils-db changes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15450>
Mike Blumenkrantz [Tue, 22 Mar 2022 19:49:21 +0000 (15:49 -0400)]
radv: fix CmdSetColorWriteEnableEXT(attachmentCount==MAX_RTS)
cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15508>
Samuel Pitoiset [Tue, 22 Feb 2022 15:39:29 +0000 (16:39 +0100)]
radv,aco: lower color exports in NIR
fossils-db (Sienna Cichlid):
Totals from 27108 (20.09% of 134913) affected shaders:
VGPRs: 1260608 -> 1261424 (+0.06%); split: -0.00%, +0.07%
CodeSize:
112795868 ->
112785892 (-0.01%); split: -0.05%, +0.04%
MaxWaves: 628608 -> 628448 (-0.03%); split: +0.00%, -0.03%
Instrs:
20750003 ->
20749314 (-0.00%); split: -0.01%, +0.00%
Latency:
288088081 ->
288015865 (-0.03%); split: -0.06%, +0.04%
InvThroughput:
53944847 ->
53961693 (+0.03%); split: -0.01%, +0.04%
VClause: 396463 -> 396467 (+0.00%); split: -0.02%, +0.02%
SClause: 842088 -> 842150 (+0.01%); split: -0.03%, +0.04%
Copies: 1244982 -> 1259026 (+1.13%); split: -0.01%, +1.14%
PreSGPRs: 1251949 -> 1251909 (-0.00%)
PreVGPRs: 1099647 -> 1100879 (+0.11%); split: -0.03%, +0.14%
fossils-db (Polaris10):
Totals from 23928 (17.60% of 135960) affected shaders:
SGPRs: 1751792 -> 1751024 (-0.04%); split: -0.05%, +0.01%
VGPRs: 1098964 -> 1098556 (-0.04%); split: -0.13%, +0.09%
CodeSize:
99893472 ->
99837940 (-0.06%); split: -0.06%, +0.00%
MaxWaves: 138322 -> 138306 (-0.01%); split: +0.03%, -0.04%
Instrs:
19213995 ->
19211980 (-0.01%); split: -0.02%, +0.01%
Latency:
273026926 ->
273109402 (+0.03%); split: -0.01%, +0.04%
InvThroughput:
111160907 ->
111195187 (+0.03%); split: -0.04%, +0.07%
VClause: 343058 -> 343097 (+0.01%); split: -0.02%, +0.03%
SClause: 802756 -> 802884 (+0.02%); split: -0.04%, +0.06%
Copies: 1729387 -> 1739208 (+0.57%); split: -0.04%, +0.61%
PreSGPRs: 1090264 -> 1090303 (+0.00%); split: -0.00%, +0.01%
PreVGPRs: 959490 -> 960600 (+0.12%); split: -0.04%, +0.15%
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15263>
Jakob Bornecrantz [Sun, 27 Mar 2022 15:00:22 +0000 (16:00 +0100)]
vulkan-device-select: Don't leak xcb_query_extension_reply_t
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15600>
Iago Toral Quiroga [Thu, 24 Mar 2022 09:45:50 +0000 (10:45 +0100)]
broadcom/compiler: allow ldunifa with indirect uniform loads
We handle uniforms by copying them into the uniform stream to be
consumed with ldunif when they have a constant offset. Otherwise
we fallback to general TMU access, which has more latency.
However, just like we did for UBOs and read-only SSBOs, we can
also try to use the unifa mechanism to handle indirect accesses
in certain cases instead of the TMU fallback.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15575>
Iago Toral Quiroga [Thu, 24 Mar 2022 09:05:17 +0000 (10:05 +0100)]
v3dv: implement VK_EXT_inline_uniform_block
Inline uniform blocks store their contents in pool memory rather
than a separate buffer, and are intended to provide a way in which
some platforms may provide more efficient access to the uniform
data, similar to push constants but with more flexible size
constraints.
We implement these in a similar way as push constants: for constant
access we copy the data in the uniform stream (using the new
QUNIFORM_UNIFORM_UBO_*) enums to identify the inline buffer from
which we need to copy and for indirect access we fallback to
regular UBO access.
Because at NIR level there is no distinction between inline and
regular UBOs and the compiler isn't aware of Vulkan descriptor
sets, we use the UBO index on UBO load intrinsics to identify
inline UBOs, just like we do for push constants. Particularly,
we reserve indices 1..MAX_INLINE_UNIFORM_BUFFERS for this,
however, unlike push constants, inline buffers are accessed
through descriptor sets, and therefore we need to make sure
they are located in the first slots of the UBO descriptor map.
This means we store them in the first MAX_INLINE_UNIFORM_BUFFERS
slots of the map, with regular UBOs always coming after these
slots.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15575>
Georg Lehmann [Fri, 25 Mar 2022 10:20:28 +0000 (11:20 +0100)]
radv: Add more RT pipeline stubs.
Entry points have to be provided even if the features are not supported.
Helps Doom Eternal.
Fixes:
f1095260a41 ("radv: Experimentally enable RT extensions.")
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15573>
Georg Lehmann [Fri, 25 Mar 2022 10:03:19 +0000 (11:03 +0100)]
radv: Add a vkCmdBuildAccelerationStructuresIndirectKHR stub.
Since this entry point is provided by VK_KHR_acceleration_structure, radv has
to implement it even if it doesn't support the indirect build feature.
Helps Doom Eternal.
Fixes:
82de184c3a2 ("radv: Enable VK_KHR_acceleration_structure with RADV_PERFTEST=rt.")
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15573>
Rhys Perry [Wed, 23 Mar 2022 18:32:06 +0000 (18:32 +0000)]
aco: fix RA validation of 16-bit fma_mix operands
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15562>
Pierre-Eric Pelloux-Prayer [Wed, 23 Mar 2022 14:37:49 +0000 (15:37 +0100)]
glsl/nir/linker: fix shader_storage_blocks_write_access
shader_storage_blocks_write_access was computed using the buffer indices
in the program but ShaderStorageBlocksWriteAccess is used with the shader
buffers.
So if a VS had 3 SSBOs and a FS had 4, the mask for VS was 0x3 (correct) but
the mask for the FS was 0x78 instead of 0x15.
Fix this by substracting the index of the first shader buffer in the program's
buffers.
Fixes:
79127f8d5be ("glsl: set ShaderStorageBlocksWriteAccess in the nir linker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6184
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15552>
Pierre-Eric Pelloux-Prayer [Wed, 23 Mar 2022 12:35:14 +0000 (13:35 +0100)]
glsl/nir/linker: update shader_storage_blocks_write_access for SPIR-V
Most of the code inside the "!prog->data->spirv" blocks shouldn't be
executed for SPIR-V except the part updating the writable mask.
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/6184
Cc: mesa-stable
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15552>
Daniel Schürmann [Fri, 18 Mar 2022 19:03:27 +0000 (20:03 +0100)]
aco: use branch definition as scratch register for SSA lowering
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15505>
Mike Blumenkrantz [Fri, 25 Mar 2022 13:48:27 +0000 (09:48 -0400)]
zink: use z24_in_z32f support and radv ci updates
This uses the new transfer helper codepath in zink and fixes a bunch of fail on radv.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15516>
Dave Airlie [Wed, 23 Mar 2022 04:59:42 +0000 (14:59 +1000)]
u_transfer_helper: add a new option for handling z24 stored in z32
It might be possible to combine this with the other merge to avoid
the overheads of making a temp copy.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15516>
Dave Airlie [Wed, 23 Mar 2022 06:24:32 +0000 (16:24 +1000)]
u_transfer: refactor out code to check interleave/deinterleave path.
The checks were reproduced making adding another one not so fun.
rework the deinterleave path code to match the interleave path code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15516>
Dave Airlie [Wed, 23 Mar 2022 05:10:51 +0000 (15:10 +1000)]
util/format: add new z24/s8 packing helper to pack z32/s8.
If zink runs on top of a vulkan impl with no 24-bit float support
it needs support to pack into 24-bit for GL.
To avoid having to make a temp copy, add a new helper to convert
and pack.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15516>
Kenneth Graunke [Wed, 16 Mar 2022 10:06:22 +0000 (03:06 -0700)]
intel/compiler: Use nir_opt_uniform_atomics()
In general, an atomic intrinsic may perform separate atomics for every
enabled SIMD channel, as each channel may operate on different memory.
However, an extremely common case is for all channels to access the same
memory location. In this case, we can simply perform a reduction/scan
across the subgroup, and perform one atomic for the whole subgroup,
rather than one per channel. For example, if an intrinsic says to take
the minimum value of the existing memory and the value in each channel,
we can do a thread-local minimum of all enabled channels, then do a
single atomic to take the minimum of that and the existing memory.
Our hardware doesn't optimize the case where multiple channels ask for
atomics on the same memory location; it assumes the compiler will do so.
nir_opt_uniform_atomics() uses divergence analysis to detect this case,
adds the necessary subgroup operations, and moves the atomic inside a
conditional that disables all but a single invocation. It even detects
cases where the shader code already performs this kind of optimization,
and avoids doing it a second time.
This may not be the optimal solution for us. In the backend, we could
detect this case and emit send(1) instructions with NoMask, rather than
generating if...send(16)...endif, and a lot of unnecessary ALU ops. But
it's simple to do, reuses the same path as ACO, and still provides most
of the benefit by cutting up to 16x atomics down to a single atomic,
which is more merciful to the memory bus.
Improves performance of Shadow of the Tomb Raider by 5.5% on XeHP.
Improves performance of a customer-internal benchmark on XeHP at
3840x2160 and low settings by approximately 30%.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Kenneth Graunke [Tue, 15 Mar 2022 23:25:55 +0000 (16:25 -0700)]
intel/compiler: Convert to LCSSA and use divergence analysis.
We'll use this more shortly. For now, enable it to separately in case
anything bisects to this.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Kenneth Graunke [Fri, 16 Oct 2020 23:05:52 +0000 (16:05 -0700)]
intel/compiler: Set divergence analysis options
Although we don't use divergence analysis yet, we've had several
work-in-progress series that make use of it. We may as well set
our options so that those series can assume they're in place.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Kenneth Graunke [Thu, 17 Mar 2022 07:46:21 +0000 (00:46 -0700)]
intel/compiler: Implement nir_intrinsic_last_invocation
We haven't exposed this intrinsic as it doesn't directly correspond to
anything in SPIR-V. However, it's used internally by some NIR passes,
namely nir_opt_uniform_atomics().
We reuse most of the infrastructure in brw_find_live_channel, but with
LZD/ADD instead of FBL. A new SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL is
like SHADER_OPCODE_FIND_LIVE_CHANNEL but from the other side.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Kenneth Graunke [Wed, 16 Mar 2022 09:14:52 +0000 (02:14 -0700)]
nir: Teach nir_divergence_analysis about Intel-specific intrinsics
- load_reloc_const is just an immediate constant load, it's convergent.
- nir_intrinsic_load_global_const_block_intel should be convergent,
it says the address must be uniform, and we uniformize the predicate
- Lowered image intrinsics: image_deref_load_param_intel just reads
information about an image, as long as the image variable is
convergent it should be too. load_raw_intel...if the address we
come up with is convergent, it ought to be as well.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Mike Blumenkrantz [Fri, 25 Mar 2022 22:41:16 +0000 (18:41 -0400)]
zink: add another radv flake
literally no idea
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15589>
Caio Oliveira [Tue, 15 Feb 2022 00:40:54 +0000 (16:40 -0800)]
intel/compiler: Inline TUE map computation into TUE Input lowering
Refactor since the TUE compute function is simpler now and the
comments make sense being near the lowering.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15022>
Caio Oliveira [Tue, 15 Feb 2022 00:36:32 +0000 (16:36 -0800)]
intel/compiler: Use nir_var_mem_task_payload
Instead of reusing the in/out slot mechanism, use a separated NIR
variable mode. This will make easier later to implement staging the
output in shared memory (and storing all at the end to the URB).
Note to get 64-bit type support we currently rely on the
brw_nir_lower_mem_access_bit_sizes() pass.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15022>
Daniel Schürmann [Wed, 23 Mar 2022 17:23:29 +0000 (18:23 +0100)]
aco: remove 'high' parameter from can_use_opsel()
No fossil-db changes.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15551>
Daniel Schürmann [Wed, 23 Mar 2022 14:12:09 +0000 (15:12 +0100)]
aco/optimizer: fix call to can_use_opsel() in apply_insert()
The definition index is -1.
Fixes:
54292e99c7844500314bfd623469c65adef954c5 ('aco: optimize 32-bit extracts and inserts using SDWA ')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15551>
Adam Jackson [Thu, 24 Mar 2022 14:49:16 +0000 (10:49 -0400)]
wsi/x11: xcb_wait_for_special_event failure is an error
The only ways that function can return NULL are:
- the xcb connection was closed
- the window for the swapchain was destroyed
- the special event listener was unregistered from another thread
- malloc failure
All of these are permanent errors, the swapchain is no longer in a
usable state, so we should treat this as VK_ERROR_SURFACE_LOST_KHR.
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15558>
Alyssa Rosenzweig [Thu, 17 Mar 2022 15:47:47 +0000 (11:47 -0400)]
pan/va: Lower BLEND to call blend shaders
Do this as late as possible.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 19 Nov 2021 20:38:04 +0000 (15:38 -0500)]
pan/va: Add packing unit tests
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Mon, 2 Aug 2021 16:30:54 +0000 (12:30 -0400)]
pan/va: Add shader-db support
Reports the common subset from Bifrost, as well as Mali offline compiler
style normalized cycle counts.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Mon, 2 Aug 2021 21:11:03 +0000 (17:11 -0400)]
pan/va: Implement the cycle model
Will feed into shader-db reporting, and maybe other things eventually.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 20:36:04 +0000 (16:36 -0400)]
pan/va: Test instruction selection lowerings
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Mon, 26 Jul 2021 22:05:39 +0000 (18:05 -0400)]
pan/va: Lower branch offsets
Logic is lifted from bi_layout.c, adapted to work on instructions (not
clauses) and for Valhall's off-by-one semantic which is annoyingly
different than Bifrost. (But the same as Midgard -- Bifrost was
annoyingly different than Midgard!)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 20:35:06 +0000 (16:35 -0400)]
pan/va: Add instruction selection lowering pass
Valhall removes certain instructions from Bifrost, requiring a canonical
lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Tue, 27 Jul 2021 18:17:14 +0000 (14:17 -0400)]
pan/va: Add constant lowering pass
Valhall has a lookup table for common constants. Add a pass to take
advantage of it, lowering away immediate indices.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 15:21:35 +0000 (11:21 -0400)]
pan/va: Validate FAU before packing
These are pre-conditions required for packing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 15:21:29 +0000 (11:21 -0400)]
pan/va: Add FAU validation
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 22 Jul 2021 15:59:09 +0000 (11:59 -0400)]
pan/va: Add unit tests for ADD_IMM optimizations
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 22 Jul 2021 00:29:54 +0000 (20:29 -0400)]
pan/va: Optimize add with imm to ADD_IMM
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Mon, 19 Jul 2021 19:51:52 +0000 (15:51 -0400)]
pan/va: Add packing routines
Mostly manual since Valhall is regular.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Tue, 27 Jul 2021 17:24:22 +0000 (13:24 -0400)]
pan/va: Add helpers for swapping bitwise sources
Annoyingly different from Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 24 Mar 2022 21:13:24 +0000 (17:13 -0400)]
pan/va: Generate header containing enums
We already collect enums in the ISA description XML. Export them for use in the
compiler backend, particularly the packing code.
Usually we'd use Mako for templating. In this case, the script is so trivial a
template engine didn't seem worth it. (The obvious version with Mako was about
10 lines longer than just prints and f-strings used here.)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 16:04:13 +0000 (12:04 -0400)]
pan/va: Build opcode info structures
Filled out the new structures from XML.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 25 Feb 2022 16:52:41 +0000 (11:52 -0500)]
pan/va: Permit encoding more flags
Missed the first time around.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 24 Mar 2022 22:08:27 +0000 (18:08 -0400)]
pan/va: Unify flow control
Group together dependency waits and flow control into a single enum. This
simplifies the code, clarifies some detail, and ensures consistency moving
forward.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 24 Mar 2022 00:29:08 +0000 (20:29 -0400)]
pan/va: Add Bifrost-style LD_VAR instructions
For use in the legacy non-MALLOC_IDVS flow. Especially useful in blit shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 15:57:52 +0000 (11:57 -0400)]
pan/va: Add LD_VAR_BUF instructions
Like LD_VAR_BUF_IMM but indirect.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 20:45:35 +0000 (16:45 -0400)]
pan/va: Add ST_TILE instruction
Encoded like LD_TILE, required for some MSAA blend shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 24 Mar 2022 22:10:23 +0000 (18:10 -0400)]
pan/bi: Rename I->action to I->flow
For consistency with the Valhall ISA.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 15:57:11 +0000 (11:57 -0400)]
pan/bi: Model LD_VAR_BUF instructions
These are indirect versions of LD_VAR_BUF_IMM, taking their index in bytes. Used
for indirect varying loads (the NIR lowering is inefficient).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 21:20:33 +0000 (17:20 -0400)]
pan/bi: Augment ST_TILE with register format
To model its Valhall incarnation.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 17 Mar 2022 16:31:28 +0000 (12:31 -0400)]
pan/bi: Check return addresses in blend shaders
Required on Valhall, where jumping to 0x0 doesn't automatically terminate the
program. Luckily the check is free there too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 17 Mar 2022 16:15:37 +0000 (12:15 -0400)]
pan/bi: Allow branch_offset on BLEND
Required to model BLEND accurately on Valhall, where it encodes a special
relative branch... Midgard style!
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 02:30:11 +0000 (22:30 -0400)]
pan/bi: Model Valhall-style A(CMP)XCHG
Handled consistently with computational atomics.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 01:53:04 +0000 (21:53 -0400)]
pan/bi: Add ATOM_RETURN pseudo-instruction
Allows modeling Valhall's atomics better.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 01:47:27 +0000 (21:47 -0400)]
pan/bi: Rename PATOM_C to ATOM
This is basically what's native on Valhall. Use the Valhall naming for the
pseudo-instruction on Bifrost for consistency.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 13:22:40 +0000 (09:22 -0400)]
pan/bi: Gate late DCE/CSE on "optimize"
Otherwise we can end up with unlowered ATOM.i32 on Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>