Anastasia Stulova [Tue, 9 Feb 2021 15:08:46 +0000 (15:08 +0000)]
[OpenCL] Fix types with signed prefix in arginfo metadata.
Signed prefix is removed and the single word spelling is
printed for the scalar types.
Tags: #clang
Differential Revision: https://reviews.llvm.org/D96161
Lei Zhang [Tue, 9 Feb 2021 15:04:43 +0000 (10:04 -0500)]
[mlir][linalg] Fix depthwise conv C++ symbol to be consistent
The assembly mnemonic includes information about input/filter
data format. The C++ symbol should be consistent.
Thomas Raoux [Tue, 9 Feb 2021 05:20:08 +0000 (21:20 -0800)]
[mlir][linalg] Fix one more missing NoSideEffect in linalg tensor op
Differential Revision: https://reviews.llvm.org/D96314
Jan Svoboda [Tue, 9 Feb 2021 14:46:10 +0000 (15:46 +0100)]
[clang][cli] Store unsigned instead of OptSpecifier in table
This fixes some buildbot failures with ambiguous call to OptSpecifier constructor.
Jan Svoboda [Tue, 9 Feb 2021 14:20:09 +0000 (15:20 +0100)]
[clang][cli] Look up program action argument in a table
This patch extracts the mapping between command line option and frontend::ActionKind into a table. The table can be reused when parsing and also generating command line options.
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D96269
Nico Weber [Tue, 9 Feb 2021 14:17:23 +0000 (09:17 -0500)]
Try to fix compiler-rt tests after
87dbdd2e3bb63b on mac and win
These tests use `--check-prefix=CHECK-%os` but then didn't have
a CHECK line for every os.
In most tests, the linux expectations were sufficient (they match
the "wrap_" prefix with .*), so just remove the check-prefix there.
In the places where this didn't easily work, make sure there are
at least CHECK-Windows and CHECK-Darwin lines.
Jan Svoboda [Tue, 9 Feb 2021 14:08:31 +0000 (15:08 +0100)]
[clang][cli] Store InputKind in FrontendOptions
This patch stores the `InputKind` (parsed mainly from `-x`) to `FrontendOptions`. This is necessary for command line generation.
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D96149
Simon Pilgrim [Tue, 9 Feb 2021 11:07:35 +0000 (11:07 +0000)]
[X86][SSE] foldShuffleOfHorizOp - add SHUFPS v4f32 handling
Fold shufps(hop(x,y),hop(z,w)) -> permute(hop(x,z)) - this is very similar to the equivalent unpack fold.
I did start trying to convert foldShuffleOfHorizOp to handle generic shuffle masks but we're relying on a lot of special cases at the moment.
Denys Shabalin [Tue, 9 Feb 2021 14:09:02 +0000 (15:09 +0100)]
[mlir] Add stacksave, stackrestore to llvm dialect
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D96333
poelmanc [Tue, 9 Feb 2021 14:02:12 +0000 (14:02 +0000)]
[clang-tidy] fix modernize-use-nullptr false positive with spaceship operator comparisons
`clang-tidy -std=c++20` with `modernize-use-nullptr` mistakenly inserts `nullptr` in place of the comparison operator if the comparison internally expands in the AST to a rewritten spaceship operator. This can be reproduced by running the new `modernize-use-nullptr-cxx20.cpp` test without applying the supplied patch to `UseNullptrCheck.cpp`; the current clang-tidy will mistakenly replace:
```result = (a1 < a2);```
with
```result = (a1 nullptr a2);```
Reviewed By: njames93
Differential Revision: https://reviews.llvm.org/D95714
Lei Zhang [Tue, 9 Feb 2021 13:51:55 +0000 (08:51 -0500)]
[mlir][linalg] Define a depthwise 2-D convolution op
This commit defines linalg.depthwise_conv_2d_nhwc for depthwise
2-D convolution with NHWC input/output data format.
This op right now only support channel multiplier == 1, which is
the most common case.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D94966
Lei Zhang [Tue, 9 Feb 2021 13:47:21 +0000 (08:47 -0500)]
[mlir][linalg] Verify indexing map required attributes
Indexing maps for named ops can reference attributes so that
we can synthesize the indexing map dynamically. This supports
cases like strides for convolution ops. However, it does cause
an issue: now the indexing_maps() function call is dependent
on those attributes.
Linalg ops inherit LinalgOpInterfaceTraits, which calls
verifyStructuredOpInterface() to verify the interface.
verifyStructuredOpInterface() further calls indexing_maps().
Note that trait verification is done before the op itself,
where ODS generates the verification for those attributes.
So we can have indexing_maps() referencing non-existing or
invalid attribute, before the ODS-generated verification
kick in.
There isn't a dependency handling mechansim for traits.
This commit adds new interface methods to query whether an
op hasDynamicIndexingMaps() and then perform
verifyIndexingMapRequiredAttributes() in
verifyStructuredOpInterface() to handle the dependency issue.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D96297
Nico Weber [Tue, 9 Feb 2021 13:18:23 +0000 (08:18 -0500)]
[lld/mac] Implement -u flag
Since we emit diagnostics for undefineds in Writer::scanRelocations()
and symbols referenced by -u flags aren't referenced by any relocations,
this needs some manual code (similar to the entry point).
Differential Revision: https://reviews.llvm.org/D94371
Wang, Pengfei [Tue, 9 Feb 2021 13:12:59 +0000 (21:12 +0800)]
[X86] Always assign reassoc flag for intrinsics *reduce_add/mul_ps/pd.
Intrinsics *reduce_add/mul_ps/pd have assumption that the elements in
the vector are reassociable. So we need to always assign the reassoc
flag when we call _mm_reduce_* intrinsics.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D96231
Nemanja Ivanovic [Tue, 9 Feb 2021 12:33:48 +0000 (06:33 -0600)]
[DAGCombine] Do not remove masking argument to FP16_TO_FP for some targets
As of commit
284f2bffc9bc5, the DAG Combiner gets rid of the masking of the
input to this node if the mask only keeps the bottom 16 bits. This is because
the underlying library function does not use the high order bits. However, on
PowerPC's ELFv2 ABI, it is the caller that is responsible for clearing the bits
from the register. Therefore, the library implementation of __gnu_h2f_ieee will
return an incorrect result if the bits aren't cleared.
This combine is desired for ARM (and possibly other targets) so this patch adds
a query to Target Lowering to check if this zeroing needs to be kept.
Fixes: https://bugs.llvm.org/show_bug.cgi?id=49092
Differential revision: https://reviews.llvm.org/D96283
Nemanja Ivanovic [Tue, 9 Feb 2021 12:11:45 +0000 (06:11 -0600)]
[RISCV] Fix shared libs build
Commit
a2d19bad07454ae7936d8f2b8482e24d57954fc4 introduced a
dependency in the RISCV disassembler on two additional libraries
(MC, RISCVDesc) which wasn't added to the CMakeLists.txt. This
causes shared library builds to break. This patch just adds them
to fix failures seen on some bots, such as the PPC64LE Multistage.
Jon Chesterfield [Tue, 9 Feb 2021 11:58:37 +0000 (11:58 +0000)]
[libomptarget][amdgcn] Tolerate deadstripped env variable
[libomptarget][amdgcn] Tolerate deadstripped env variable
Discovered by Pushpinder. If the device_environment variable is unused
it can be deadstripped, in which case we should not abort due to it
missing. This change is safe in that a missing symbol which is actually
used can be reported by both linker and loader, and a missing unused
symbol is better deadstripped than left in the image.
Reviewed By: pdhaliwal
Differential Revision: https://reviews.llvm.org/D96329
Dylan McKay [Tue, 9 Feb 2021 10:08:19 +0000 (23:08 +1300)]
[AVR] Fix global references to function symbols
References to functions are in program memory and need a `pm()` fixup. This should fix trait objects for Rust on AVR.
Differential Revision: https://reviews.llvm.org/D87631
Patch by Alex Mikhalev.
Thomas Preud'homme [Tue, 9 Feb 2021 11:27:35 +0000 (11:27 +0000)]
Revert STRICT_FCMP nonan optimisation
Summary: This reverts commit
b7b61a7b5bc63df0d84f3722a1dcfa375c35ba30 which fails on some of the builders: http://lab.llvm.org:8011/#/builders/14/builds/5806
Reviewers:
Subscribers:
Thomas Preud'homme [Thu, 19 Nov 2020 23:38:42 +0000 (23:38 +0000)]
Improve STRICT_FSETCC codegen in absence of no NaN
As for SETCC, use a less expensive condition code when generating
STRICT_FSETCC if the node is known not to have Nan.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D91972
Vitaly Buka [Tue, 9 Feb 2021 10:59:59 +0000 (02:59 -0800)]
[NFC,Clang] Add more Asan Driver tests
Vitaly Buka [Tue, 9 Feb 2021 10:56:57 +0000 (02:56 -0800)]
[NFC,Clang] Add SanCov Driver tests
Vitaly Buka [Tue, 9 Feb 2021 10:55:33 +0000 (02:55 -0800)]
[NFC,Clang] Add LTO Driver MSan,KMsan tests
Vitaly Buka [Tue, 9 Feb 2021 10:51:19 +0000 (02:51 -0800)]
[NFC,Clang] Add LTO Driver DFsan tests
Vitaly Buka [Tue, 9 Feb 2021 10:49:51 +0000 (02:49 -0800)]
[NFC,Clang] Add LTO Driver Tsan tests
Kirill Bobyrev [Tue, 9 Feb 2021 10:46:22 +0000 (11:46 +0100)]
[clangd] Fix false positive in local rename collision detetction
Fixes https://github.com/clangd/clangd/issues/685
Reviewed By: hokein
Differential Revision: https://reviews.llvm.org/D96247
Valeriy Savchenko [Tue, 9 Feb 2021 10:48:24 +0000 (13:48 +0300)]
[-Wcompletion-handler][NFC] Remove unexpected warnings on Windows
Jan Svoboda [Tue, 9 Feb 2021 10:42:01 +0000 (11:42 +0100)]
[clang][cli] Generate and round-trip CodeGen options
This patch implements generation of remaining codegen options and tests it by performing parse-generate-parse round trip.
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D96056
Jan Svoboda [Tue, 9 Feb 2021 10:06:03 +0000 (11:06 +0100)]
[clang][codegen] Remember string used to create llvm::Regex for optimization remarks
Regular expression patterns passed through the command line are being used to create an instances of `llvm::Regex` and thrown away.
There is no API to serialize `Regex` back to the original pattern. This means we have no way to reconstruct the original pattern from command line. This is necessary for serializing `CompilerInvocation`.
This patch stores the original pattern string in `CodeGenOptions` alongside the `llvm::Regex` instance.
Reviewed By: dexonsmith, thegameg
Differential Revision: https://reviews.llvm.org/D96036
Jeremy Morse [Tue, 9 Feb 2021 09:48:22 +0000 (09:48 +0000)]
Revert "[DebugInfo] Re-engineer a test to be stricter, add XFails"
This reverts commit
e05c10380ce7c18d1a232dcc5baa7c10d8bd2bf6.
See parent commit, there's a bot which isn't captured in the XFail list,
reverting til I work out what it is.
Jeremy Morse [Tue, 9 Feb 2021 09:46:32 +0000 (09:46 +0000)]
Revert "Follow up to
e05c10380ce7: add aarch64 to test XFails"
This reverts commit
4fd29e4fd3c5490b658f4b467d94aeed6b3d1ac3.
There's a report in D95617 that this is failing on what (I think?) is an
aarch64 bot, which should be covered by the XFail list... reverting this
follow-up and the base patch until I work out what's wrong here.
LLVM GN Syncbot [Tue, 9 Feb 2021 09:19:31 +0000 (09:19 +0000)]
[gn build] Port
40c261c41c4c
Jan Svoboda [Tue, 9 Feb 2021 09:17:04 +0000 (10:17 +0100)]
[clang][cli] Generate and round-trip language options
This patch implements generation of remaining language options and tests it by performing parse-generate-parse round trip (on by default for assert builds, off otherwise).
This patch also correctly reports failures in `parseSanitizerKinds`, which is necessary for emitting diagnostics when an invalid sanitizer is passed to `-fsanitize=` during round-trip.
This patch also removes TableGen marshalling classes from two options:
* `fsanitize_blacklist` When parsing: it's first initialized via the generated code, but then also changed by manually written code, which is confusing.
* `fopenmp` When parsing: it's first initialized via generated code, but then conditionally changed by manually written code. This is also confusing. Moreover, we need to do some extra checks when generating it, which would be really cumbersome in TableGen. (Specifically, not emitting it when `-fopenmp-simd` was present.)
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D95793
Fangrui Song [Tue, 9 Feb 2021 08:43:10 +0000 (00:43 -0800)]
[ELF] Drop Android specific workaround -m aarch64_elf64_le_vec
`extern const bfd_target aarch64_elf64_le_vec;` is a variable in BFD.
It was somehow misused as an emulation by Android.
```
% aarch64-linux-gnu-ld -m aarch64_elf64_le_vec a.o
aarch64-linux-gnu-ld: unrecognised emulation mode: aarch64_elf64_le_vec
Supported emulations: aarch64linux aarch64elf aarch64elf32 aarch64elf32b aarch64elfb armelf armelfb aarch64linuxb aarch64linux32 aarch64linux32b armelfb_linux_eabi armelf_linux_eabi
```
Acked by Stephen Hines, who removed the flag from Android a while back.
Valeriy Savchenko [Mon, 8 Feb 2021 15:47:21 +0000 (18:47 +0300)]
[-Wcompletion-handler] Support checks with builtins
It is very common to check callbacks and completion handlers for null.
This patch supports such checks using built-in functions:
* __builtin_expect
* __builtin_expect_with_probablity
* __builtin_unpredictable
rdar://
73455388
Differential Revision: https://reviews.llvm.org/D96268
Hongtao Yu [Sat, 6 Feb 2021 01:56:45 +0000 (17:56 -0800)]
[ELF] Rewriting the path of sample profile file for --reproduce response.txt
Rewritting the path of the sample profile file in response.txt to be relative to the repro tar.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D96193
Chuanqi Xu [Tue, 9 Feb 2021 07:52:11 +0000 (15:52 +0800)]
[NFC] [Coroutine] Remove Unused Variables
Hsiangkai Wang [Tue, 9 Feb 2021 06:43:10 +0000 (14:43 +0800)]
[RISCV] Use whole register load/store for generic load/store.
In vector v0.10, there are whole vector register load/store
instructions. I suggest to use the whole register load/store
instructions for generic load/store for scalable vector types. It could
save up vset{i}vl{i} for these load/store.
For fractional LMUL, I keep to use vle{eew}.v/vse{eew}.v instructions to
load/store partial vector registers.
Differential Revision: https://reviews.llvm.org/D95853
Zakk Chen [Tue, 9 Feb 2021 07:43:32 +0000 (23:43 -0800)]
[Docs] Fix Typo
Matthias Springer [Tue, 9 Feb 2021 07:43:04 +0000 (16:43 +0900)]
[MLIR][AVX512] Add integration test for vp2intersect
Differential Revision: https://reviews.llvm.org/D96306
Fangrui Song [Tue, 9 Feb 2021 07:36:37 +0000 (23:36 -0800)]
[test] Drop redundant REQUIRES: x86-registered-target
Fangrui Song [Tue, 9 Feb 2021 07:34:41 +0000 (23:34 -0800)]
[test] Add REQUIRES: x86-registered-target to DebugInfo/Symbolize/ELF llvm-mc tests
Douglas Yung [Tue, 9 Feb 2021 06:47:14 +0000 (22:47 -0800)]
Mark 4 tests added in
6d766c8bf9df as requiring an x86 backend as they fail when it is not present.
This should fix buildbot failures like http://lab.llvm.org:8011/#/builders/107/builds/4469
Kazu Hirata [Tue, 9 Feb 2021 06:33:53 +0000 (22:33 -0800)]
[Transforms] Use range-based for loops (NFC)
Kazu Hirata [Tue, 9 Feb 2021 06:33:51 +0000 (22:33 -0800)]
[TableGen] Use ListSeparator (NFC)
Kazu Hirata [Tue, 9 Feb 2021 06:33:49 +0000 (22:33 -0800)]
[Transforms/Utils] Drop unnecessary const from a return type (NFC)
Identified with const-return-type.
Max Kazantsev [Tue, 9 Feb 2021 04:00:12 +0000 (11:00 +0700)]
Return "[Test] Add failing test for PR49087"
Another attempt, this time with tripple fix.
George [Tue, 9 Feb 2021 03:54:19 +0000 (19:54 -0800)]
[MLIR] Add C API for navigating up the IR tree
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D96301
Sam Clegg [Tue, 9 Feb 2021 01:12:23 +0000 (17:12 -0800)]
[lld][WebAssembly] Fix typo in function name
addOptionalGlobalSymbols should be addOptionalGlobalSymbol.
Also, remove unnecessary additional argument to make the signature match
the sibling function: addOptionalDataSymbol.
Differential Revision: https://reviews.llvm.org/D96305
Yaxun (Sam) Liu [Tue, 19 Jan 2021 22:35:23 +0000 (17:35 -0500)]
[CUDA][HIP] Add -fuse-cuid
This patch added a distinct CUID for each input file, which is represented by InputAction.
clang initially creates an InputAction for each input file for the host compilation. In CUDA/HIP action
builder, each InputAction is given a CUID and cloned for each GPU arch, and the CUID is also cloned. In this way,
we guarantee the corresponding device and host compilation for the same file shared the
same CUID. On the other hand, different compilation units have different CUID.
-fuse-cuid=random|hash|none is added to control the method to generate CUID. The default
is hash. -cuid=X is also added to specify CUID explicitly, which overrides -fuse-cuid.
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D95007
Dave Lee [Tue, 9 Feb 2021 01:33:53 +0000 (17:33 -0800)]
[lldb] Fix crash in FormatEntity for mangled-name
Check a `Block` pointer before dereferencing.
Using `function.mangled-name` led to a crash for a frame where the symbol
context had no block info. In my case, the frame's function was a system frame.
Differential Revision: https://reviews.llvm.org/D96307
Jinsong Ji [Tue, 9 Feb 2021 02:12:54 +0000 (02:12 +0000)]
Revert "[CostModel] Remove VF from IntrinsicCostAttributes"
This reverts commit
502a67dd7f23901834e05071ab253889f671b5d9.
This expose a failure in test-suite build on PowerPC,
revert to unblock buildbot first,
Dave will re-commit in https://reviews.llvm.org/D96287.
Thanks Dave.
Richard Smith [Tue, 9 Feb 2021 01:58:05 +0000 (17:58 -0800)]
PR48606: The lifetime of a constexpr heap allocation always started
during the same evaluation.
It looks like the only case for which this matters is determining
whether mutable subobjects of a heap allocation can be modified during
constant evaluation.
Richard Smith [Tue, 9 Feb 2021 01:32:52 +0000 (17:32 -0800)]
PR48587: is_constant_evaluated() should not evaluate to true during a
variable's destruction if it didn't do so during construction.
The standard doesn't give any guidance as to what to do here, but this
approach seems reasonable and conservative, and has been proposed to the
standard committee.
Fangrui Song [Tue, 9 Feb 2021 01:22:22 +0000 (17:22 -0800)]
[llvm-objcopy][test] Stablize build-id-link-dir.test
LLVM GN Syncbot [Tue, 9 Feb 2021 01:14:44 +0000 (01:14 +0000)]
[gn build] Port
87104faac433
Greg McGary [Sat, 26 Sep 2020 20:00:22 +0000 (13:00 -0700)]
[lld-macho] Add ARM64 target arch
This is an initial base commit for ARM64 target arch support. I don't represent that it complete or bug-free, but wish to put it out for review now that some basic things like branch target & load/store address relocs are working.
I can add more tests to this base commit, or add them in follow-up commits.
It is not entirely clear whether I use the "ARM64" (Apple) or "AArch64" (non-Apple) naming convention. Guidance is appreciated.
Differential Revision: https://reviews.llvm.org/D88629
Sam Clegg [Mon, 8 Feb 2021 02:51:42 +0000 (18:51 -0800)]
[MC][WebAssembly] Fix provisional values for data alias relocations
When calculating the symbol offsets to write as provisitonal values
in object files we are only interested in the offset of the symbol
itself. For aliases this offset already includes the offset of the
base symbol.
The testin question was added back in https://reviews.llvm.org/D87407
but I believe the expectations here were incorrect. sym_a lives
at offset 4 and sym_b lives 4 bytes into that (should be 8).
The addresses of the 3 symbosl in this object file are:
foo : 0
sym_a: 4
sym_b: 8
Differential Revision: https://reviews.llvm.org/D96234
Craig Topper [Tue, 9 Feb 2021 00:25:18 +0000 (16:25 -0800)]
[TableGen] Use return value from EmitVBRValue instead of calling GetVBRSize on the same value. Consistently use unsigned for child sizes. NFCI
getSize and setSize both use unsigned. So size_t doesn't
increase range here and might get truncated if passed to
setSize.
Also not sure why EmitVBRValue was returning uint64_t, but used
an unsigned to supply the value.
Uday Bondhugula [Sun, 7 Feb 2021 06:30:22 +0000 (12:00 +0530)]
[MLIR][NFC] Fix std.copysign op documentation
Fix std.copysign op documentation. NFC.
Differential Revision: https://reviews.llvm.org/D96217
Yaxun (Sam) Liu [Tue, 9 Feb 2021 00:27:17 +0000 (19:27 -0500)]
Fix failure in cuda-external-tools.cu
-fgpu-rdc is output in different order
LemonBoy [Tue, 9 Feb 2021 00:23:38 +0000 (19:23 -0500)]
[SPARC] Recognize and handle the %lm(sym) operator
Reviewed By: joerg
Differential Revision: https://reviews.llvm.org/D77737
Jameson Nash [Tue, 9 Feb 2021 00:11:08 +0000 (19:11 -0500)]
Revert "Renovate CMake files in the `llvm-exegesis` tool."
This reverts commit
549a1e2e59508d4aeaf9a93912b479798954bd5e.
I see some buildbot failures, so reverting while I look into them.
Argyrios Kyrtzidis [Mon, 8 Feb 2021 08:24:31 +0000 (00:24 -0800)]
Make sure a module file with errors produced via '-fallow-pcm-with-compiler-errors' can be loaded when using implicit modules
A module with errors would be marked as out-of-date, then the `compilerModule` action would produce it, but due to the error it would be treated as failure and the resulting PCM would not get used.
rdar://
74087062
Differential Revision: https://reviews.llvm.org/D96246
Yaxun (Sam) Liu [Mon, 8 Feb 2021 23:51:31 +0000 (18:51 -0500)]
[CUDA][HIP] Pass -fgpu-rdc to host clang -cc1
Currently -fgpu-rdc is not passed to host clang -cc1.
This causes issue because -fgpu-rdc affects shadow
variable linkage in host compilation.
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D96105
Eric Schweitz [Mon, 8 Feb 2021 21:47:16 +0000 (13:47 -0800)]
[flang][fir] Add OpaqueAttr.
Add the opaque attribute class used in flang.
https://github.com/flang-compiler/f18-llvm-project/pull/402
Differential Revision: https://reviews.llvm.org/D96293
Jameson Nash [Mon, 8 Feb 2021 23:20:16 +0000 (18:20 -0500)]
Renovate CMake file for the `llvm-cfi-verify` tool
Hopefully this is the non-problematic part from https://reviews.llvm.org/rL342148, which later got reverted in r342336 (
b09a8c9bd9b819741b38071a7ccd95042ef2643a) due to problems with the llvm-exegesis part of the change. That part would also still be desirable, but currently appears not to be possible (https://reviews.llvm.org/D81922).
I think this should replace https://reviews.llvm.org/D44650, per Keno's comment there.
Reviewed By: hctim
Differential Revision: https://reviews.llvm.org/D90969
Jameson Nash [Mon, 8 Feb 2021 23:03:23 +0000 (18:03 -0500)]
Renovate CMake files in the `llvm-exegesis` tool.
This attempts to move all tools over to using `add_llvm_library` for
better consistency. After doing this, I noticed it ended up as nearly a
reimplementation of https://reviews.llvm.org/rL342148, which later got
reverted in r342336 (
b09a8c9bd9b819741b38071a7ccd95042ef2643a).
With ccache and ninja on a large core machine (40), I haven't run into
build errors, so I'm hopeful it's better now, though it doesn't seem to
be any different / new.
Reviewed By: stephenneuendorffer
Differential Revision: https://reviews.llvm.org/D90970
Hsiangkai Wang [Wed, 27 Jan 2021 07:00:46 +0000 (15:00 +0800)]
[RISCV] Initial support of LoopVectorizer for RISC-V Vector.
Define an option -riscv-vector-bits-max to specify the maximum vector
bits for vectorizer. Loop vectorizer will use the value to check if it
is safe to use the whole vector registers to vectorize the loop.
It is not the optimum solution for loop vectorizing for scalable vector.
It assumed the whole vector registers will be used to vectorize the code.
If it is possible, we should configure vl to do vectorize instead of
using whole vector registers.
We only consider LMUL = 1 in this patch.
This patch just an initial work for loop vectorizer for RISC-V Vector.
Differential Revision: https://reviews.llvm.org/D95659
Matt Arsenault [Mon, 8 Feb 2021 21:53:42 +0000 (16:53 -0500)]
GlobalISel: Use correct calling convention in handleAssignments
This was using the calling convention of the calling function, not the
callee. Avoids regressions in a future patch.
Matt Arsenault [Sun, 7 Feb 2021 17:12:09 +0000 (12:12 -0500)]
AMDGPU: Stop adding stack passed wide arguments to call conv handler
The generated calling convention code shouldn't see these types since
we split large types into 32-bit chunks before the calling convention
code is triggered.
GlobalISel ends up directly calls the generated CC code before
checking for the register count breakdown. Arguably this difference is
a bug, but this was dead code for the DAG anyway.
Matt Arsenault [Sun, 7 Feb 2021 21:15:08 +0000 (16:15 -0500)]
AMDGPU/GlobalISel: Remove dead check prefixes
Arthur Eubanks [Mon, 8 Feb 2021 21:52:14 +0000 (13:52 -0800)]
[NVPTX][NewPM] Re-enable NVVMReflectPass
Disabled alongside NVVMIntrRangePass in https://reviews.llvm.org/D96166,
but turns out NVVMIntrRangePass was the issue.
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D96291
Eric Schweitz [Mon, 8 Feb 2021 21:49:16 +0000 (13:49 -0800)]
[flang][NFC] Add comment.
Fangrui Song [Mon, 8 Feb 2021 21:44:29 +0000 (13:44 -0800)]
[test] Fix unused check prefixes
Fangrui Song [Mon, 8 Feb 2021 21:37:03 +0000 (13:37 -0800)]
[FileCheck] Default --allow-unused-prefixes to false
Link: https://lists.llvm.org/pipermail/llvm-dev/2020-October/146162.html
If a downstream project using lit needs time for transition,
add the following to `lit.local.cfg`:
```
from lit.llvm.subst import ToolSubst
fc = ToolSubst('FileCheck', unresolved='fatal')
config.substitutions.insert(0, (fc.regex, 'FileCheck --allow-unused-prefixes'))
```
Differential Revision: https://reviews.llvm.org/D95849
Fangrui Song [Mon, 8 Feb 2021 21:31:05 +0000 (13:31 -0800)]
[Verifier] Allow DW_TAG_class_type/DW_TAG_union_type to have no filename
`clang/lib/CodeGen/CGOpenMPRuntime.cpp` synthesized union
(`distinct !DICompositeType(tag: DW_TAG_union_type, name: "kmp_cmplrdata_t", size: 64, elements: <0x62b690>)`)
does not have meaningful filename/line number.
D94735 dropped the previously arbitrary and untested filename/line from the union and caused a verifier error here.
This fixes `check-libarcher` failures.
Differential Revision: https://reviews.llvm.org/D96212
David Green [Mon, 8 Feb 2021 21:24:32 +0000 (21:24 +0000)]
[ARM] One-off identity shuffle
A One-Off Identity mask is a shuffle that is mostly an identity mask
from as single source but contains a single element out-of-place, either
from a different vector or from another position in the same vector. As
opposed to lowering this via a ARMISD::BUILD_VECTOR we can generate an
extract/insert pair directly. Under ARM with individually accessible
lane elements this often becomes a simple lane move.
This also alters the LowerVECTOR_SHUFFLEUsingMovs code to use v4f32 (not
v4i32), a more natural type for lane moves.
Differential Revision: https://reviews.llvm.org/D95551
Arthur Eubanks [Mon, 8 Feb 2021 20:52:20 +0000 (12:52 -0800)]
[SimpleLoopUnswitch] Don't non-trivially unswitch loops that are unsafe to clone
Non-trivial unswitching can clone loops.
The legacy -loop-unswitch pass also checks for this.
Fixes PR49085.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D96288
Nico Weber [Mon, 8 Feb 2021 21:10:59 +0000 (16:10 -0500)]
[gn build] reformat all gn files
$ git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format
Markus Böck [Mon, 8 Feb 2021 21:04:04 +0000 (23:04 +0200)]
[CMake] [MinGW] Enable use of LLVM_USE_SANITIZER in a MinGW environment
Currently using LLVM_USE_SANITIZER with a MinGW target leads to a fatal
configuration error due to an unsupported platform. MinGW targets on
clang however implement a few sanitizers, currently ASAN and UBSAN.
This patch enables LLVM_USE_SANITIZER in a MinGW environment as well.
Differential Revision: https://reviews.llvm.org/D95750
Amara Emerson [Wed, 3 Feb 2021 18:33:48 +0000 (10:33 -0800)]
[AArch64][GlobalISel] Support the 'returned' parameter attribute.
On AArch64 (which seems to be the only target that supports it), this
attribute allows codegen to avoid saving/restoring the value in x0
across a call.
Gives a 0.1% geomean -Os code size improvement on CTMark.
Differential Revision: https://reviews.llvm.org/D96099
Nico Weber [Mon, 8 Feb 2021 20:46:29 +0000 (15:46 -0500)]
Revert "[Test] Add failing test for PR49087"
This reverts commit
0fc1738eb75d613b9e16143b83e7cb80512e84eb.
The test passes (unexpectedly, due to the XFAIL: *) when x86 isn't
the default triple (such as on an arm machine).
Martin Storsjö [Mon, 8 Feb 2021 13:24:42 +0000 (15:24 +0200)]
[AArch64] Use '//' as comment string for MSVC assembly
As the actual MSVC toolset doesn't use the GAS-style assembly that
Clang/LLVM produces and consumes, there's no reference for what
string to use for e.g. comments when building with a MSVC triple.
This frees up the use of semicolon as separator string, just like
was done for GNU targets in
23413195649d0cf6f3860ae8b5fb115b35032075.
(Previously, both the separator and comment strings were set to
the same, a semicolon.)
Compiler-rt extensively uses separator chars in its assembly,
and that assembly should be buildable with clang-cl for MSVC too.
Differential Revision: https://reviews.llvm.org/D96259
Fangrui Song [Mon, 8 Feb 2021 20:29:11 +0000 (12:29 -0800)]
DebugInfo/Symbolize: Allow STT_NOTYPE/STT_GNU_IFUNC symbols for .symtab symbolization
In assembly files, omitting `.type foo,@function` is common. Such functions have
type `STT_NOTYPE` and llvm-symbolizer reports `??` for them.
An ifunc symbol usually has an associated resolver symbol which is defined at
the same address. Returning either one is fine for symbolization. The resolver
symbol may not end up in the symbol table if (object file) `.L` is used (linked
image) .symtab is stripped while .dynsym is retained.
This patch allows ELF STT_NOTYPE/STT_GNU_IFUNC symbols for .symtab symbolization.
I have left TODO in the test files for an unimplemented STT_FILE heuristic.
Differential Revision: https://reviews.llvm.org/D95916
Roland McGrath [Thu, 4 Feb 2021 03:28:29 +0000 (19:28 -0800)]
[scudo/standalone] Use .arch_extension memtag, not mte
GNU binutils accepts only `.arch_extension memtag` while Clang
accepts either that or `.arch_extension mte` to mean the same thing.
Reviewed By: pcc
Differential Revision: https://reviews.llvm.org/D95996
Eric Schweitz [Mon, 8 Feb 2021 20:10:43 +0000 (12:10 -0800)]
[flang][NFC] Update comments.
Jon Chesterfield [Mon, 8 Feb 2021 20:07:51 +0000 (20:07 +0000)]
[libomptarget][amdgcn] Fix language linkage post D95300, drop use of assert
Jianzhou Zhao [Fri, 5 Feb 2021 21:50:15 +0000 (21:50 +0000)]
[dfsan] Refactor visitCallBase
To simplify the review of https://reviews.llvm.org/D95835.
Reviewed-by: morehouse
Differential Revision: https://reviews.llvm.org/D96177
Jez Ng [Mon, 8 Feb 2021 19:50:13 +0000 (14:50 -0500)]
[lld-macho] Try to make ubsan happy
Summary: We should avoid passing a null pointer to memcpy.
Craig Topper [Mon, 8 Feb 2021 19:25:50 +0000 (11:25 -0800)]
[RISCV] Use _COMMUTABLE fma pseudos for fixed vectors.
This matches what we do in the VLMAX SDNode patterns.
Mitch Phillips [Mon, 8 Feb 2021 18:46:45 +0000 (10:46 -0800)]
[GWP-ASan] Add aligned allocations.
Adds a new allocation API to GWP-ASan that handles size+alignment
restrictions.
Reviewed By: cryptoad, eugenis
Differential Revision: https://reviews.llvm.org/D94830
Mircea Trofin [Mon, 8 Feb 2021 19:21:56 +0000 (11:21 -0800)]
Revert "[Utils] Add a switch controlling prefix warnings in UpdateTestChecks"
This reverts commit
87f8a08ce36e5bc72f11129d2cf36b5848f86f63.
Craig Topper [Mon, 8 Feb 2021 18:59:38 +0000 (10:59 -0800)]
[RISCV] Add support for splat fixed length build_vectors using RVV.
Building on the fixed vector support from D95705
I've added ISD nodes for vmv.v.x and vfmv.v.f and switched to
lowering the intrinsics to it. This allows us to share the same
isel patterns for both.
This doesn't handle splats of i64 on RV32 yet. The build_vector
gets converted to a vXi32 build_vector+bitcast during type
legalization. Not sure the best way to handle this at the moment.
Differential Revision: https://reviews.llvm.org/D96108
Craig Topper [Mon, 8 Feb 2021 18:45:45 +0000 (10:45 -0800)]
[RISCV] Add support for fixed vector FMA.
Follow up to D95705. Does not include the commuting support from D95800.
Differential Revision: https://reviews.llvm.org/D96103
Nicolas Vasilache [Mon, 8 Feb 2021 15:28:29 +0000 (15:28 +0000)]
[mlir][Linalg] Fix padding related bugs.
This revision fixes the fact that the padding transformation did not have enough information to set the proper type for the padding value.
Additionally, the verifier for Yield in the presence of PadTensorOp is fixed to properly report incorrect number of results or operands. Previously, the error would be silently ignored which made the core issue difficult to debug.
Differential Revision: https://reviews.llvm.org/D96264
Jez Ng [Mon, 8 Feb 2021 18:47:34 +0000 (13:47 -0500)]
[lld-macho] Emit LSDA info in compact unwind
The LSDA pointers are encoded as offsets from the image base,
and arranged in one big contiguous array. Each second-level page records
the offset within that LSDA array which corresponds to the LSDA for its
first CU entry.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D95810
Jez Ng [Mon, 8 Feb 2021 18:47:33 +0000 (13:47 -0500)]
[lld-macho] Emit personalities in compact unwind
Note that there is a triple indirection involved with
personalities and compact unwind:
1. Two bits of each CU encoding are used as an offset into the
personality array.
2. Each entry of the personality array is an offset from the image base.
The resulting address (after adding the image base) should point within the
GOT.
3. The corresponding GOT entry contains the actual pointer to the
personality function.
To further complicate things, when the personality function is in the
object file (as opposed to a dylib), its references in
`__compact_unwind` may refer to it via a section + offset relocation
instead of a symbol relocation. Since our GOT implementation can only
create entries for symbols, we have to create a synthetic symbol at the
given section offset.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D95809
Craig Topper [Mon, 8 Feb 2021 18:32:32 +0000 (10:32 -0800)]
[RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions.
This is an alternative to D95563.
This is modeled after a similar feature for AArch64's SVE that uses
predicated scalable vector instructions.a
Rather than use predication, this patch uses an explicit VL operand.
I've limited it to always use LMUL=1 for now, but we can improve this
in the future.
This requires a bunch of new ISD opcodes to carry the VL operand.
I think we can probably lower intrinsics to these ISD opcodes to
cut down on the size of the isel table. Which is why I've added
patterns for all integer/float types and not just LMUL=1.
I'm only testing one vector width right now, but the width is
programmable via the command line.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D95705
Fangrui Song [Mon, 8 Feb 2021 18:34:57 +0000 (10:34 -0800)]
[ELF] Inspect -EL & -EB for OUTPUT_FORMAT(default, big, little)
Choose big if -EB is specified, little if -EL is specified, or default if neither is specified.
The new behavior matches GNU ld.
Fixes: https://github.com/ClangBuiltLinux/linux/issues/1025
Differential Revision: https://reviews.llvm.org/D96214