Lukasz Luba [Fri, 11 Jan 2019 17:07:45 +0000 (18:07 +0100)]
arm: DT: exynos: add exynos5422 DMC device
The patch adds a new file with Dynamic Controller device and
accosiated performance counters. It provides definition of used clocks
and register sets.
Change-Id: I71d31db1f4c4f2be174adc735662f4c35f4dcf7d
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Lukasz Luba [Fri, 11 Jan 2019 17:00:39 +0000 (18:00 +0100)]
drivers: devfreq: exynos5: add DMC driver
This patch adds driver for Exynos5 Dynamic Memory Controller.
The driver provides support for DVFS in DMC and DRAM.
It also supports changing timings of DRAM running with different
frequency.
Change-Id: I98a630d1f0e6639bb160e0465302ae8f3800ef92
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Lukasz Luba [Fri, 11 Jan 2019 18:09:33 +0000 (19:09 +0100)]
clk: samsung: add new clocks for Exynos5422 SoC
This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422. It also defines new PLL rates for BPLL which is used
for DMC.
Change-Id: I85d151a19a176ef5ea8057b49b0afbfb778fe5a9
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Lukasz Luba [Fri, 11 Jan 2019 18:07:38 +0000 (19:07 +0100)]
clk: samsung: add needed IDs for DMC clocks in Exynos5420
Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.
Change-Id: Ic73d88601fa2c4631088300b930abefa25816158
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Marek Szyprowski [Fri, 7 Dec 2018 14:55:12 +0000 (15:55 +0100)]
LOCAL / PCI: workaround for PCI issues in system suspend/resume on TM2
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I31e72d43c2bc80c88049ec441aef4786839a1ff3
Marek Szyprowski [Fri, 7 Dec 2018 11:21:14 +0000 (12:21 +0100)]
LOCAL / PCI: exynos: add simple suspend/resume methods
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I255983c0cbd6ee19b39c9c229d21139a46dc22f4
Marek Szyprowski [Fri, 30 Nov 2018 09:30:17 +0000 (10:30 +0100)]
arm64: dts: exynos: Add sleep state for the sleep relevant pins
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ia3f96901af60d5a81f7c559b0111bb3ed1c2024b
Marek Szyprowski [Tue, 20 Nov 2018 14:25:47 +0000 (15:25 +0100)]
arm64: dts: exynos: Enable all PCIe regulators
According to schematic diagram, a part of PCIe is using
VDD10_MIPI2L_1.0V_AP. Enable it always for now.
Suggested-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I6a2742809237898419e417c983acb4d79eb6401f
Marek Szyprowski [Mon, 3 Dec 2018 14:43:20 +0000 (15:43 +0100)]
pinctrl: samsung: use NOIRQ phase for suspend/resume
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ibf8a51e77403bab519afa99ce826f060ec1f523e
Marek Szyprowski [Tue, 12 Jun 2018 10:55:23 +0000 (12:55 +0200)]
mmc: dw_mmc-exynos: fix potential external abort in resume_noirq()
dw_mci_exynos_resume_noirq() performs DWMMC register access without
ensuring that respective clocks are enabled. This might cause external
abort on some systems (observed on Exynos5433 based boards). Fix this
by forcing a PM runtime active state before register access. Using
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS allows also to cleanup conditional code
a bit.
Suggested-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Change-Id: I172ee95730a0f45b0a2f4dea002c59928f3b1e63
Marek Szyprowski [Tue, 11 Sep 2018 06:49:39 +0000 (08:49 +0200)]
serial: samsung: Enable baud clock for UART reset procedure in resume
Ensure that baud clock is also enabled for UART reset in driver resume.
On Exynos5433 SoC this is needed to avoid external abort in UART register
writes.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I2987842ea1b38582bdbceb9ffab3ed1a3b1cbfd2
Marek Szyprowski [Wed, 19 Sep 2018 09:36:55 +0000 (11:36 +0200)]
clk: samsung: exynos5433: add workaround for NOIRQ sleep
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I53b8969337a3464eb5cd5d877ce877670895836a
Marek Szyprowski [Fri, 11 May 2018 06:50:36 +0000 (08:50 +0200)]
clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume
cycle, otherwise TM2(e) boards hangs before entering the suspend mode.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I198880bcee0688c9e33b1e4056b8b60819303945
Marek Szyprowski [Wed, 29 Aug 2018 16:00:13 +0000 (18:00 +0200)]
clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
Before entering system suspend, one has to ensure that some clocks from
TOP, CPIF and PERIC CMUs are enabled. This is needed by the firmware
to properly perform system suspend operation. Instead of adding more and
more clocks with CRITICAL flag, simply enable those clocks directly in
respective CMU registers using 'suspend_regs' feature.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Change-Id: I1dab71d4834fcbd13634411d44ecb11775c46cde
Marek Szyprowski [Wed, 29 Aug 2018 16:00:12 +0000 (18:00 +0200)]
clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
SoC clock drivers should suspend after every other drivers in the system,
which are using clocks and resume before them. The last stage for calling
suspend device callbacks is NOIRQ stage and there exists driver, which use
that state (dwmmc-exynos), so Exynos5433 clocks driver should also use it.
During the same stage, clocks driver will be always suspended after its
clients as a direct result of proper device probe order (deferred probe
reorders the suspend call sequence).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Change-Id: I3e15407b8d3ec2d10d706b21321ce098b14a0d50
Marek Szyprowski [Wed, 29 Aug 2018 15:50:44 +0000 (17:50 +0200)]
clk: samsung: Add support for setting registers state before suspend
Some registers of clock controller have to be set to certain values before
entering system suspend state. Till now drivers did that on their own,
but it will be easier to handle it by generic code and let drivers simply
to provide the list of registers and their state.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I9038d2b135fb8a5402015cc9e709045b085b6e04
Marek Szyprowski [Mon, 11 Jun 2018 11:30:13 +0000 (13:30 +0200)]
drm/exynos: Ensure suspended runtime PM state during system suspend
Add calls to pm_runtime_force_{suspend,resume} as SYSTEM_SLEEP_PM_OPS for
all drivers for the real Exynos DRM hardware modules. This ensures that
the resources will be released for the system PM suspend/resume cycle.
Exynos DRM core already takes care of suspending the whole display pipeline
before PM callbacks of the real devices are called.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I29ad062624f110926a091dd6ad778e50de664986
Marek Szyprowski [Thu, 17 May 2018 06:46:07 +0000 (08:46 +0200)]
drm/exynos: Suspend/resume display pipeline as early/late as possible
In the current code, exynos_drm_suspend() function is called after all
real devices (CRTCs, Encoders, etc) are suspended, because Exynos DRM
virtual platform device is created as last device in the system (as
a part of DRM registration). None of the devices for real hardware
modules has its own system suspend/resume callbacks, so it doesn't
change any order of the executed code, but it has a side-effect:
runtime PM callbacks for real devices are not executed, because those
devices are considered by PM core as already suspended. This might
cause issues on boards with complex pipelines, where something
depends on the runtime PM state of the given device.
To ensure that exynos_drm_suspend() is called before any suspend
callback from the real devices, assign it to .prepare callback. Same
for exynos_drm_resume(), using .complete callback ensures that all
real devices have been resumed when calling it.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Icb178cecfbec2cb5b71b7a2ea70bf290c89198d2
Marek Szyprowski [Mon, 11 Jun 2018 10:52:33 +0000 (12:52 +0200)]
drm/exynos: Drop useless check from exynos_drm_{suspend,resume}
The virtual Exynos DRM device has no runtime PM enabled, so checking
for its runtime suspended state is useless.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I35a181ec0367f97613d2a3344c31705aacecff48
Marek Szyprowski [Mon, 21 May 2018 06:34:49 +0000 (08:34 +0200)]
pinctrl: samsung: Fix suspend/resume for Exynos5433 GPF1..5 banks
GPF1..5 banks in Exynos5433 are located in two pinctrl devices: ALIVE and
IMEM. Although they are partially located in ALIVE section, the state of
their registers in IMEM section is lost after suspend/resume cycle. To
properly handle such case, those banks have to be defined with standard
'exynos5433_bank_type_off' type (with PINCFG_TYPE_CON_PDN and
PINCFG_TYPE_PUD_PDN register offsets). This automatically instructs
the generic Samsung pinctrl suspend/resume code to save and restore state
of those registers.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Change-Id: Ib097dca4d0a3a44a9e6216461b0e97aa090d3b16
Marek Szyprowski [Tue, 18 Sep 2018 07:35:56 +0000 (09:35 +0200)]
arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs
Update DWC3 hardware modules to Exynos5433 specific variant: change
compatible name and add all required clocks (both to the glue node and
DWC3 core node).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I84cf27a3c55c59043b02f77d74070b325fd99acd
Marek Szyprowski [Tue, 18 Sep 2018 07:16:21 +0000 (09:16 +0200)]
usb: dwc3: exynos: Add support for Exynos5433 variant with all clocks
DWC3 variant found in Exynos5433 SoCs requires keeping all DRD30/UHOST30
clocks enabled all the time the driver does any access to DWC3 registers,
otherwise external abort happens. So far DWC3 hardware module worked with
samsung,exynos5250-dwusb3 compatible only by luck when built into kernel:
all DRD30 clocks were left enabled by bootloader and later kept enabled
by the DRD PHY driver. However, if one tried to use Exnos DWC3 driver as
a module or performed system suspend/resume cycle, external abort
happened. This patch finally fixes this issue.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: If2cff3c68c73ef288b47ec3fe623c8b904a1e067
Marek Szyprowski [Tue, 18 Sep 2018 07:15:54 +0000 (09:15 +0200)]
usb: dwc3: exynos: Rework clock handling and prepare for new variants
Add per-variant list of clocks and manage them all together in
the single array. This is a preparation for adding new variants
of Exynos SoCs. No functional changes for existing Exynos SoCs.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ib8f4c93445f88b82d08fe9e49aac60f465a44a3f
Marek Szyprowski [Mon, 17 Sep 2018 07:26:51 +0000 (09:26 +0200)]
usb: dwc3: exynos: Remove dead code
All supported Exynos variants provide respective generic PHY framework
based drivers for controlling USB PHYs, so there is no point
creating fake USB PHYs based on platform devices. While removing useless
code, remove calls to runtime PM, which have no effect.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I2c82d23cfe1daeea1b3b93f1f87de5757f17e451
Marek Szyprowski [Wed, 16 May 2018 08:34:13 +0000 (10:34 +0200)]
spi: spi-s3c64xx: Fix system resume support
Since Linux v4.10 release (commit
1d9174fbc55e "PM / Runtime: Defer
resuming of the device in pm_runtime_force_resume()"),
pm_runtime_force_resume() function doesn't runtime resume device if it was
not runtime active before system suspend. Thus, driver should not do any
register access after pm_runtime_force_resume() without checking the
runtime status of the device. To fix this issue, simply move
s3c64xx_spi_hwinit() call to s3c64xx_spi_runtime_resume() to ensure that
hardware is always properly initialized. This fixes Synchronous external
abort issue on system suspend/resume cycle on newer Exynos SoCs.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
CC: <stable@vger.kernel.org> # 4.10.x: 1c75862d8e5a spi: spi-s3c64xx: Remove unused s3c64xx_spi_hwinit()
CC: <stable@vger.kernel.org> # 4.10.x
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Andi Shyti <andi@etezian.org>
Change-Id: I34cb90a7eff4bf21162c232eb6308fb120d06d4a
Marek Szyprowski [Wed, 13 Jun 2018 12:55:45 +0000 (14:55 +0200)]
soc: samsung: Fix arm 32bit build break in Exynos PM code
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: If656a06064684707b4cea7d8cfb7f1e08c2c02f3
Marek Szyprowski [Tue, 15 May 2018 12:41:25 +0000 (14:41 +0200)]
soc: samsung: pmu: fix first suspend failure
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I68c1e0187cc6b7d533923092bc811dfa7daa9030
Marek Szyprowski [Tue, 15 May 2018 11:58:40 +0000 (13:58 +0200)]
soc: samsung: pmu: enable AUD power domain before the suspend
PMU system suspend procedure assumes that it has to turn off AUD power
domain and fails if AUD power domain is already turned off. To
make PMU happy enable AUD power domain when configuring suspend PMU
registers.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ieb338eb79b1d99ebd0bccdac837feb88619b2068
Marek Szyprowski [Mon, 14 May 2018 07:06:03 +0000 (09:06 +0200)]
clock_source: mct vs arch_timer - fix suspend/resume support
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I87d83c16fbcf5d0151c4f298cbb540a941a5606e
Marek Szyprowski [Wed, 12 Sep 2018 07:22:25 +0000 (09:22 +0200)]
arm64: dts: exynos: Mark 1.2GHz CPU OPPs as suitable for suspend on Exynos5433
Reduce speed of both CPU clusters to 1.2GHz for suspend/resume cycle on
Exynos5433 boards. Test on TM2(e) boards proved that this made
suspend/resume stable.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Icca296d13185cd26e16e231896e8cf1a0f5cdd68
Chanwoo Choi [Tue, 9 Jan 2018 07:59:04 +0000 (16:59 +0900)]
arm64: dts: exynos: Use power key as a wakeup source on TM2/TM2E board
This patch uses the power-key as a wakeup source from suspend/freeze state.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Change-Id: Iec001d32ab712bdc1ad36bdb86ed02a93395aec3
Chanwoo Choi [Thu, 11 Jan 2018 02:42:32 +0000 (11:42 +0900)]
pinctrl: samsung: Add LPDDR3_PAD_RETENTION to top domain
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Change-Id: Ia7004c2e252e1b58f88c61497e807523efe9bba8
Marek Szyprowski [Tue, 24 Jul 2018 09:06:08 +0000 (11:06 +0200)]
soc: samsung: pm: adapt to recent pinctrl changes
Adapt code to recent Exynos pinctrl changes. exynos_get_eint_wake_mask()
hack has been removed and EXYNOS5433_EINT_WAKEUP_MASK PMU register is
configured directly by the pinctrl driver.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I7ccf5f350b07a5454339c3bf528d959ba7666988
Chanwoo Choi [Mon, 8 Jan 2018 06:24:51 +0000 (15:24 +0900)]
soc: samsung: pm: Add support for suspend-to-ram of Exynos5433
Add the specific exynos_pm_data instance for Exynos5433 in order to
support the suspend-to-ram. Exynos5433 SoC need to write the 'cpu_resume'
poiter address and the specific magic number for suspend mode.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Change-Id: Ie879807ebf379ff9fdffa5965e547a733b8cda6d
Chanwoo Choi [Fri, 9 Mar 2018 07:17:12 +0000 (16:17 +0900)]
soc: samsung: Add generic power-management driver for Exynos
To enter suspend, Exynos SoC requires the some machine dependent procedures.
Introduce the generic power-management driver to support those requirements
and generic interface for power state management.
Change-Id: I585b9538e50f27310b860a8ccbc3776dec756a6a
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Chanwoo Choi [Tue, 9 Jan 2018 06:20:32 +0000 (15:20 +0900)]
soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state
Add the PMU (Power Management Unit) data of exynos5433 SoC
in order to support the various power modes. Each power mode has
the different value for reducing the power-consumption.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Change-Id: I60af59997bcc2f8ab994c4d02d52f91fd608c094
Krzysztof Kozlowski [Thu, 19 Jul 2018 10:37:12 +0000 (12:37 +0200)]
pinctrl: samsung: Remove legacy API for handling external wakeup interrupts mask
Remove the legacy, ugly API of exposing the static value of external
wakeup interrupts mask, because all arch-machine users where converted
to use generic implementation from pinctrl driver.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: I002a290e7600a3dfb2146a45e6f061cb7343f2c1
Krzysztof Kozlowski [Thu, 19 Jul 2018 10:38:17 +0000 (12:38 +0200)]
ARM: exynos: Remove legacy setting of external wakeup interrupts
Since Exynos/S5Pv210 pin-controller driver is taking care about setting
the external wakeup interrupts mask, the legacy code can be removed.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: I71e5b93c091f24a73c0df803c47f30320d3fe07b
Krzysztof Kozlowski [Thu, 19 Jul 2018 10:39:35 +0000 (12:39 +0200)]
ARM: s5pv210: Remove legacy setting of external wakeup interrupts
Since Exynos/S5Pv210 pin-controller driver is taking care about setting
the external wakeup interrupts mask, the legacy code can be removed.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: Id3dcaa57f6175054e77df3b17688d8d81e0d3797
Krzysztof Kozlowski [Thu, 19 Jul 2018 11:51:13 +0000 (13:51 +0200)]
ARM: dts: s5pv210: Switch to S5Pv210 specific pinctrl wakeup compatible
The pin controller block of S5Pv210 for handling external wakeup
interrupts is different than in newer designs (Exynos).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: I6d12df9f7df79ff4785ffabaa9fe62b5cf0a57c1
Krzysztof Kozlowski [Thu, 19 Jul 2018 10:19:10 +0000 (12:19 +0200)]
pinctrl: samsung: Write external wakeup interrupt mask
The pinctrl driver defines an IRQ chip which handles external wakeup
interrupts, therefore from logical point of view, it is the owner of
external interrupt mask. The register controlling the mask belongs to
Power Management Unit address space so it has to be accessed with PMU
syscon regmap handle.
This mask should be written to hardware during system suspend. Till now
ARMv7 machine code was responsible for this which created a dependency
between pin controller driver and arch/arm/mach code.
Try to rework this dependency so the pinctrl driver will write external
wakeup interrupt mask during late suspend.
Impact on ARMv7 designs (S5Pv210 and Exynos)
============================================
This duplicates setting mask with existing machine code
arch/arm/mach-exynos/suspend.c and arch/arm/mach-s5pv210/pm.c but it is
not a problem - the wakeup mask register will be written twice. The
machine code will be cleaned up later.
The difference between implementation here and ARMv7 machine code
(arch/arm/mach-*) is the time of writing the mask:
1. The machine code is writing the mask quite late during system suspend
path, after offlining secondary CPUs and just before doing actual
suspend.
2. The implementation in pinctrl driver uses late suspend ops, therefore it
will write the mask much earlier. Hopefully late enough, after all
drivers will enable or disable its interrupt wakeup
(enable_irq_wake() etc).
Impact on ARMv8 designs (Exynos5433 and Exynos7)
================================================
The Suspend to RAM was not supported and external wakeup interrupt mask
was not written to HW. This change brings us one step closer to
supporting Suspend to RAM.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: I7b3fb9f7e9b1b353c3842872d654ad8a22e7ec5d
Krzysztof Kozlowski [Thu, 19 Jul 2018 12:10:08 +0000 (14:10 +0200)]
ARM: exynos: Define EINT_WAKEUP_MASK registers for S5Pv210 and Exynos5433
S5Pv210 and Exynos5433/Exynos7 have different address of
EINT_WAKEUP_MASK register. Rename existing S5P_EINT_WAKEUP_MASK to
avoid confusion and add new ones.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: I60e1456faf90fd2413c7d0180b311cb599932516
Krzysztof Kozlowski [Thu, 19 Jul 2018 11:55:44 +0000 (13:55 +0200)]
pinctrl: samsung: Add dedicated compatible for S5Pv210 wakeup interrupts
The S5Pv210 external wakeup interrupts differ from Exynos therefore
separate compatible is needed. Duplicate existing flavor specific data
from exynos4210_wkup_irq_chip and add new compatible for S5Pv210.
At this point this new compatible does not bring anything new and works
exactly as existing "samsung,exynos4210-wakeup-eint".
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: I863f9ed6a0e8f2624428560bb6d9c18641556388
Krzysztof Kozlowski [Thu, 19 Jul 2018 10:34:27 +0000 (12:34 +0200)]
pinctrl: samsung: Document hidden requirement about one external wakeup
Hardware (S5Pv210 and all Exynos SoCs) provides only 32 external
interrupts which can wakeup device from deep sleep modes. On S5Pv210
these are gph0-gph3. On all Exynos designs these are gpx0-gpx3.
There is only one 32-bit register for controlling the external wakeup
interrupt mask (masking and unmasking waking capability of these
interrupts).
This lead to implementation in pinctrl driver and machine code which was
using static memory for storing the mask value and not caring about
multiple devices of pin controller... because only one pin controller
device will be handling this.
Since each pin controller node in Device Tree maps onto one device, this
corresponds to hidden assumption in parsing the Device Tree: external
wakeup interrupts can be defined only once. Make this assumption an
explicit requirement.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: I69ced8e994ab60b85ef509b59d50bf2f4589cf1d
Krzysztof Kozlowski [Thu, 19 Jul 2018 10:15:10 +0000 (12:15 +0200)]
pinctrl: samsung: Document suspend and resume members
Add missing documentation for suspend and resume members of struct
samsung_pin_ctrl and samsung_pinctrl_drv_data.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: I3bd0b3f1c3b1d47cc58282de30aa101346196ebb
Krzysztof Kozlowski [Thu, 19 Jul 2018 10:14:38 +0000 (12:14 +0200)]
pinctrl: samsung: Define suspend and resume callbacks for all banks and SoCs
Suspend and resume callbacks in Exynos/S5Pv210 pin controller drivers,
save and restore state of registers. This operations should be done for
all banks which have external interrupts (as denoted by using
EXYNOS_PIN_BANK_EINTG/EINTW macros).
Add all banks of Exynos5260 and Exynos5420. This is necessary step for
supporting suspend to RAM on these SoCs.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Change-Id: Ib70bae6682aed48f83999813adeb5dfbf540a947
Marek Szyprowski [Tue, 28 Aug 2018 12:02:04 +0000 (14:02 +0200)]
Revert "clk: samsung: exynos5433: Add clock flag to support suspend-to-ram"
This reverts commit
0061c5a84547bcb89d1ac9b578c455fb63f22c69.
Change-Id: I2b284f01b33d844c0b42216ab98faa825eca35d3
Junghoon Kim [Tue, 18 Dec 2018 01:57:05 +0000 (10:57 +0900)]
ARM: tizen_odroid_defconfig: enable DEVFREQ drivers
Enable DEVFREQ drivers and governors.
Change-Id: If32620cb0f8e0f4fe9490ec6a368af225c76d9c4
Signed-off-by: Junghoon Kim <jhoon20.kim@samsung.com>
Marek Szyprowski [Wed, 10 Oct 2018 18:25:58 +0000 (20:25 +0200)]
arm64: exynos: Enable generic power domain support
Generic power domains are needed to enable support for Exynos power
domains.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[backport of mainline commit
5220a73a409d9d31b42aa6624d5e901a612ec584]
Change-Id: I5cb1f0675ade71503d3caa75e1bc5ec39eb0ae7f
Marek Szyprowski [Thu, 8 Nov 2018 13:45:45 +0000 (14:45 +0100)]
extcon: max77843: Avoid forcing UART path on drive probe
Driver unconditionally forces UART path during probe, probably to ensure
that one can get kernel serial log as soon as possible.
This approach causes some issues, especially when board is booted with
non-UART cable connected to micro-USB port. For example, when USB cable is
connected, UART TX/RX lines are unconditionally short-circuited to USB
D+/D- lines. This is in turn recognized by a series of serial BREAK
signals and some random characters when USB host tries to perform
enumeration procedure.
To solve the above issue and keep UART console operational as early as
possible, set UART path only when USB ID reports UART capable cable.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
[backport of mainline commit
d9204acb37569579fc49af1689c0ae32bdd4710f]
Change-Id: I18608a07ed5cf5325470240304c6223ad9cc7cc5
Bartlomiej Zolnierkiewicz [Thu, 6 Dec 2018 17:15:18 +0000 (18:15 +0100)]
ARM: dts: Add missing CPU frequencies for Exynos5422/5800
Add missing 2.0GHz, 1.9GHz & 1.8GHz OPPs (for A15 cores) and 1.4GHz
OPP (for A7 cores). Also update common Odroid-XU3 Lite/XU3/XU4
thermal cooling maps to account for new OPPs.
Since some new OPPs are not available on all Exynos5422/5800 boards
modify dts files for Odroid XU3 Lite (limited to 1.8 GHz / 1.3 GHz) &
Peach Pi (limited to 2.0 GHz / 1.3 GHz) accordingly.
This patch uses maximum voltages for new OPPs. This is a temporary
solution till proper Exynos ASV support is added.
Also while at it fix the number of cooling down steps for big cores
(should be 11 instead of 12 on Odroid XU3 Lite and 14 on XU3/XU4).
Change-Id: I6bff20d0a6c5a0b9a0eff9b028ca00ac3ef56049
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Sylwester Nawrocki [Tue, 11 Dec 2018 10:39:05 +0000 (11:39 +0100)]
ARM: EXYNOS: Enable exynos-asv driver for ARCH_EXYNOS
Enable exynos-asv driver for Exynos 32-bit SoCs.
Change-Id: Ia5d2ff41f5dd64a48bc4e395c154b1e52c396ec5
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Sylwester Nawrocki [Fri, 7 Dec 2018 09:33:06 +0000 (10:33 +0100)]
soc: samsung: Add Exynos Adaptive Supply Voltage (ASV) driver
The purpose of exynos-asv driver added in this patch is to modify
CPU OPPs as defined in DT depending on exact SoC revision specified
by data available in the CHIP ID block.
This patch is based on hardkernel code:
https://github.com/hardkernel/linux/blob/odroidxu4-4.14.y/arch/arm/mach-exynos/exynos5422-asv.c
https://github.com/hardkernel/linux/blob/odroidxu4-4.14.y/arch/arm/mach-exynos/exynos5422-asv.h
Change-Id: I115c693684ed5e87d69d82f662a1a828ad1c998a
Signed-off by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Sylwester Nawrocki [Fri, 7 Dec 2018 09:33:43 +0000 (10:33 +0100)]
soc: samsung: exynos chipid driver update
This patch adds definition of selected CHIP ID register offsets
and register bit field definitions for Exynos5422 SoC.
exynos_chipid_read() helper function is added to allow reading
the CHIP ID block registers.
Change-Id: I69c12ea52c382f5f5da1dae6de692eab2772554c
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Pankaj Dubey [Thu, 15 Nov 2018 15:11:33 +0000 (16:11 +0100)]
ARM64: EXYNOS: enable exynos_chipid for ARCH_EXYNOS
This patch enables exynos_chipid driver for ARCH_EXYNOS
based SoC.
Change-Id: I465a3693821e181da12886e53e1f136e3e62a01b
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Pankaj Dubey [Thu, 15 Nov 2018 15:11:32 +0000 (16:11 +0100)]
ARM: EXYNOS: enable exynos_chipid for ARCH_EXYNOS
As now we have chipid driver to initialize SoC related information
let's include it in build by default.
Change-Id: Ie962e50c1c2f1ac085cdde0b9bcfb018e44a8663
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Pankaj Dubey [Thu, 15 Nov 2018 15:11:31 +0000 (16:11 +0100)]
soc: samsung: add exynos chipid driver support
Exynos SoCs have Chipid, for identification of product IDs and SoC
revisions. This patch intends to provide initialization code for all
these functionalities, at the same time it provides some sysfs entries
for accessing these information to user-space.
This driver uses existing binding for exynos-chipid.
Changes by Bartlomiej:
- fixed return values on errors
- removed bogus kfree_const()
- added missing Exynos4210 EVT0 id
- converted code to use EXYNOS_MASK define
- fixed np use after of_node_put()
- fixed too early use of dev_info()
- made driver fail for unknown SoC-s
- added SPDX tag
- updated Copyrights
Change-Id: I02ee0e759166f3722f61f108026aa8dc658a5608
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
[m.szyprowski: for suggestion and code snippet of product_id_to_soc_id]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Pankaj Dubey [Thu, 15 Nov 2018 15:11:30 +0000 (16:11 +0100)]
ARM: exynos: Remove secondary startup initialization from smp_prepare_cpus
We are taking care of setting secondary cpu boot address in
exynos_boot_secondary just before sending ipi to secondary CPUs,
so we can safely remove this setting from smp_prepare_cpus.
Change-Id: I2a3f839d7cc03d85df5b377b6f7175535dcc0604
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Jaehoon Chung [Wed, 5 Dec 2018 03:31:51 +0000 (12:31 +0900)]
ARM: configs: tizen_odroid: enable configs relevant to network feature
Eanble configs relevant to network feature.
In Tizen, stc-manager needs to enable these configurations to work fine.
This patch is form tizen branch commit
6b1405a4b2.
Change-Id: If34bce8b9b04ec6a2a50b05531475ce166085f7e
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung [Wed, 5 Dec 2018 03:26:03 +0000 (12:26 +0900)]
ARM: config: tizen_odroid: enable Atheros USB driver
Enable Atheros USB driver to test WiFi Mesh.
This patch is based on tizen branch commit
fe53e6f56.
Change-Id: I7b242b1e3b7f703a4db1542745153f3bba5a4931
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Inha Song [Tue, 4 Dec 2018 06:19:13 +0000 (15:19 +0900)]
packaging: use upstream tags with .gbs.conf
To build properly with upstream version tag in obs, add
.gbs.conf.
Change-Id: Ib6eaf6e12ecc8f065b085253dbcc0c538caff511
Signed-off-by: Inha Song <ideal.song@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Seung-Woo Kim [Tue, 4 Dec 2018 06:20:55 +0000 (15:20 +0900)]
packaging: change 4.14.y stable version as this tree
Change 4.14.y stable version as this tree.
Change-Id: I2f235f16e6e20e224a5fc33c6ff19230e25eab15
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Marek Szyprowski [Mon, 3 Dec 2018 13:37:01 +0000 (14:37 +0100)]
LOCAL / GPU: ARM: Add proper flag handle extended mmap offset operations
Since stable commit
16d7ceb04b55 ("mmap: introduce sane default mmap
limits"), drivers, which use mmap offset needs to set additional flag
in ->open() call, so set this flag in MALI drivers too.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Chanho Park [Tue, 27 Mar 2018 13:58:01 +0000 (22:58 +0900)]
pinctrl: samsung: add pin_dbg_show callback for debugfs
This patch adds a samsung_pin_dbg_show function to implement the
pin_dbg_show callback function which can be used to show pin
confuration values. Basically, it can show pin setting values by
accessing the "pins" node like below:
$ cat pins
pin 0 (gpy7-0) CON(0x0) DAT(0x1) PUD(0x1) DRV(0x0) CON_PDN(0x0) PUD_PDN(0x0)
Signed-off-by: Chanho Park <parkch98@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I20bf8c3201e08e23a8ba360a215facd91310e987
Inki Dae [Mon, 26 Nov 2018 00:33:42 +0000 (09:33 +0900)]
arm: dts: exynos5422: change mali node position in alphabet order
Change-Id: I8e0d490d51093488849f99f70d242f038863ba01
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Inki Dae [Fri, 23 Nov 2018 08:30:37 +0000 (17:30 +0900)]
arm: dts: exynos5422: change BPLL clock to 933MHz
This patch changes BPLL clock to 933MHz for DREX controller
can use maximum speed.
Change-Id: Ia06079c32ad532cb8a53d9dcae6a7fbacf80895a
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Inki Dae [Fri, 23 Nov 2018 08:29:31 +0000 (17:29 +0900)]
clk: samsung: add 933MHz clock to bpll
Change-Id: I9951d067e530e6bd9393cfe1fc7789be7ed06488
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Marek Szyprowski [Mon, 26 Nov 2018 15:09:11 +0000 (16:09 +0100)]
ARM: configs: tizen_odroid_defconfig: disable rotator IPP device
Disable rotator IPP device, because it confuses ipptest tool.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Iabd6a1fd31e93e56aa25c3c4de3e0e6ef3d30a37
Sylwester Nawrocki [Tue, 27 Nov 2018 16:44:24 +0000 (17:44 +0100)]
ARM: dts: exynos: Move some assigned-clock* properties to i2s0 node
Setting of an IP block clock parent clock should be in the IP's DT node,
this ensures respective driver sees correct parent clock right from the
beginning, i.e. right after registering clock provider in probe() callback.
Without this change wrong I2S function clock (op_clk) is being used by
the driver in runtime suspend/resume ops, i.e. i2s_bus is enabled/disabled
twice instead of having activated both i2s_bus and sclk_i2s when required.
Change-Id: I1b52e20ff3596dae7b09d6a65d8ac6da7b76fe7d
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Sylwester Nawrocki [Fri, 9 Mar 2018 17:48:55 +0000 (18:48 +0100)]
ASoC: samsung: i2s: Fix rclk_srcrate handling
As the RCLK clock may be updated through the common clk API before each
snd_soc_dai_ops::trigger call, it is not enough to update i2s->rclk_srcrate
only once after it has been initially set to 0. To avoid wrong PSR values
we always get RCLK frequency from the CLK_I2S_RCLK_SRC clock, when that
clock is available.
Fixes:
e1417fdf3011 "ASoC: samsung: i2s: Ensure the RCLK rate is properly determined"
Change-Id: I81065cf4e7da3c159a1f91bb0df626cdc0356c23
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Lukasz Luba [Mon, 19 Nov 2018 13:46:07 +0000 (14:46 +0100)]
arm: dts: exynos4: opp-suspend in DMC and leftbus
Mark the state for devfreq device while entring suspend/resume process.
The patch is based on earlier work by Tobias Jakobi.
Change-Id: I2b82fcb2a405abd15bea1e480bca1a1328bd6ff9
Suggested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Suggested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Lukasz Luba [Fri, 16 Nov 2018 12:36:53 +0000 (13:36 +0100)]
drivers: power: suspend: call devfreq suspend/resume
Devfreq framework supports suspend of its devices.
Call the the devfreq interface and allow devfreq devices preserve/restore
their states during suspend/resume.
The patch is based on earlier work by Tobias Jakobi.
Change-Id: I1aa62a13466120ef6f88edec2637888d77edc981
Suggested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Lukasz Luba [Fri, 16 Nov 2018 12:33:53 +0000 (13:33 +0100)]
devfreq: add devfreq_suspend/resume() functions
This patch adds implementation for global suspend/resume for
devfreq framework. System suspend will next use these functions.
The patch is based on earlier work by Tobias Jakobi.
Change-Id: Id48187e492eb11f532512ecdda736309bc094af4
Suggested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Suggested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Lukasz Luba [Thu, 15 Nov 2018 14:26:10 +0000 (15:26 +0100)]
devfreq: add support for suspend/resume of a devfreq device
The patch prepares devfreq device for handling suspend/resume
functionality. The new fields will store needed information during this
process. Devfreq framework handles opp-suspend DT entry and there is no
need of modyfications in the drivers code. It uses atomic variables to
make sure no race condition affects the process.
The patch is based on earlier work by Tobias Jakobi.
Change-Id: I55187da468966b11b27f7d90e1e59471fb602422
Suggested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Suggested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Lukasz Luba [Thu, 15 Nov 2018 15:12:43 +0000 (16:12 +0100)]
devfreq: refactor set_target frequency function
The refactoring is needed for the new client in devfreq: suspend.
To avoid code duplication, move it to the new local function
devfreq_set_target.
The patch is based on earlier work by Tobias Jakobi.
Change-Id: I8515ba9cde9b957b47684ff36296bfeab54f76f6
Suggested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Suggested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Marek Szyprowski [Mon, 26 Nov 2018 14:24:52 +0000 (15:24 +0100)]
ARM64: dts: exynos: Add clocks and pins needed for bluetooth chip
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I99cab815d6b756b4ea27f83286e8fe27ad1d08d9
Beomho Seo [Thu, 26 Feb 2015 08:54:50 +0000 (17:54 +0900)]
mfd: exynos-lpass: Enable UART module support
This patch enables support for UART module in AUD subsystem. There are
boards (for example TM2), which use it for communication with bluetooth
chip.
Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
[mszyprow: rephrased commit message, added UART reset]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I4f189b64baca4865d119d7e931c1ce608a5908bd
Seung-Woo Kim [Thu, 15 May 2014 03:35:50 +0000 (12:35 +0900)]
tty: serial: samsung: Increase maximum baudrate
This driver can be used to communicate with bluetooth chip in high-speed
UART mode, so increase maximum baudrate to 3Mbps.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
[mszyprow: rephrased commit message]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ifd046553dfd9f4f469f58ded785844631c1ef08e
Inki Dae [Fri, 23 Nov 2018 07:18:36 +0000 (16:18 +0900)]
ARM: dts: exynos: change vpll clock to 600MHz
This change enhances MALI inference(on-device deep leanring) performance.
Change-Id: I2a9341589873a049bd91ee6771c96d831768df3c
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Inki Dae [Fri, 23 Nov 2018 07:06:33 +0000 (16:06 +0900)]
clk: samsung: add vpll pms tables
This patch adds pms tables to generate various clock frequencies.
In default, VPLL generates 400MHz but it's not enough for MALI GPU
device so it allows to change vpll clock frequency through device tree.
Change-Id: Iae8c55d03a4efc40ecc7966c4591572f27e4a81a
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Inki Dae [Fri, 23 Nov 2018 07:15:39 +0000 (16:15 +0900)]
Revert "ARM: dts: exynos: set g3d parent clock to dpll"
We don't need to change parent clock of mali gpu device.
Instead, we can change vpll clock frequency through device tree,
and it's a better way because vpll is dedicated to gpu device
in default.
This reverts commit
d78913aca3abe06124e71b63f7171f83c666d85a.
Change-Id: Ib4770fba8df4a55d04ca8587af0458c9d3f8882c
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Inki Dae [Fri, 23 Nov 2018 01:37:11 +0000 (10:37 +0900)]
ARM: dts: exynos: set g3d parent clock to dpll
MALI GPU device uses VPLL as its parent clock which generates
400MHz clock so it's not enough for MALI GPU device.
This patch changes g3d parent clock to dpll which generates
600MHz.
Change-Id: I42f0a8c13ec8eec8e91f73ba210e3c0cbcb596d0
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Inki Dae [Fri, 23 Nov 2018 01:29:01 +0000 (10:29 +0900)]
clk: samsung: exynos542x: add clock ID for G3D performance enhancement
This patch adds clock IDs for CLKMUX_ACLK_G3D and DPLL_CTRL,
and these IDs will be used by device tree to change G3D's parent
clock to DPLL(600MHz) instead of VPLL(400MHz).
Change-Id: Ia2c11331d42a73e095fd4c9deb64e9fb162c511d
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Inki Dae [Mon, 19 Nov 2018 01:52:54 +0000 (10:52 +0900)]
ARM: dts: exynos5420: add mali dt bindings
Change-Id: I850b32a6be2be6ada5344e26e4af636360e9cfbc
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Inki Dae [Mon, 19 Nov 2018 08:12:47 +0000 (17:12 +0900)]
packaging: packaging: Add spec file for TM2 and Odroid-XU3/4
Change-Id: Iefcde80b71ac44f5c3aff8206a61175e524b4e12
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Maciej Purski [Tue, 23 Jan 2018 11:13:16 +0000 (12:13 +0100)]
drm/bridge/sii8620: fix HDMI cable connection to dongle
MHL bridge is usually connected to TV via MHL dongle. Currently plugging
HDMI cable to dongle is handled improperly.
Fix it by splitting connecting of a dongle and a HDMI cable. The driver
should now handle unplugging a sink from a dongle and plugging a
different sink with new edid.
Tested on MHL1, MHL2 and MHL3 using various vendors' dongles both in
DVI and HDMI mode.
Signed-off-by: Maciej Purski <m.purski@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1516705996-8928-1-git-send-email-m.purski@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I74dcc6ff2cec4c926ad3107a99d6987aabeebf09
Maciej Purski [Wed, 29 Nov 2017 15:12:47 +0000 (16:12 +0100)]
drm/bridge/sii8620: remove HSIC initialization
HSIC initialization was taken from the vendor code. HSIC in MHL circuit
is not connected, so it is not possible to test it. Tests prove that
without HSIC the device works well. Therefore it can be removed.
Signed-off-by: Maciej Purski <m.purski@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1511968368-30884-1-git-send-email-m.purski@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I619d5eabbc04fa4d9134378cabd529682c9d114a
Maciej Purski [Wed, 29 Nov 2017 11:48:50 +0000 (12:48 +0100)]
drm/bridge/sii8620: start MHL transmission after HDMI signal detection
The vendor code waits for infoframe to detect video mode set by source.
We do not need to follow this pattern, because video mode information is
provided by drm core. As a result most of the infoframe handling
code can be removed.
Start transmission immediately after detecting stream on HDMI lines
in irq_scdt() function without waiting for infoframe interrupt.
Signed-off-by: Maciej Purski <m.purski@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1511956130-24482-1-git-send-email-m.purski@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I4c437ae8340f0a896429c752a2e9c5a210a6f6f8
Maciej Purski [Fri, 2 Feb 2018 10:54:25 +0000 (11:54 +0100)]
drm/bridge/sii8620: fix display modes validation
Current implementation of mode_valid() and mode_fixup() callbacks
handle packed pixel modes improperly.
Fix it by using proper maximum clock values from the documentation.
Signed-off-by: Maciej Purski <m.purski@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1517568865-25219-1-git-send-email-m.purski@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ia6782c6302a1d75e3970fba420a0fed2a13a6530
Andrzej Hajda [Fri, 8 Jun 2018 06:04:57 +0000 (08:04 +0200)]
drm/bridge/sii8620: simplify hardware reset procedure
There is no need to flip reset pin twice. Also delays can be changed to
values present in vendor's code.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Maciej Purski <m.purski@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180608060457.18357-1-a.hajda@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ib7710bedc9f5dbdd448262d44f83c2c80c208ac5
Marek Szyprowski [Tue, 29 May 2018 08:18:47 +0000 (10:18 +0200)]
drm/exynos: scaler: Fix support for YUV420, YUV422 and YUV444 modes
Fix Cb/CR components order in two-planar YUV420, YUV422 and YUV444 modes.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ib71dd82d3a0cd9e742d97a18b4999f8d22a0c544
Marek Szyprowski [Mon, 28 May 2018 12:34:39 +0000 (14:34 +0200)]
drm/exynos: gsc: Increase Exynos5433 buffer width alignment to 16 pixels
Investigation revealed that GScaler hardware requires the real buffer width
(pitch) to be aligned to 16 pixels.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I27ddbdb73fdcdfbfc4b90e76242196f72be91c98
Marek Szyprowski [Mon, 28 May 2018 12:10:14 +0000 (14:10 +0200)]
drm/exynos: gsc: Use real buffer width for configuring the hardware
DMA hardware should respect buffer pitch, so use the width calculated from
the buffer pitch instead of the virtual one.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Id35299775cb6064e4c0af4542c34061223ff9d16
Marek Szyprowski [Mon, 28 May 2018 12:03:20 +0000 (14:03 +0200)]
drm/exynos: ipp: Rework checking for the correct buffer formats
Prepare a common function for size and scale checks and call it for
source and destination buffers. Then also move there the state-less checks
from exynos_drm_ipp_task_setup_buffer, so the format information is already
available in limits processing. Finally perform the IPP_LIMIT_BUFFER check
on the real width of the buffer (the width calculated from the provided
buffer pitch).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I7bd24c4448f27abf5dcbcf19045d30bbcdd4ee87
Marek Szyprowski [Fri, 25 May 2018 11:02:55 +0000 (13:02 +0200)]
drm/exynos: rotator: Fix DRM_MODE_REFLECT_{X,Y} interpretation
Horizontal (DRM_MODE_REFLECT_Y) and vertical (DMR_MODE_REFLECT_Y) flip
were swapped in Rotator driver. Fix this by swapping code for interpreting
them.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ic6aef7b463ebb89fd217092f129427303102641b
Marek Szyprowski [Fri, 25 May 2018 11:02:26 +0000 (13:02 +0200)]
drm/exynos: gsc: Fix DRM_MODE_REFLECT_{X,Y} interpretation
Horizontal (DRM_MODE_REFLECT_Y) and vertical (DMR_MODE_REFLECT_Y) flip
were swapped in GScaler driver. Fix this by swapping code for interpreting
them.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ie442b31ef85f698e163af1a4c745311c9074ceb3
Andrzej Pietrasiewicz [Mon, 5 Feb 2018 15:41:54 +0000 (16:41 +0100)]
drm/exynos: scaler: Reset hardware before starting the operation
Ensure that Scaler hardware is properly reset and interrupts are cleared
before processing next image.
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I036118b95bdf37e1c6dd133606746f2d6fce4758
Marek Szyprowski [Wed, 23 May 2018 09:21:19 +0000 (11:21 +0200)]
drm/exynos: decon: Add support for hardware windows no 4 and 5
Enable support for 2 more hardware windows. This require enabling a few
more clocks and set proper plane type for all windows. In the new
configuration primary plane uses hardware window no 3 and cursor uses
window no 5. The remaining hardware windows are used for overlays. This
gives us an overlay plane both below and above primary plane for both
Decon and DeconTV (which uses hardware window nr 0 for background).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I1c9947d040cb9af24dd7b7ec5ce7aa80845d3c9b
Marek Szyprowski [Wed, 23 May 2018 09:14:53 +0000 (11:14 +0200)]
drm/exynos: Fix default value for zpos plane property
The default zpos property for all planes in Exynos DRM was fixed as zero.
Fix this by providing proper value provided by hardware drivers, which
typically matches hardware window number.
Reported-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ie7caf48e2560d05338778a2d71f1d7f0016a9950
Marek Szyprowski [Wed, 23 May 2018 09:12:27 +0000 (11:12 +0200)]
arm64: dts: exynos: Add more clocks to Exynos5433 Decon and DeconTV
Add all '1x' clocks to decon and decontv devices. Enabling those clocks
is needed to get proper display on hardware windows no 4 and 5.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I47043438d55591f0202e8ddf3cf4cf86bfa4a9f3
projects / platform / kernel / linux-exynos.git / log