Jay Foad [Mon, 6 Feb 2023 15:42:39 +0000 (15:42 +0000)]
[AMDGPU] Fix DOS line endings in some tests
serge-sans-paille [Thu, 26 Jan 2023 07:41:14 +0000 (08:41 +0100)]
Reapply
6fa2abf90886f18472c87bc9bffbcdf4f73c465e
Lazyly initialize uncommon toolchain detector
Cuda and rocm toolchain detectors are currently run unconditionally,
while their result may not be used at all. Make their initialization
lazy so that the discovery code is not run in common cases.
Reapplied since
77910ac374656319ff114ef251fda358d4aa166a landed and
fixes the test ordering issue.
Differential Revision: https://reviews.llvm.org/D142606
zhijian [Mon, 6 Feb 2023 15:43:29 +0000 (10:43 -0500)]
[NFC] add new function is64Bit for SymbolicFile class
Summary:
since the class 'SymbolicFile ' do not have a is64Bit() API , when we need to check whether a SymbolicFile object is 64bit or not. we need to write a function to do it, it maybe cause duplication code.
Reviewers: James Henderson, Fangrui Song
Differential Revision: https://reviews.llvm.org/D143097
Simon Pilgrim [Mon, 6 Feb 2023 15:20:02 +0000 (15:20 +0000)]
[X86] combineConcatVectorOps - add X86ISD::VPERMV handling
Simon Pilgrim [Mon, 6 Feb 2023 14:28:51 +0000 (14:28 +0000)]
[X86] combineConcatVectorOps - merge 256-bit logic ops on AVX2+
AVX1 doesn't benefit as nearly all integer ops will stay as 128-bit ops.
This only exposes a couple of minor changes but will be a lot more useful in an upcoming shuffle combining patch.
John Brawn [Mon, 30 Jan 2023 14:34:14 +0000 (14:34 +0000)]
[extract_symbols.py] Better handling of templates
Since commit 846b676 SmallVectorBase<uint32_t> has been explicitly
instantiated, which means that clang.exe must export it for a plugin
to be able to link against it, but the constructor is not exported as
currently no template constructors or destructors are exported.
We can't just export all constructors and destructors, as that puts us
over the symbol limit on Windows, so instead rewrite how we decide
which templates need to be exported to be more precise. Currently we
assume that templates instantiated many times have no explicit
instantiations, but this isn't necessarily true and results also in
exporting implicit template instantiations that we don't need
to. Instead check for references to template members, as this
indicates that the template must be explicitly instantiated (as if it
weren't the template would just be implicitly instantiated on use).
Doing this reduces the number of symbols exported from clang from
66011 to 53993 (in the build configuration that I've been testing). It
also lets us get rid of the special-case handling of Type::getAs, as
its explicit instantiations are now being detected as such.
Differential Revision: https://reviews.llvm.org/D142989
Craig Topper [Mon, 6 Feb 2023 15:29:31 +0000 (07:29 -0800)]
[X86] Change precision control to FP80 during u64->fp32 conversion on Windows.
This is an alternative to D141074 to fix the problem by adjusting
the precision control dynamically.
Reviewed By: icedrocket
Differential Revision: https://reviews.llvm.org/D142178
Jonathan Peyton [Mon, 6 Feb 2023 15:26:44 +0000 (09:26 -0600)]
[OpenMP][libomp] Remove false positive for memory sanitizer
The memory sanitizer intercepts the memcpy() call but not the direct
assignment of last byte to 0. This leads the sanitizer to believe the
last byte of a string based on the kmp_str_buf_t type is uninitialized.
Hence, the eventual strlen() inside __kmp_env_dump() leads to an
use-of-uninitialized-value warning.
Using strncat() instead gives the sanitizer the information it needs.
Differential Revision: https://reviews.llvm.org/D143401
Fixes #60501
Mark de Wever [Tue, 31 Jan 2023 19:50:08 +0000 (20:50 +0100)]
[libc++][CI] Uses LLVM 17 in Docker.
Updates the LLVM versions used in the Dockerfile. It also removes
obsolete symlinks. This doesn't update the Buildkite jobs, they need to
use the new Docker image before they can be updated.
Reviewed By: ldionne, #libc, philnik
Differential Revision: https://reviews.llvm.org/D143007
Craig Topper [Mon, 6 Feb 2023 15:14:37 +0000 (07:14 -0800)]
[RISCV] Remove DecoderMethod from C_NOP_HINT. NFC
This doesn't appear to be needed.
Differential Revision: https://reviews.llvm.org/D143367
Craig Topper [Mon, 6 Feb 2023 15:11:10 +0000 (07:11 -0800)]
[RISCV] Make 'c.addi x0, imm' an alias for 'c.nop imm'.
Instead of making it an AsmParserOnly instruction, make it an alias.
This makes printing consistent with disassembly.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D143362
Matthias Springer [Mon, 6 Feb 2023 15:17:45 +0000 (16:17 +0100)]
[mlir][bufferization] Fix bufferization of repetitive regions
The previous strategy was too complex and faulty. Op dominance cannot be used to rule out RaW conflicts due to op ordering if the reading op and the conflicting writing op are in a sub repetitive region of the closest enclosing repetitive region of the definition of the read value.
Differential Revision: https://reviews.llvm.org/D143087
Yaxun (Sam) Liu [Mon, 9 Jan 2023 21:50:15 +0000 (16:50 -0500)]
[HIP] Support ASAN with malloc/free
Device side malloc/free needs special
implementation for ASAN.
Reviewed by: Artem Belevich, Matt Arsenault
Differential Revision: https://reviews.llvm.org/D143111
Matthias Springer [Mon, 6 Feb 2023 15:10:23 +0000 (16:10 +0100)]
[mlir][bufferization] Reads from tensors with undefined data are not a conflict
Reading from tensor.empty or bufferization.alloc_tensor (without copy) cannot cause a conflict because these ops do not specify the contents of their result tensors.
Differential Revision: https://reviews.llvm.org/D143183
serge-sans-paille [Mon, 6 Feb 2023 15:02:21 +0000 (16:02 +0100)]
[clang] Reorder output of rocm-detect.hip test
Since
6fa2abf90886f18472c87bc9bffbcdf4f73c465e the rocm driver is lazily
loaded, which impacts the output of the rocm-detect.hip test.
Jonas Hahnfeld [Mon, 6 Feb 2023 14:39:33 +0000 (15:39 +0100)]
Revert "Lazyly initialize uncommon toolchain detector"
clang/test/Driver/rocm-detect.hip is failing for a number of
configurations, for example:
clang-x86_64-debian-fast
https://lab.llvm.org/buildbot/#/builders/109/builds/57270
clang-debian-cpp20
https://lab.llvm.org/buildbot/#/builders/249/builds/310
clang-with-lto-ubuntu
https://lab.llvm.org/buildbot/#/builders/124/builds/6693
This reverts commit
6fa2abf90886f18472c87bc9bffbcdf4f73c465e.
Jean Perier [Mon, 6 Feb 2023 14:14:08 +0000 (15:14 +0100)]
[flang][hlfir] deref pointers before lowering assignment to hlfir.assign
There is little point not to dereference pointers LHS and RHS before
before emitting an hlfir.assign when lowering an assignment.
This pushes complexity and descriptor read side effects that are better
expressed in a load before the assignment.
Differential Revision: https://reviews.llvm.org/D143372
Pratik Sharma [Mon, 6 Feb 2023 14:11:26 +0000 (09:11 -0500)]
Fix broken link to CxxCodeBrowser in External Clang Examples
Replaced the dead link with the correct link in ExternalClangExamples.rst
Differential Revision: https://reviews.llvm.org/D143343
Fixes https://github.com/llvm/llvm-project/issues/60142
David Green [Mon, 6 Feb 2023 14:05:26 +0000 (14:05 +0000)]
[AArch64] Don't create ST2 for 64bit store that requires an EXT
A 64bit st2 which does not start at element 0 will involved adding extra ext
elements, making the st2 unprofitable. This prevents that case which can lead
to a few less instructions.
Differential Revision: https://reviews.llvm.org/D142966
Haojian Wu [Fri, 3 Feb 2023 16:08:45 +0000 (17:08 +0100)]
[clangd] Remove the direct use of StdSymbolMapping.inc usage.
Replace them with the library APIs.
Differential Revision: https://reviews.llvm.org/D143274
Aaron Ballman [Mon, 6 Feb 2023 13:34:31 +0000 (08:34 -0500)]
Update status of WG21 DR1042
We've supported attributes on alias declarations at least as far back
as Clang 3.5 from my testing. This also updates the RUN lines to test
the newer language modes as well.
Alex Zinenko [Mon, 23 Jan 2023 14:46:46 +0000 (14:46 +0000)]
[mlir] more side effect verification in transform dialect
Add a verifier checking that if a transform operation consumes a handle
(which is associated with a payload operation being erased or
recreated), it also indicates modification of the payload IR. This
hasn't been consistent in the past because of the "no-aliasing"
assumption where we couldn't have had more than one handle to an
operation, requiring some handle-manipulation operations, such as
`transform.merge_handles` to consume their operands. That assumption has
been liften and it is no longer necessary for these operations to
consume handles and thus make the life harder for the clients.
Additionally, remove TransformEffects.td that uses the ODS mechanism for
indicating side effects that works only for operands and results. It
was being used incorrectly to also indicate effects on the payload IR,
not assocaited with any IR value, and lacked the consume/produce
semantics available via helpers in C++.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D142361
Vladislav Vinogradov [Mon, 6 Feb 2023 11:31:20 +0000 (14:31 +0300)]
[mlir][NFC] Use fully qualified C++ namespaces in .td files.
Add missing llvm:: and mlir:: namespaces qualifiers to some auto-generated code.
Reviewed By: ftynse, springerm
Differential Revision: https://reviews.llvm.org/D143381
Bjorn Pettersson [Mon, 6 Feb 2023 10:29:17 +0000 (11:29 +0100)]
Remove no longer needed includes of LegacyPassManager.h
Most of the removed includes should probably have been removed already
when we removed TargetMachine::adjustPassManager.
Bjorn Pettersson [Mon, 6 Feb 2023 10:00:37 +0000 (11:00 +0100)]
[CodeGen] Remove some not needed includes in BackendUtil.cpp
Getting rid of some include dependencies that seem to be outdated.
Petar Avramovic [Mon, 6 Feb 2023 12:18:41 +0000 (13:18 +0100)]
AMDGPU/MC: Fix indentation and remove unused macro after D142636
Backl1ght [Mon, 6 Feb 2023 10:47:11 +0000 (18:47 +0800)]
[clang-format] PackConstructorInitializers support PCIS_OnlyNextLine
fixes https://github.com/llvm/llvm-project/issues/60241
Differential Revision: https://reviews.llvm.org/D143091
Timm Bäder [Mon, 6 Feb 2023 11:36:25 +0000 (12:36 +0100)]
[clang][NFC] Fix a documentation typo
gonglingqin [Thu, 2 Feb 2023 02:10:35 +0000 (10:10 +0800)]
[LoongArch] Add baseline tests for optimizations that merge offsets into instructions
Florian Hahn [Mon, 6 Feb 2023 11:30:14 +0000 (11:30 +0000)]
[LV] Also check interleaving only in select-min-index.ll
The new combination exposed a crash in earlier versions of
D132063.
Christian Ulmann [Mon, 6 Feb 2023 11:14:13 +0000 (12:14 +0100)]
[mlir][llvm] Add missing license header (NFC)
This commit adds a missing license header that was forgotten in
https://reviews.llvm.org/D143064.
Markus Böck [Sun, 5 Feb 2023 13:58:06 +0000 (14:58 +0100)]
[mlir][MemRef] Add required address space cast when lowering alloc to LLVM
alloc uses either `malloc` or a plugable allocation function for allocating the required memory. Both of these functions always return a `llvm.ptr<i8>`, aka a pointer in the default address space. When allocating for a memref in a different memory space however, no address space cast is created, leading to invalid LLVM IR being generated.
This is currently not caught by the verifier since the pointer to the memory is always bitcast which currently lacks a verifier disallowing address space casts. Translating to actual LLVM IR would cause the verifier to go off, since bitcast cannot translate from one address space to another: https://godbolt.org/z/3a1z97rc9
This patch fixes that issue by generating an address space cast if the address space of the allocation function does not match the address space of the resulting memref.
Not sure whether this is actually a real life problem. I found this issue while converting the pass to using opaque pointers which gets rid of all the bitcasts and hence caused type errors without the address space cast.
Differential Revision: https://reviews.llvm.org/D143341
serge-sans-paille [Thu, 26 Jan 2023 07:41:14 +0000 (08:41 +0100)]
Lazyly initialize uncommon toolchain detector
Cuda and rocm toolchain detectors are currently run unconditionally,
while their result may not be used at all. Make their initialization
lazy so that the discovery code is not run in common cases.
Differential Revision: https://reviews.llvm.org/D142606
David Green [Mon, 6 Feb 2023 10:54:18 +0000 (10:54 +0000)]
[ARM][AArch64] Regenerate hadd tests. NFC
This just runs the existing tests through opt -O1, which helps canonicalizing
the code and adds additional flags which can be useful for matching.
Tom Eccles [Wed, 1 Feb 2023 15:41:29 +0000 (15:41 +0000)]
[flang][NFC] Move IntrinsicCall to Optimizer/Builder/ 6/6
This will allow IntrinsicCall to be used in passes to implement hlfir
transformational intrinsic operations.
Differential Revision: https://reviews.llvm.org/D143084
Tom Eccles [Wed, 1 Feb 2023 15:29:01 +0000 (15:29 +0000)]
[flang][NFC] Move intrinsic name mangling to IntrinsicCall 5/6
This removes another dependency of IntrinsicCall upon flang/lib/Lower:
making it possible to move IntrinsicCall into flang/lib/Optimizer.
Differential Revision: https://reviews.llvm.org/D143083
Tom Eccles [Wed, 1 Feb 2023 15:22:14 +0000 (15:22 +0000)]
[flang][NFC] remove duplicate fir::toInt definition 4/6
Differential Revision: https://reviews.llvm.org/D143082
Tom Eccles [Wed, 1 Feb 2023 15:14:11 +0000 (15:14 +0000)]
[flang][NFC] Move runtime helpers used by intrinsics to lib/Optimizer 3/6
This will allow IntrinsicCall to be moved into lib/Optimizer later.
Differential Revision: https://reviews.llvm.org/D143081
Tom Eccles [Wed, 1 Feb 2023 13:55:36 +0000 (13:55 +0000)]
[flang][NFC] remove spurious dependency from IntrinsicCall 2/6
Differential Revision: https://reviews.llvm.org/D143080
Tom Eccles [Wed, 1 Feb 2023 11:54:36 +0000 (11:54 +0000)]
[flang][NFC] remove stmtCtx genIntrinsicCall 1/6
This removes IntrinsicCall's dependency upon StatementContext, which
will make it easier to move IntrinsicCall into flang/lib/Optimizer, for
use in passes.
Differential Revision: https://reviews.llvm.org/D143079
Simon Pilgrim [Mon, 6 Feb 2023 09:55:03 +0000 (09:55 +0000)]
[TLI] SimplifyMultipleUseDemandedBits - remove insert_subvector(undef, x, 0) fold
SimplifyMultipleUseDemandedBits shouldn't be creating general nodes on the fly, it should mainly just peek through them (although we do currently allow creation of new bitcasts and constant folding).
This is mostly a win - by avoiding new nodes we avoid a lot of hasOneUse limitations inside x86 shuffle combining - the main regressions I've noticed are where we've ended up with multiple insert_subvector(undef, x, 0) nodes, widening x to different vector widths - that should hopefully be improved when we remove the last of the vector widening from combineX86ShufflesRecursively for Issue #45319
David Spickett [Fri, 3 Feb 2023 11:06:34 +0000 (11:06 +0000)]
[libc] Fix pthread argument for scudo integration tests when using GCC
This adds "-pthreads" which appears to be a clang only
alias for "-pthread" (all the drivers check for both).
Use "-pthread" instead to be compatible with gcc.
Otherwise you get:
FAILED: bin/libc-gwp-asan-uaf-should-crash
: && /usr/bin/g++-11 <...> -pthreads <...> projects/libc/test/integration/scudo/liblibc_for_scudo_integration_test.a && :
g++-11: error: unrecognized command-line option ‘-pthreads’; did you mean ‘-pthread’?
Reviewed By: michaelrj
Differential Revision: https://reviews.llvm.org/D143258
Matthias Springer [Mon, 6 Feb 2023 09:19:22 +0000 (10:19 +0100)]
[mlir][tensor][bufferize] tensor.empty does not define the result tensor contents
This is encoded in the `BufferizableOpInterface` via `resultBufferizesToMemoryWrite = false`.
Differential Revision: https://reviews.llvm.org/D143181
chenglin.bi [Mon, 6 Feb 2023 09:23:02 +0000 (17:23 +0800)]
[Instcombine] precommit tests for icmp with intrinsic look through trunc; NFC
Tobias Gysi [Mon, 6 Feb 2023 09:13:02 +0000 (10:13 +0100)]
[mlir][llvm] Drop opaque ptr test in LLVM IR import.
After switching all LLVM IR import tests to opaque pointers
the specialized opaque pointer test file is redundant.
Reviewed By: Dinistro
Differential Revision: https://reviews.llvm.org/D143370
Chuanqi Xu [Mon, 6 Feb 2023 09:11:22 +0000 (17:11 +0800)]
[Modules] Recreate file manager for ftime-trace when compiling a module
Close https://github.com/llvm/llvm-project/issues/60544.
The root cause for the issue is that when we compile a module unit, the
file manager (and proprocessor and source manager) are owned by AST
instead of the compilaton instance. So the file manager may be invalid
when we want to create a time-report file for -ftime-trace when we are
compiling a module unit.
This patch tries to recreate the file manager for -ftime-trace if we
find the file manager is not valid.
chenglin.bi [Mon, 6 Feb 2023 09:16:25 +0000 (17:16 +0800)]
[InstCombine] precommit tests for icmp with bool range; NFC
Kevin Sala [Mon, 6 Feb 2023 09:12:55 +0000 (10:12 +0100)]
[NFC][OpenMP][libomptarget] Fix format in PluginInterface header
Philipp Tomsich [Sat, 4 Feb 2023 16:59:32 +0000 (17:59 +0100)]
[RISCV][NFC] Update debug message for XTHeadVdot
As we prepare the tree to add more vendor-defined extensions that are
originating with T-Head, the debug message announcing the XTheadVdot
decoder namespace should refer to XTHeadVdot instead of all T-Head
custom extensions.
Tobias Gysi [Mon, 6 Feb 2023 09:01:27 +0000 (10:01 +0100)]
[mlir][llvm] Fix bug in constant import from LLVM IR.
The revision addresses a bug during constant expression traversal
when importing LLVM IR. A constant expression may have cyclic
dependencies, for example, when a constant is initialized with its
address. This revision extends the constant expression traversal
to detect cyclic dependencies and adds a test to verify this
case is handled properly.
Reviewed By: Dinistro
Differential Revision: https://reviews.llvm.org/D143152
Kevin Sala [Wed, 25 Jan 2023 00:04:07 +0000 (01:04 +0100)]
[OpenMP][libomptarget] Notify the plugins regarding new mapping/unmappings
The NextGen plugins use the information regarding new mapping/unmappings to
lock/unlock the corresponding host buffer and speed up the host-device memory
transfers involving those buffers. The locking/unlocking is disabled by default
and can be enabled by the LIBOMPTARGET_LOCK_MAPPED_HOST_BUFFERS envar. The
envar accepts boolean values (on/off) and a special option:
- off: Do not lock mapped host buffers (default).
- on: Lock mapped host buffers automatically, but do not report lock
failures if the plugin fails to lock them.
- mandatory: Lock mapped host buffers automatically and treat locking failures
in the plugins as fatal errors. This option may be useful for
debugging purposes.
Differential Revision: https://reviews.llvm.org/D142514
Guillaume Chatelet [Mon, 6 Feb 2023 09:03:55 +0000 (09:03 +0000)]
[NFC] Inline variable
Nathan Ridge [Mon, 30 Jan 2023 08:09:00 +0000 (03:09 -0500)]
[clangd] Semantic highlighting for constrained-parameter
Differential Revision: https://reviews.llvm.org/D142871
Rainer Orth [Mon, 6 Feb 2023 08:30:36 +0000 (09:30 +0100)]
[Release] Increase test-release.sh verbosity
`test-release.sh` is too silent in some cases:
- Only the build proper is run verbosely, but `check-all` is not.
- `lit` is run without `-v`, so in case of failures one cannot see what's
actually wrong.
This patch fixes both issues, running all `${MAKE}` invocations with
`$Verbose` (except for `${MAKE} install` where it would only add noise),
and running `lit` with `-v`.
Tested on `x86_64-pc-linux-gnu` and `arm64-apple-darwin21.6`.
Differential Revision: https://reviews.llvm.org/D143249
Jean Perier [Mon, 6 Feb 2023 07:53:57 +0000 (08:53 +0100)]
[flang][hlfir] Lower asInquired intrinsic arguments
Differential Revision: https://reviews.llvm.org/D143272
Jean Perier [Mon, 6 Feb 2023 07:51:56 +0000 (08:51 +0100)]
[flang][hlfir] Turn fir.char<1> results into hlfir.expr<fir.char<1>>
This gets rid of a special case with CHAR() intrinsic and BIND(C) results.
I tested this has no impact on the LLVM assembly when LLVM opt -01 or
more is run.
See comment in the patch for more details.
Differential Revision: https://reviews.llvm.org/D143270
Craig Topper [Mon, 6 Feb 2023 07:12:22 +0000 (23:12 -0800)]
[RISCV] Use uint32_t intead of uint64_t for instruction fields in RISCVDisassembler.cpp. NFC
The tablegen generated code is templated based on the type of Insn
passed to decodeInstruction which is currently uint32_t. All of the
fields extracted will this type.
Craig Topper [Mon, 6 Feb 2023 06:42:57 +0000 (22:42 -0800)]
[RISCV] Simplify some code in RISCVDisassembler. NFC
Create X0 register directly instead of passing 0 to DecodeGPRRegisterClass.
Ruiling Song [Thu, 2 Feb 2023 05:59:59 +0000 (13:59 +0800)]
AMDGPU: Mark control flow intrinsics non-duplicable
This is used to help get simplified CFG for divergent regions as well as
get better code generation in some cases.
For example, with below IR:
```
define amdgpu_kernel void @test() {
bb:
br label %bb1
bb1:
%tmp = phi i32 [ 0, %bb ], [ %tmp5, %bb4 ]
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%cnd = icmp eq i32 %tid, 0
br i1 %cnd, label %bb4, label %bb2
bb2:
%tmp3 = add nsw i32 %tmp, 1
br label %bb4
bb4:
%tmp5 = phi i32 [ %tmp3, %bb2 ], [ %tmp, %bb1 ]
store volatile i32 %tmp5, ptr addrspace(1) undef
br label %bb1
}
```
We got below assembly before the change:
```
v_mov_b32_e32 v1, 0
v_cmp_eq_u32_e32 vcc, 0, v0
s_branch .LBB0_2
.LBB0_1: ; %bb4
; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s2, -1
s_mov_b32 s3, 0xf000
buffer_store_dword v1, off, s[0:3], 0
s_waitcnt vmcnt(0)
.LBB0_2: ; %bb
; =>This Inner Loop Header: Depth=1
s_and_saveexec_b64 s[0:1], vcc
s_xor_b64 s[0:1], exec, s[0:1]
; kill: def $sgpr0_sgpr1 killed $sgpr0_sgpr1 killed $exec
s_cbranch_execnz .LBB0_1
; %bb.3: ; %bb2
; in Loop: Header=BB0_2 Depth=1
s_or_b64 exec, exec, s[0:1]
s_waitcnt expcnt(0)
v_add_i32_e64 v1, s[0:1], 1, v1
s_branch .LBB0_1
```
After the change:
```
s_mov_b32 s0, 0
v_cmp_eq_u32_e32 vcc, 0, v0
s_mov_b32 s2, -1
s_mov_b32 s3, 0xf000
v_mov_b32_e32 v0, s0
s_branch .LBB0_2
.LBB0_1: ; %bb4
; in Loop: Header=BB0_2 Depth=1
buffer_store_dword v0, off, s[0:3], 0
s_waitcnt vmcnt(0)
.LBB0_2: ; %bb1
; =>This Inner Loop Header: Depth=1
s_and_saveexec_b64 s[0:1], vcc
s_cbranch_execnz .LBB0_1
; %bb.3: ; %bb2
; in Loop: Header=BB0_2 Depth=1
s_or_b64 exec, exec, s[0:1]
s_waitcnt expcnt(0)
v_add_i32_e64 v0, s[0:1], 1, v0
s_branch .LBB0_1
```
We are using one less VGPR, one less s_xor_, and better LICM with one
additional branch after the change. Please note the experiment
was done with reverting the workaround D139780, as it will stop the
tail-duplication completely for this case.
Reviewed by: arsenm
Differential Revision: https://reviews.llvm.org/D118250
Adrian Kuegel [Mon, 6 Feb 2023 07:02:28 +0000 (08:02 +0100)]
[mlir] Use mlir::TypedValue to avoid compiler bug in MSVC.
Kazu Hirata [Mon, 6 Feb 2023 06:45:46 +0000 (22:45 -0800)]
Revert "[lldb] Fix warning about unhandled enum value `WasmExternRef` (NFC)."
This reverts commit
b27e4f72213e78cacf0ce5bfd127261ec0b9309b.
bccf5999d38f14552f449618c1d72d18613f4285 necessitates this revert.
Vitaly Buka [Mon, 6 Feb 2023 05:26:19 +0000 (21:26 -0800)]
Revert "[clang][WebAssembly] Initial support for reference type externref in clang"
Very likely breaks stage 3 of msan build bot.
Good:
764c88a50ac76a2df2d051a0eb5badc6867aabb6 https://lab.llvm.org/buildbot/#/builders/74/builds/17058
Looks unrelated:
48b5a06dfcab12cf093a1a3df42cb5b684e2be4c
Bad:
48b5a06dfcab12cf093a1a3df42cb5b684e2be4c https://lab.llvm.org/buildbot/#/builders/74/builds/17059
This reverts commit
eb66833d19573df97034a81279eda31b8d19815b.
Ganesh Gopalasubramanian [Mon, 6 Feb 2023 04:16:12 +0000 (09:46 +0530)]
[X86] Add RMPQUERY to SNP instructions
Add RMPQUERY to the list of SNP instructions.
Tech Documentation: https://www.amd.com/system/files/TechDocs/24594.pdf
Reviewed By: RKSimon, craig.topper
Differential Revision: https://reviews.llvm.org/D141458
Siva Chandra Reddy [Tue, 10 Jan 2023 08:01:51 +0000 (08:01 +0000)]
[bootstrap build] Add libc-hdrgen as a build dep for libc bootstrap build.
With this change, libc-hdrgen is built like a host build tool like clang and used
to build libc for the target.
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D141460
Craig Topper [Mon, 6 Feb 2023 01:36:03 +0000 (17:36 -0800)]
[RISCV] Use decodeSImmNonZeroOperand for simm6nonzero and decodeUImmNonZeroOperand for uimmlog2xlennonzero.
Roland McGrath [Mon, 6 Feb 2023 02:15:10 +0000 (18:15 -0800)]
[RISCV] Default to -fsanitize=shadow-call-stack for Fuchsia
The ShadowCallStack is the preferred and default ABI for Fuchsia.
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D143357
Petr Hosek [Mon, 6 Feb 2023 02:47:31 +0000 (02:47 +0000)]
Revert "[CMake] Support runtimes targets without specifying triple"
This reverts commit
e6975c4ced27fe93945393603df79557aeb23d83 since it
broke the bootstrapping build on Windows.
Roland McGrath [Mon, 6 Feb 2023 02:29:55 +0000 (18:29 -0800)]
[RISCV] Default to -ffixed-x18 for Fuchsia
Fuchsia's ABI always reserves the x18 (s2) register for the
ShadowCallStack ABI, even when -fsanitize=shadow-call-stack is
not enabled.
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D143355
Roland McGrath [Mon, 6 Feb 2023 02:09:20 +0000 (18:09 -0800)]
[RISCV] Use OS-specific stack-guard ABI for Fuchsia
Fuchsia provides a slot relative to tp for the stack-guard value,
which is cheaper to materialize than the default GOT load.
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D143353
Fangrui Song [Mon, 6 Feb 2023 02:26:07 +0000 (18:26 -0800)]
[RISCV] clang-format #include. NFC
sstwcw [Mon, 6 Feb 2023 00:57:03 +0000 (00:57 +0000)]
[clang-format] Recognize Verilog non-blocking assignment
Reviewed By: HazardyKnusperkeks, owenpan
Differential Revision: https://reviews.llvm.org/D142891
Fangrui Song [Mon, 6 Feb 2023 00:34:22 +0000 (16:34 -0800)]
[docs] Replace deprecated -target with --target=
Rahul Kayaith [Sun, 5 Feb 2023 23:57:50 +0000 (18:57 -0500)]
[flang] Fix driver option tests after
90094ab8
David Turner [Sun, 5 Feb 2023 21:19:11 +0000 (13:19 -0800)]
[clang-format] Fix inconsistent annotation of operator&
Token annotator incorrectly annotates operator& as a reference type in
situations like Boost serialization archives:
https://www.boost.org/doc/libs/1_81_0/libs/serialization/doc/tutorial.html
Add annotation rules for standalone and chained operator& instances while
preserving behavior for reference declarations at class scope. Add tests to
validate annotation and formatting behavior.
Differential Revision: https://reviews.llvm.org/D141959
David Green [Sun, 5 Feb 2023 20:59:49 +0000 (20:59 +0000)]
[ARM] Remove FlattenVectorShuffle and add PerformVQDMULHCombine.
This removes the FlattenVectorShuffle that folds shuffles through certain
binops. This is now handled by generic DAG combines for all but ARMISD::VQDMULH
where a PerformVQDMULHCombine is added to compensate. It pushes identical
shuffles down through the operation, in a similar way to the other combines in
DAG.
Craig Topper [Sun, 5 Feb 2023 20:31:36 +0000 (12:31 -0800)]
[RISCV] Fix bug where C_ADDI_HINT_IMM_ZERO was incorrectly disassembled as C_ADDI.
And was then printed as 'mv'.
Stanislav Mekhanoshin [Fri, 3 Feb 2023 23:21:31 +0000 (15:21 -0800)]
[AMDGPU] Fix liveness in the SIOptimizeExecMaskingPreRA.cpp
If a condition register def happens past the newly created use
we do not properly update LIS. It has two problems:
1) We do not extend defining segment to the end of its block
marking it a live-out (this is regression after
https://reviews.llvm.org/rG09d38dd7704a52e8ad2d5f8f39aaeccf107f4c56)
2) We do not extend use segment to the beginning of the use block
marking it a live-in.
Fixes: SWDEV-379563
Differential Revision: https://reviews.llvm.org/D143302
Simon Pilgrim [Sun, 5 Feb 2023 20:16:32 +0000 (20:16 +0000)]
[X86] combineX86ShufflesRecursively - peek through free extract_subvector nodes
If we're shuffling an op that is extracted from the lowest subvector of a larger vector then we should try to peek through as much as possible without exceeding the root size
Another step towards removing the widenSubVector call from combineX86ShufflesRecursively (Issue #45319)
Simon Pilgrim [Sun, 5 Feb 2023 19:21:40 +0000 (19:21 +0000)]
[SLP] Use allConstant helper. NFCI.
Fangrui Song [Sun, 5 Feb 2023 18:46:43 +0000 (10:46 -0800)]
[AArch64] Unconditionally use DW_EH_PE_indirect|DW_EH_PE_pcrel personality/lsda/ttype encodings
For -fno-pic, without DW_EH_PE_indirect, the personality routine pointer in a
CIE needs an R_AARCH64_ABS64 relocation. In common configurations that
`__gcc_personality_v0` is defined in a shared object, this will lead to a
discouraged canonical PLT entry, or, if `ld.lld -z notext` (betwen D122459 and
D143136), a dynamic R_AARCH64_ABS64 relocation with an incorrect offset:
https://github.com/llvm/llvm-project/issues/60392
Since GCC uses DW_EH_PE_indirect for -fno-pic code (the behavior hasn't changed
since the initial port in 2012), let's follow suit by simplifying the code.
(
For tiny and small code models, we use DW_EH_PE_sdata8 instead of GCC's
DW_EH_PE_sdata4. This is a deliberate choice to support personality-.eh_frame
offset > 2GiB. This is unneeded for small code model since "Max text segment
size < 2GiB" but making `-fno-pic -mcmodel={tiny,small}` different seems
unnecessary: the scenarios that uses both -fno-pic and C++ exceptions have been
increasingly rare now, so there is little advantage optimizing for the little
size saving with code complexity.
)
---
Two clang/test/Interpreter tests would fail without
6747fc07d1aa94e22622e278e5a02ba70675ac9b
([ORC] Use JITLink as the default linker for LLJIT on Linux/arm64.)
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D143039
Fangrui Song [Sun, 5 Feb 2023 18:29:58 +0000 (10:29 -0800)]
[Driver] Add -mllvm= as an alias for -mllvm
Similar to D131455 (-Xclang=). As well as making it convenient for some build
systems, this allows `-Xarch_device '-mllvm=--inline-threshold=100'` (and
`-Xarch_host`; so we don't need to allow space separators which are uncommon in
driver code).
Bear in mind that -mllvm options are unstable and should be avoided if possible.
Reviewed By: jhuber6, yaxunl
Differential Revision: https://reviews.llvm.org/D143325
Matt Arsenault [Tue, 31 Jan 2023 18:23:56 +0000 (14:23 -0400)]
DAG: Fix broken lowering of is.fplcass fcZero with DAZ
is.fpclass x, fcZero is not equivalent to fcmp with 0 if
denormals are treated as 0. It would be equivalent to fcZero|fcSubnormal
which can be done separately; this is the minimal correctness fix.
The same optimization was not ported to the GlobalISel version.
Matt Arsenault [Sun, 11 Dec 2022 21:43:46 +0000 (16:43 -0500)]
InstCombine: Fold is.fpclass (fabs x), mask -> is.fpclass x, (fabs mask)
Matt Arsenault [Sun, 11 Dec 2022 20:23:26 +0000 (15:23 -0500)]
InstCombine: Fold is.fpclass (fneg x) into the test mask
Matt Arsenault [Thu, 17 Nov 2022 04:51:40 +0000 (20:51 -0800)]
InstCombine: Fold out is_fpclass inf checks from test mask for known finite sources
Make the partner transform already done for nnan sources.
Simon Pilgrim [Sun, 5 Feb 2023 13:07:20 +0000 (13:07 +0000)]
[X86] combineINSERT_SUBVECTOR - fold (insert_subvector X, (insert_subvector undef, Y, 0), Idx) -> (insert_subvector X, Y, Idx)
Helps some shuffle combines that do a poor job of peeking through (insert_subvector undef, Y, 0) vector widening patterns
Matt Arsenault [Fri, 11 Nov 2022 00:15:34 +0000 (16:15 -0800)]
InstCombine: Perform basic isnan combines on llvm.is.fpclass
is.fpclass(x, qnan|snan) -> fcmp uno x, 0.0
is.fpclass(nnan x, qnan|snan|other) -> is.fpclass(x, other)
Start porting the existing combines from llvm.amdgcn.class to the
generic intrinsic. Start with the ones which aren't dependent on the
FP mode.
Paul Walker [Sun, 15 Jan 2023 15:21:20 +0000 (15:21 +0000)]
[SVE][Builtins] Lower X forms of binop arithmetic builtins to dedicated intrinsics.
This patch changes the lowering for the following builtins to emit
calls to the new aarch64.sve.###.u intrinsics.
svabd_x
svabd_n_x
svadd_x
svadd_n_x
svasr_x
svasr_n_x
svdiv_x
svdiv_n_x
svdivr_x
svdivr_n_x
svlsl_x
svlsl_n_x
svlsr_x
svlsr_n_x
svmax_x
svmax_n_x
svmin_x
svmin_n_x
svmul_x
svmul_n_x
svmulh_x
svmulh_n_x
svsub_x
svsub_n_x
svsubr_x
svsubr_n_x
Depends on D141938
Differential Revision: https://reviews.llvm.org/D141939
Matt Arsenault [Tue, 6 Dec 2022 14:16:27 +0000 (09:16 -0500)]
LangRef: Clarify behavior of llvm.is.fpclass with "denormal-fp-math"
This does not read canonicalized values, which matches the behavior of
the basic DAG expansion using integer operations. There is a buggy
expansion using FP-operations if legal which needs to be adjusted to
account for this. We need to be aware of the denormal mode to switch
between is.fpclass calls and fcmp.
There's no real spec for denormal handling anywhere, but I believe
this is the most harmonious way to deal with the question considering
the requirement to not quiet input signaling nans.
This matches the behavior of MSVC's _fpclass and AMDGPU's
v_cmp_class_f32. fpclassify currently does not use this, and has
inconsistent behavior for denormals under DAZ on different platforms
(i.e. clang and gcc report FP_ZERO return FP_ZERO for a denormal under
DAZ, MSVC reports FP_SUBNORMAL).
Matt Arsenault [Thu, 5 Jan 2023 16:00:35 +0000 (11:00 -0500)]
IROutliner: Fix another assert with non-0 alloca addrspaces
Code is inserting an addrspacecast it shouldn't be, but
that's a separate CodeExtractor bug.
This also stops caring about typed pointers.
David Green [Sun, 5 Feb 2023 10:28:54 +0000 (10:28 +0000)]
[DAG] Add visitABD optimizations
This adds basic a visitABD to optimize ABDS and ABDU nodes, similar to the
existing visitAVG method.
The fold I was initially interested in was folding shuffles though the binop.
This also:
- Marks ABDS and ABDU as commutative binops (https://alive2.llvm.org/ce/z/oCDogb
and https://alive2.llvm.org/ce/z/7zrs86).
- Add reassociative folds.
- Add constant folding using max(x,y)-min(x,y)
- Canonicalizes constants to the RHS
- Folds abds x, 0 -> abs(x) (https://alive2.llvm.org/ce/z/4ZEibv)
- Folds abdu x, 0 -> x (https://alive2.llvm.org/ce/z/J_rKqx)
- Folds abd x, undef -> 0 (https://alive2.llvm.org/ce/z/NV6Nsv and
https://alive2.llvm.org/ce/z/vs92hu).
Differential Revision: https://reviews.llvm.org/D143193
Jonas Hahnfeld [Tue, 24 Jan 2023 09:54:55 +0000 (10:54 +0100)]
[ORC] Drop Comdat when discarding IR symbol
According to the IR verifier, "Declaration[s] may not be in a Comdat!"
This is a re-commit of
76b3f0b4d5a0b8c54147c4c73a30892bbca76467 and
87d7838202267a011639fcbf97263556ccf091dc with updates to the test:
* Force emission of the extra-module, to trigger the bug after D138264,
by providing a second symbol @g, and making the comdat nodeduplicate.
(Technically only one is needed, but two should be safer.)
* Name the comdat $f to avoid failure on Windows:
LLVM ERROR: Associative COMDAT symbol 'c' does not exist.
* Mark the test as UNSUPPORTED on macOS, MachO doesn't support COMDATs.
Differential Revision: https://reviews.llvm.org/D142443
Simon Pilgrim [Sun, 5 Feb 2023 09:38:15 +0000 (09:38 +0000)]
[AArch64] AArch64ExpandImm.cpp - fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC.
Matt Arsenault [Thu, 26 Jan 2023 00:46:44 +0000 (20:46 -0400)]
AMDGPU: Ensure flat loads are broken into dword in functions
We were assuming we could rely on the flat scratch init detection
to imply if there are possible flat addressed stack objects, which
doesn't work outside of a kernel. We should have a way to prove
if a given flat access can't access the stack.
We could use a not-stack parameter attribute to avoid
these splits.
Make the minimally correct change for GlobalISel; I'll address
this better in my larger patch to rewrite load and store legalization.
Fixes: SWDEV-218237
Lang Hames [Sun, 5 Feb 2023 03:36:40 +0000 (03:36 +0000)]
[ORC] Use JITLink as the default linker for LLJIT on Linux/arm64.
Also updates the OrcCAPIsTest unit test to enable the C API tests on Linux.
Owen Anderson [Wed, 4 Jan 2023 06:23:31 +0000 (23:23 -0700)]
Teach the AArch64 backend to materialize immediates using a pair of ORR-immediate
instructions.
Credit to czwarich for figuring out the algorithm to test for this.
Re-applied with fix for ubsan error on out-of-range shift.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D140952
Owen Anderson [Sun, 5 Feb 2023 04:13:31 +0000 (22:13 -0600)]
Revert "Teach the AArch64 backend to materialize immediates using a pair of ORR-immediate"
This reverts commit
8d433a0ae55ac25ba0a77d733e1ee5e23d1eb9f7 due to test failures on
CodeGen/AArch64/GlobalISel/store-merging.ll
Petr Hosek [Sun, 5 Feb 2023 02:43:54 +0000 (02:43 +0000)]
[CMake] Process components and install targets separately
This addresses issue introduced accidentally in D117263.
Owen Anderson [Wed, 4 Jan 2023 06:23:31 +0000 (23:23 -0700)]
Teach the AArch64 backend to materialize immediates using a pair of ORR-immediate
instructions.
Credit to czwarich for figuring out the algorithm to test for this.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D140952
Craig Topper [Sun, 5 Feb 2023 01:31:37 +0000 (17:31 -0800)]
[RISCV] Move all isel cases for ISD::ConstantFP into RISCVDAGToDAGISel::Select.
After D142953, non-zero cases were handled in RISCVDAGToDAGISel::Select
and zeros were handled with isel patterns. The zeros cases are
sufficiently similar to zero that we might as well handle them all
together. We already needed to detect the cases to skip out to
tablegen.