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yroux [Wed, 16 Jul 2014 16:15:26 +0000 (16:15 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210369.
2014-05-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (neon_itype): Remove NEON_RESULTPAIR.
(arm_init_neon_builtins): Remove handling of NEON_RESULTPAIR.
Remove associated type declarations and initialisations.
(arm_expand_neon_builtin): Likewise.
(neon_emit_pair_result_insn): Delete.
* config/arm/arm_neon_builtins (vtrn, vzip, vuzp): Delete.
* config/arm/neon.md (neon_vtrn<mode>): Delete.
(neon_vzip<mode>): Likewise.
(neon_vuzp<mode>): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212678
138bc75d-0d04-0410-961f-
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yroux [Wed, 16 Jul 2014 16:03:58 +0000 (16:03 +0000)]
gcc/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211058, 211177.
2014-05-29 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): New static data.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): New builtin.
* config/aarch64/aarch64-simd.md (aarch64_ext, aarch64_im_lane_boundsi):
New patterns.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm_const_1): Match
patterns for EXT.
(aarch64_evpc_ext): New function.
* config/aarch64/iterators.md (UNSPEC_EXT): New enum element.
* config/aarch64/arm_neon.h (vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64): Replace __asm with __builtin_shuffle and im_lane_boundsi.
2014-06-03 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64.c (aarch64_evpc_ext): allow and handle
location == 0.
gcc/testsuite/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210152, 211059.
2014-05-29 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/arm/simd/vextQf32_1.c: New file.
* gcc.target/arm/simd/vextQp16_1.c: New file.
* gcc.target/arm/simd/vextQp8_1.c: New file.
* gcc.target/arm/simd/vextQs16_1.c: New file.
* gcc.target/arm/simd/vextQs32_1.c: New file.
* gcc.target/arm/simd/vextQs64_1.c: New file.
* gcc.target/arm/simd/vextQs8_1.c: New file.
* gcc.target/arm/simd/vextQu16_1.c: New file.
* gcc.target/arm/simd/vextQu32_1.c: New file.
* gcc.target/arm/simd/vextQu64_1.c: New file.
* gcc.target/arm/simd/vextQu8_1.c: New file.
* gcc.target/arm/simd/vextQp64_1.c: New file.
* gcc.target/arm/simd/vextf32_1.c: New file.
* gcc.target/arm/simd/vextp16_1.c: New file.
* gcc.target/arm/simd/vextp8_1.c: New file.
* gcc.target/arm/simd/vexts16_1.c: New file.
* gcc.target/arm/simd/vexts32_1.c: New file.
* gcc.target/arm/simd/vexts64_1.c: New file.
* gcc.target/arm/simd/vexts8_1.c: New file.
* gcc.target/arm/simd/vextu16_1.c: New file.
* gcc.target/arm/simd/vextu32_1.c: New file.
* gcc.target/arm/simd/vextu64_1.c: New file.
* gcc.target/arm/simd/vextu8_1.c: New file.
* gcc.target/arm/simd/vextp64_1.c: New file.
2014-05-07 Alan Lawrence <alan.lawrence@arm.com>
gcc.target/aarch64/simd/ext_f32.x: New file.
gcc.target/aarch64/simd/ext_f32_1.c: New file.
gcc.target/aarch64/simd/ext_p16.x: New file.
gcc.target/aarch64/simd/ext_p16_1.c: New file.
gcc.target/aarch64/simd/ext_p8.x: New file.
gcc.target/aarch64/simd/ext_p8_1.c: New file.
gcc.target/aarch64/simd/ext_s16.x: New file.
gcc.target/aarch64/simd/ext_s16_1.c: New file.
gcc.target/aarch64/simd/ext_s32.x: New file.
gcc.target/aarch64/simd/ext_s32_1.c: New file.
gcc.target/aarch64/simd/ext_s64.x: New file.
gcc.target/aarch64/simd/ext_s64_1.c: New file.
gcc.target/aarch64/simd/ext_s8.x: New file.
gcc.target/aarch64/simd/ext_s8_1.c: New file.
gcc.target/aarch64/simd/ext_u16.x: New file.
gcc.target/aarch64/simd/ext_u16_1.c: New file.
gcc.target/aarch64/simd/ext_u32.x: New file.
gcc.target/aarch64/simd/ext_u32_1.c: New file.
gcc.target/aarch64/simd/ext_u64.x: New file.
gcc.target/aarch64/simd/ext_u64_1.c: New file.
gcc.target/aarch64/simd/ext_u8.x: New file.
gcc.target/aarch64/simd/ext_u8_1.c: New file.
gcc.target/aarch64/simd/ext_f64.c: New file.
gcc.target/aarch64/simd/extq_f32.x: New file.
gcc.target/aarch64/simd/extq_f32_1.c: New file.
gcc.target/aarch64/simd/extq_p16.x: New file.
gcc.target/aarch64/simd/extq_p16_1.c: New file.
gcc.target/aarch64/simd/extq_p8.x: New file.
gcc.target/aarch64/simd/extq_p8_1.c: New file.
gcc.target/aarch64/simd/extq_s16.x: New file.
gcc.target/aarch64/simd/extq_s16_1.c: New file.
gcc.target/aarch64/simd/extq_s32.x: New file.
gcc.target/aarch64/simd/extq_s32_1.c: New file.
gcc.target/aarch64/simd/extq_s64.x: New file.
gcc.target/aarch64/simd/extq_s64_1.c: New file.
gcc.target/aarch64/simd/extq_s8.x: New file.
gcc.target/aarch64/simd/extq_s8_1.c: New file.
gcc.target/aarch64/simd/extq_u16.x: New file.
gcc.target/aarch64/simd/extq_u16_1.c: New file.
gcc.target/aarch64/simd/extq_u32.x: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212677
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yroux [Wed, 16 Jul 2014 15:49:51 +0000 (15:49 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209797.
2014-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p):
Use HOST_WIDE_INT_C for mask literal.
(aarch_rev16_shleft_mask_imm_p): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212675
138bc75d-0d04-0410-961f-
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yroux [Wed, 16 Jul 2014 15:45:43 +0000 (15:45 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211148.
2014-06-02 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64-linux.h (GLIBC_DYNAMIC_LINKER):
/lib/ld-linux32-aarch64.so.1 is used for ILP32.
(LINUX_TARGET_LINK_SPEC): Update linker script for ILP32.
file whose name depends on -mabi= and -mbig-endian.
* config/aarch64/t-aarch64-linux (MULTILIB_OSDIRNAMES): Handle LP64
better and handle ilp32 too.
(MULTILIB_OPTIONS): Delete.
(MULTILIB_DIRNAMES): Delete.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212673
138bc75d-0d04-0410-961f-
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yroux [Wed, 16 Jul 2014 15:39:57 +0000 (15:39 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210828, r211103.
2014-05-31 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
(arm_builtins) : Add ARM_BUILTIN_GET_FPSCR and ARM_BUILTIN_SET_FPSCR.
(bdesc_2arg) : Add description for builtins __builtins_arm_set_fpscr
and __builtins_arm_get_fpscr.
(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
__builtins_arm_get_fpscr.
(arm_expand_builtin) : Expand builtins __builtins_arm_set_fpscr and
__builtins_arm_ldfpscr.
(arm_atomic_assign_expand_fenv): New function.
* config/arm/vfp.md (set_fpscr): New pattern.
(get_fpscr) : Likewise.
* config/arm/unspecs.md (unspecv): Add VUNSPEC_GET_FPSCR and
VUNSPEC_SET_FPSCR.
* doc/extend.texi (AARCH64 Built-in Functions) : Document
__builtins_arm_set_fpscr, __builtins_arm_get_fpscr.
2014-05-23 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/aarch64/aarch64.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New
define.
* config/aarch64/aarch64-protos.h (aarch64_atomic_assign_expand_fenv):
New function declaration.
* config/aarch64/aarch64-builtins.c (aarch64_builtins) : Add
AARCH64_BUILTIN_GET_FPCR, AARCH64_BUILTIN_SET_FPCR.
AARCH64_BUILTIN_GET_FPSR and AARCH64_BUILTIN_SET_FPSR.
(aarch64_init_builtins) : Initialize builtins
__builtins_aarch64_set_fpcr, __builtins_aarch64_get_fpcr.
__builtins_aarch64_set_fpsr and __builtins_aarch64_get_fpsr.
(aarch64_expand_builtin) : Expand builtins __builtins_aarch64_set_fpcr
__builtins_aarch64_get_fpcr, __builtins_aarch64_get_fpsr,
and __builtins_aarch64_set_fpsr.
(aarch64_atomic_assign_expand_fenv): New function.
* config/aarch64/aarch64.md (set_fpcr): New pattern.
(get_fpcr) : Likewise.
(set_fpsr) : Likewise.
(get_fpsr) : Likewise.
(unspecv): Add UNSPECV_GET_FPCR and UNSPECV_SET_FPCR, UNSPECV_GET_FPSR
and UNSPECV_SET_FPSR.
* doc/extend.texi (AARCH64 Built-in Functions) : Document
__builtins_aarch64_set_fpcr, __builtins_aarch64_get_fpcr.
__builtins_aarch64_set_fpsr and __builtins_aarch64_get_fpsr.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212672
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 15:24:13 +0000 (15:24 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210355.
2014-05-13 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64-protos.h
(aarch64_hard_regno_caller_save_mode): New prototype.
* config/aarch64/aarch64.c (aarch64_hard_regno_caller_save_mode):
New function.
* config/aarch64/aarch64.h (HARD_REGNO_CALLER_SAVE_MODE): New macro.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212669
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 15:04:27 +0000 (15:04 +0000)]
gcc/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209943.
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/arm_neon.h (vuzp1_f32, vuzp1_p8, vuzp1_p16, vuzp1_s8,
vuzp1_s16, vuzp1_s32, vuzp1_u8, vuzp1_u16, vuzp1_u32, vuzp1q_f32,
vuzp1q_f64, vuzp1q_p8, vuzp1q_p16, vuzp1q_s8, vuzp1q_s16, vuzp1q_s32,
vuzp1q_s64, vuzp1q_u8, vuzp1q_u16, vuzp1q_u32, vuzp1q_u64, vuzp2_f32,
vuzp2_p8, vuzp2_p16, vuzp2_s8, vuzp2_s16, vuzp2_s32, vuzp2_u8,
vuzp2_u16, vuzp2_u32, vuzp2q_f32, vuzp2q_f64, vuzp2q_p8, vuzp2q_p16,
vuzp2q_s8, vuzp2q_s16, vuzp2q_s32, vuzp2q_s64, vuzp2q_u8, vuzp2q_u16,
vuzp2q_u32, vuzp2q_u64): Replace temporary asm with __builtin_shuffle.
gcc/testsuite/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209940, `r209943, r209947.
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/arm/simd/vuzpqf32_1.c: New file.
* gcc.target/arm/simd/vuzpqp16_1.c: New file.
* gcc.target/arm/simd/vuzpqp8_1.c: New file.
* gcc.target/arm/simd/vuzpqs16_1.c: New file.
* gcc.target/arm/simd/vuzpqs32_1.c: New file.
* gcc.target/arm/simd/vuzpqs8_1.c: New file.
* gcc.target/arm/simd/vuzpqu16_1.c: New file.
* gcc.target/arm/simd/vuzpqu32_1.c: New file.
* gcc.target/arm/simd/vuzpqu8_1.c: New file.
* gcc.target/arm/simd/vuzpf32_1.c: New file.
* gcc.target/arm/simd/vuzpp16_1.c: New file.
* gcc.target/arm/simd/vuzpp8_1.c: New file.
* gcc.target/arm/simd/vuzps16_1.c: New file.
* gcc.target/arm/simd/vuzps32_1.c: New file.
* gcc.target/arm/simd/vuzps8_1.c: New file.
* gcc.target/arm/simd/vuzpu16_1.c: New file.
* gcc.target/arm/simd/vuzpu32_1.c: New file.
* gcc.target/arm/simd/vuzpu8_1.c: New file.
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/vuzps32_1.c: Expect zip1/2 insn rather than uzp1/2.
* gcc.target/aarch64/vuzpu32_1.c: Likewise.
* gcc.target/aarch64/vuzpf32_1.c: Likewise.
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/simd/vuzpf32_1.c: New file.
* gcc.target/aarch64/simd/vuzpf32.x: New file.
* gcc.target/aarch64/simd/vuzpp16_1.c: New file.
* gcc.target/aarch64/simd/vuzpp16.x: New file.
* gcc.target/aarch64/simd/vuzpp8_1.c: New file.
* gcc.target/aarch64/simd/vuzpp8.x: New file.
* gcc.target/aarch64/simd/vuzpqf32_1.c: New file.
* gcc.target/aarch64/simd/vuzpqf32.x: New file.
* gcc.target/aarch64/simd/vuzpqp16_1.c: New file.
* gcc.target/aarch64/simd/vuzpqp16.x: New file.
* gcc.target/aarch64/simd/vuzpqp8_1.c: New file.
* gcc.target/aarch64/simd/vuzpqp8.x: New file.
* gcc.target/aarch64/simd/vuzpqs16_1.c: New file.
* gcc.target/aarch64/simd/vuzpqs16.x: New file.
* gcc.target/aarch64/simd/vuzpqs32_1.c: New file.
* gcc.target/aarch64/simd/vuzpqs32.x: New file.
* gcc.target/aarch64/simd/vuzpqs8_1.c: New file.
* gcc.target/aarch64/simd/vuzpqs8.x: New file.
* gcc.target/aarch64/simd/vuzpqu16_1.c: New file.
* gcc.target/aarch64/simd/vuzpqu16.x: New file.
* gcc.target/aarch64/simd/vuzpqu32_1.c: New file.
* gcc.target/aarch64/simd/vuzpqu32.x: New file.
* gcc.target/aarch64/simd/vuzpqu8_1.c: New file.
* gcc.target/aarch64/simd/vuzpqu8.x: New file.
* gcc.target/aarch64/simd/vuzps16_1.c: New file.
* gcc.target/aarch64/simd/vuzps16.x: New file.
* gcc.target/aarch64/simd/vuzps32_1.c: New file.
* gcc.target/aarch64/simd/vuzps32.x: New file.
* gcc.target/aarch64/simd/vuzps8_1.c: New file.
* gcc.target/aarch64/simd/vuzps8.x: New file.
* gcc.target/aarch64/simd/vuzpu16_1.c: New file.
* gcc.target/aarch64/simd/vuzpu16.x: New file.
* gcc.target/aarch64/simd/vuzpu32_1.c: New file.
* gcc.target/aarch64/simd/vuzpu32.x: New file.
* gcc.target/aarch64/simd/vuzpu8_1.c: New file.
* gcc.target/aarch64/simd/vuzpu8.x: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212665
138bc75d-0d04-0410-961f-
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yroux [Wed, 16 Jul 2014 14:43:37 +0000 (14:43 +0000)]
Merge branches/gcc-4_9-branch rev 212419
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212661
138bc75d-0d04-0410-961f-
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yroux [Thu, 26 Jun 2014 07:44:46 +0000 (07:44 +0000)]
Bump version number, post release.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212012
138bc75d-0d04-0410-961f-
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yroux [Thu, 26 Jun 2014 07:39:54 +0000 (07:39 +0000)]
Make Linaro GCC 4.9-2014.06-1.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212009
138bc75d-0d04-0410-961f-
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yroux [Wed, 25 Jun 2014 13:10:09 +0000 (13:10 +0000)]
Merge branches/gcc-4_9-branch rev 211964
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211979
138bc75d-0d04-0410-961f-
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yroux [Tue, 24 Jun 2014 14:14:35 +0000 (14:14 +0000)]
2014-06-24 Yvan Roux <yvan.roux@linaro.org>
Revert:
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209643.
2014-04-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/aarch64/aarch64.c (TARGET_FLAGS_REGNUM): Define.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211940
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 20 Jun 2014 08:59:14 +0000 (08:59 +0000)]
2014-06-13 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210493, 210494, 210495, 210496, 210497, 210498,
210499, 210500, 210501, 210502, 210503, 210504, 210505, 210506, 210507,
210508, 210509, 210510, 210512, 211205, 211206.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-protos.h (scale_addr_mode_cost): New.
(cpu_addrcost_table): Use it.
* config/aarch64/aarch64.c (generic_addrcost_table): Initialize it.
(aarch64_address_cost): Rewrite using aarch64_classify_address,
move it.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (cortexa57_addrcost_table): New.
(cortexa57_vector_cost): Likewise.
(cortexa57_tunings): Use them.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs_wrapper): New.
(TARGET_RTX_COSTS): Call it.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_build_constant): Conditionally
emit instructions, return number of instructions which would
be emitted.
(aarch64_add_constant): Update call to aarch64_build_constant.
(aarch64_output_mi_thunk): Likewise.
(aarch64_rtx_costs): Estimate cost of a CONST_INT, cost
a CONST_DOUBLE.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_strip_shift_or_extend): Rename
to...
(aarch64_strip_extend): ...this, don't strip shifts, check RTX is
well formed.
(aarch64_rtx_mult_cost): New.
(aarch64_rtx_costs): Use it, refactor as appropriate.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Set default costs.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philip Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costing
for SET RTX.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Use address
costs when costing loads and stores to memory.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve cost for
logical operations.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost
ZERO_EXTEND and SIGN_EXTEND better.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
rotates and shifts.
2014-03-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_arith_op_extract_p): New.
(aarch64_rtx_costs): Improve costs for SIGN/ZERO_EXTRACT.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
DIV/MOD.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost comparison
operators.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost FMA,
FLOAT_EXTEND, FLOAT_TRUNCATE, ABS, SMAX, and SMIN.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost TRUNCATE.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost SYMBOL_REF,
HIGH, LO_SUM.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle the case
where we were unable to cost an RTX.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_mult_cost): Fix FNMUL case.
2014-06-03 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.c (aarch64_if_then_else_costs): New function.
(aarch64_rtx_costs): Use aarch64_if_then_else_costs.
2014-06-03 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Allow non
comparisons for OP0.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211843
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 13 Jun 2014 08:01:29 +0000 (08:01 +0000)]
Bump version number, post release.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211609
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 13 Jun 2014 07:57:25 +0000 (07:57 +0000)]
Make Linaro GCC 4.9-2014.06.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211607
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:55:11 +0000 (12:55 +0000)]
2014-06-04 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211211.
2014-06-04 Bin Cheng <bin.cheng@arm.com>
* config/aarch64/aarch64.c (aarch64_classify_address)
(aarch64_legitimize_reload_address): Support full addressing modes
for vector modes.
* config/aarch64/aarch64.md (mov<mode>, movmisalign<mode>)
(*aarch64_simd_mov<mode>, *aarch64_simd_mov<mode>): Relax predicates.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211584
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:52:45 +0000 (12:52 +0000)]
2014-05-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210615.
2014-05-19 Richard Henderson <rth@redhat.com>
* config/aarch64/sjlj.S: New file.
* config/aarch64/target.h: New file.
* configure.tgt: Enable aarch64.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211583
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:48:58 +0000 (12:48 +0000)]
gcc/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209906.
2014-04-29 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/arm_neon.h (vzip1_f32, vzip1_p8, vzip1_p16, vzip1_s8,
vzip1_s16, vzip1_s32, vzip1_u8, vzip1_u16, vzip1_u32, vzip1q_f32,
vzip1q_f64, vzip1q_p8, vzip1q_p16, vzip1q_s8, vzip1q_s16, vzip1q_s32,
vzip1q_s64, vzip1q_u8, vzip1q_u16, vzip1q_u32, vzip1q_u64, vzip2_f32,
vzip2_p8, vzip2_p16, vzip2_s8, vzip2_s16, vzip2_s32, vzip2_u8,
vzip2_u16, vzip2_u32, vzip2q_f32, vzip2q_f64, vzip2q_p8, vzip2q_p16,
vzip2q_s8, vzip2q_s16, vzip2q_s32, vzip2q_s64, vzip2q_u8, vzip2q_u16,
vzip2q_u32, vzip2q_u64): Replace inline __asm__ with __builtin_shuffle.
gcc/testsuite/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209908.
2013-04-29 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/arm/simd/simd.exp: New file.
* gcc.target/arm/simd/vzipqf32_1.c: New file.
* gcc.target/arm/simd/vzipqp16_1.c: New file.
* gcc.target/arm/simd/vzipqp8_1.c: New file.
* gcc.target/arm/simd/vzipqs16_1.c: New file.
* gcc.target/arm/simd/vzipqs32_1.c: New file.
* gcc.target/arm/simd/vzipqs8_1.c: New file.
* gcc.target/arm/simd/vzipqu16_1.c: New file.
* gcc.target/arm/simd/vzipqu32_1.c: New file.
* gcc.target/arm/simd/vzipqu8_1.c: New file.
* gcc.target/arm/simd/vzipf32_1.c: New file.
* gcc.target/arm/simd/vzipp16_1.c: New file.
* gcc.target/arm/simd/vzipp8_1.c: New file.
* gcc.target/arm/simd/vzips16_1.c: New file.
* gcc.target/arm/simd/vzips32_1.c: New file.
* gcc.target/arm/simd/vzips8_1.c: New file.
* gcc.target/arm/simd/vzipu16_1.c: New file.
* gcc.target/arm/simd/vzipu32_1.c: New file.
* gcc.target/arm/simd/vzipu8_1.c: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211582
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:44:00 +0000 (12:44 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209897.
2014-04-29 James Greenhalgh <james.greenhalgh@arm.com>
* calls.c (initialize_argument_information): Always treat
PUSH_ARGS_REVERSED as 1, simplify code accordingly.
(expand_call): Likewise.
(emit_library_call_calue_1): Likewise.
* expr.c (PUSH_ARGS_REVERSED): Do not define.
(emit_push_insn): Always treat PUSH_ARGS_REVERSED as 1, simplify
code accordingly.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211581
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:40:56 +0000 (12:40 +0000)]
gcc/testsuite/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209893.
2014-04-29 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/simd/simd.exp: New file.
* gcc.target/aarch64/simd/vzipf32_1.c: New file.
* gcc.target/aarch64/simd/vzipf32.x: New file.
* gcc.target/aarch64/simd/vzipp16_1.c: New file.
* gcc.target/aarch64/simd/vzipp16.x: New file.
* gcc.target/aarch64/simd/vzipp8_1.c: New file.
* gcc.target/aarch64/simd/vzipp8.x: New file.
* gcc.target/aarch64/simd/vzipqf32_1.c: New file.
* gcc.target/aarch64/simd/vzipqf32.x: New file.
* gcc.target/aarch64/simd/vzipqp16_1.c: New file.
* gcc.target/aarch64/simd/vzipqp16.x: New file.
* gcc.target/aarch64/simd/vzipqp8_1.c: New file.
* gcc.target/aarch64/simd/vzipqp8.x: New file.
* gcc.target/aarch64/simd/vzipqs16_1.c: New file.
* gcc.target/aarch64/simd/vzipqs16.x: New file.
* gcc.target/aarch64/simd/vzipqs32_1.c: New file.
* gcc.target/aarch64/simd/vzipqs32.x: New file.
* gcc.target/aarch64/simd/vzipqs8_1.c: New file.
* gcc.target/aarch64/simd/vzipqs8.x: New file.
* gcc.target/aarch64/simd/vzipqu16_1.c: New file.
* gcc.target/aarch64/simd/vzipqu16.x: New file.
* gcc.target/aarch64/simd/vzipqu32_1.c: New file.
* gcc.target/aarch64/simd/vzipqu32.x: New file.
* gcc.target/aarch64/simd/vzipqu8_1.c: New file.
* gcc.target/aarch64/simd/vzipqu8.x: New file.
* gcc.target/aarch64/simd/vzips16_1.c: New file.
* gcc.target/aarch64/simd/vzips16.x: New file.
* gcc.target/aarch64/simd/vzips32_1.c: New file.
* gcc.target/aarch64/simd/vzips32.x: New file.
* gcc.target/aarch64/simd/vzips8_1.c: New file.
* gcc.target/aarch64/simd/vzips8.x: New file.
* gcc.target/aarch64/simd/vzipu16_1.c: New file.
* gcc.target/aarch64/simd/vzipu16.x: New file.
* gcc.target/aarch64/simd/vzipu32_1.c: New file.
* gcc.target/aarch64/simd/vzipu32.x: New file.
* gcc.target/aarch64/simd/vzipu8_1.c: New file.
* gcc.target/aarch64/simd/vzipu8.x: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211580
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:36:45 +0000 (12:36 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209880.
2014-04-28 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_types_storestruct_lane_qualifiers): New.
(TYPES_STORESTRUCT_LANE): Likewise.
* config/aarch64/aarch64-simd-builtins.def (st2_lane): New.
(st3_lane): Likewise.
(st4_lane): Likewise.
* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): New.
(vec_store_lanesci_lane<mode>): Likewise.
(vec_store_lanesxi_lane<mode>): Likewise.
(aarch64_st2_lane<VQ:mode>): Likewise.
(aarch64_st3_lane<VQ:mode>): Likewise.
(aarch64_st4_lane<VQ:mode>): Likewise.
* config/aarch64/aarch64.md (unspec): Add UNSPEC_ST{2,3,4}_LANE.
* config/aarch64/arm_neon.h
(__ST2_LANE_FUNC): Rewrite using builtins, update use points to
use new macro arguments.
(__ST3_LANE_FUNC): Likewise.
(__ST4_LANE_FUNC): Likewise.
* config/aarch64/iterators.md (V_TWO_ELEM): New.
(V_THREE_ELEM): Likewise.
(V_FOUR_ELEM): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211579
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:33:49 +0000 (12:33 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209878.
2014-04-28 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_modes_tieable_p): New.
* config/aarch64/aarch64.c
(aarch64_cannot_change_mode_class): Weaken conditions.
(aarch64_modes_tieable_p): New.
* config/aarch64/aarch64.h (MODES_TIEABLE_P): Use it.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211578
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:31:13 +0000 (12:31 +0000)]
gcc/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209808.
2014-04-25 Jiong Wang <jiong.wang@arm.com>
* config/arm/predicates.md (call_insn_operand): Add long_call check.
* config/arm/arm.md (sibcall, sibcall_value): Force the address to
reg for long_call.
* config/arm/arm.c (arm_function_ok_for_sibcall): Remove long_call
restriction.
gcc/testsuite/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209808.
2014-04-25 Jiong Wang <jiong.wang@arm.com>
* gcc.target/arm/tail-long-call.c: New test.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211577
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:27:08 +0000 (12:27 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209806.
2014-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (arm_cortex_a8_tune): Initialise
T16-related fields.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211576
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:21:40 +0000 (12:21 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209747.
2014-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* configure.ac: Quote usage of ac_cv_func_clock_gettime in if test.
* configure: Regenerate.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211575
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:17:03 +0000 (12:17 +0000)]
gcc/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209742, 209749.
2014-04-24 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64.c (aarch64_evpc_tbl): Enable for bigendian.
2014-04-24 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64.c (aarch64_evpc_tbl): Reverse order of elements
for big-endian.
gcc/testsuite/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209749.
2014-04-24 Alan Lawrence <alan.lawrence@arm.com>
* lib/target-supports.exp (check_effective_target_vect_perm): Return
true for aarch64_be.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211574
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:12:37 +0000 (12:12 +0000)]
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209736.
2014-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Handle BUILT_IN_BSWAP16,
BUILT_IN_BSWAP32, BUILT_IN_BSWAP64.
* config/aarch64/aarch64-simd.md (bswap<mode>): New pattern.
* config/aarch64/aarch64-simd-builtins.def: Define vector bswap
builtins.
* config/aarch64/iterator.md (VDQHSD): New mode iterator.
(Vrevsuff): New mode attribute.
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209736.
2014-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* lib/target-supports.exp (check_effective_target_vect_bswap): New.
* gcc.dg/vect/vect-bswap16: New test.
* gcc.dg/vect/vect-bswap32: Likewise.
* gcc.dg/vect/vect-bswap64: Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211573
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:07:45 +0000 (12:07 +0000)]
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209713.
2014-04-23 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vdup_lane_1.c: New testcase.
* gcc.target/aarch64/vdup_lane_2.c: New testcase.
* gcc.target/aarch64/vdup_n_1.c: New testcase.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211560
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:05:13 +0000 (12:05 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209712.
2014-04-23 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
* config/aarch64/aarch64.md (stack_protect_set, stack_protect_test)
(stack_protect_set_<mode>, stack_protect_test_<mode>): Add
machine descriptions for Stack Smashing Protector.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211530
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:02:58 +0000 (12:02 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209711.
2014-04-23 Richard Earnshaw <rearnsha@arm.com>
* aarch64.md (<optab>_rol<mode>3): New pattern.
(<optab>_rolsi3_uxtw): Likewise.
* aarch64.c (aarch64_strip_shift): Handle ROTATE and ROTATERT.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211524
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:59:51 +0000 (11:59 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209710.
2014-04-23 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/arm.c (arm_cortex_a57_tune): Initialize all fields.
(arm_cortex_a12_tune): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211523
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:57:21 +0000 (11:57 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209706.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle BSWAP.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211521
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:54:42 +0000 (11:54 +0000)]
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209701, 209702, 209703, 209704, 209705.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (arm_rev16si2): New pattern.
(arm_rev16si2_alt): Likewise.
* config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md (rev16<mode>2): New pattern.
(rev16<mode>2_alt): Likewise.
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle rev16 case.
* config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p): New.
(aarch_rev16_shleft_mask_imm_p): Likewise.
(aarch_rev16_p_1): Likewise.
(aarch_rev16_p): Likewise.
* config/arm/aarch-common-protos.h (aarch_rev16_p): Declare extern.
(aarch_rev16_shright_mask_imm_p): Likewise.
(aarch_rev16_shleft_mask_imm_p): Likewise.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/aarch-common-protos.h (alu_cost_table): Add rev field.
* config/arm/aarch-cost-tables.h (generic_extra_costs): Specify
rev cost.
(cortex_a53_extra_costs): Likewise.
(cortex_a57_extra_costs): Likewise.
* config/arm/arm.c (cortexa9_extra_costs): Likewise.
(cortexa7_extra_costs): Likewise.
(cortexa8_extra_costs): Likewise.
(cortexa12_extra_costs): Likewise.
(cortexa15_extra_costs): Likewise.
(v7m_extra_costs): Likewise.
(arm_new_rtx_costs): Handle BSWAP.
2013-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (cortexa8_extra_costs): New table.
(arm_cortex_a8_tune): New tuning struct.
* config/arm/arm-cores.def (cortex-a8): Use cortex_a8 tuning struct.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (arm_new_rtx_costs): Handle FMA.
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209704, 209705.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/arm/rev16.c: New test.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/rev16_1.c: New test.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211520
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:48:36 +0000 (11:48 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209659.
2014-04-22 Richard Henderson <rth@redhat.com>
* config/aarch64/aarch64 (addti3, subti3): New expanders.
(add<GPI>3_compare0): Remove leading * from name.
(add<GPI>3_carryin): Likewise.
(sub<GPI>3_compare0): Likewise.
(sub<GPI>3_carryin): Likewise.
(<su_optab>mulditi3): New expander.
(multi3): New expander.
(madd<GPI>): Remove leading * from name.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211519
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:45:47 +0000 (11:45 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209649.
2014-04-22 Yufeng Zhang <yufeng.zhang@arm.com>
* longlong.h: Merge from glibc.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211518
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:43:21 +0000 (11:43 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209645.
2014-04-22 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
Handle TLS for ILP32.
* config/aarch64/aarch64.md (tlsie_small): Rename to ...
(tlsie_small_<mode>): this and handle PTR.
(tlsie_small_sidi): New pattern.
(tlsle_small): Change to an expand to handle ILP32.
(tlsle_small_<mode>): New pattern.
(tlsdesc_small): Rename to ...
(tlsdesc_small_<mode>): this and handle PTR.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211517
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:40:26 +0000 (11:40 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209643.
2014-04-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/aarch64/aarch64.c (TARGET_FLAGS_REGNUM): Define.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211516
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:36:54 +0000 (11:36 +0000)]
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209641, 209642.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* config/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
(aarch64_types_signed_unsigned_qualifiers): Qualifier added.
(aarch64_types_signed_poly_qualifiers): Likewise.
(aarch64_types_unsigned_signed_qualifiers): Likewise.
(aarch64_types_poly_signed_qualifiers): Likewise.
(TYPES_REINTERP_SS): Type macro added.
(TYPES_REINTERP_SU): Likewise.
(TYPES_REINTERP_SP): Likewise.
(TYPES_REINTERP_US): Likewise.
(TYPES_REINTERP_PS): Likewise.
(aarch64_fold_builtin): New expression folding added.
* config/aarch64/aarch64-simd-builtins.def (REINTERP):
Declarations removed.
(REINTERP_SS): Declarations added.
(REINTERP_US): Likewise.
(REINTERP_PS): Likewise.
(REINTERP_SU): Likewise.
(REINTERP_SP): Likewise.
* config/aarch64/arm_neon.h (vreinterpret_p8_f64): Implemented.
(vreinterpretq_p8_f64): Likewise.
(vreinterpret_p16_f64): Likewise.
(vreinterpretq_p16_f64): Likewise.
(vreinterpret_f32_f64): Likewise.
(vreinterpretq_f32_f64): Likewise.
(vreinterpret_f64_f32): Likewise.
(vreinterpret_f64_p8): Likewise.
(vreinterpret_f64_p16): Likewise.
(vreinterpret_f64_s8): Likewise.
(vreinterpret_f64_s16): Likewise.
(vreinterpret_f64_s32): Likewise.
(vreinterpret_f64_s64): Likewise.
(vreinterpret_f64_u8): Likewise.
(vreinterpret_f64_u16): Likewise.
(vreinterpret_f64_u32): Likewise.
(vreinterpret_f64_u64): Likewise.
(vreinterpretq_f64_f32): Likewise.
(vreinterpretq_f64_p8): Likewise.
(vreinterpretq_f64_p16): Likewise.
(vreinterpretq_f64_s8): Likewise.
(vreinterpretq_f64_s16): Likewise.
(vreinterpretq_f64_s32): Likewise.
(vreinterpretq_f64_s64): Likewise.
(vreinterpretq_f64_u8): Likewise.
(vreinterpretq_f64_u16): Likewise.
(vreinterpretq_f64_u32): Likewise.
(vreinterpretq_f64_u64): Likewise.
(vreinterpret_s64_f64): Likewise.
(vreinterpretq_s64_f64): Likewise.
(vreinterpret_u64_f64): Likewise.
(vreinterpretq_u64_f64): Likewise.
(vreinterpret_s8_f64): Likewise.
(vreinterpretq_s8_f64): Likewise.
(vreinterpret_s16_f64): Likewise.
(vreinterpretq_s16_f64): Likewise.
(vreinterpret_s32_f64): Likewise.
(vreinterpretq_s32_f64): Likewise.
(vreinterpret_u8_f64): Likewise.
(vreinterpretq_u8_f64): Likewise.
(vreinterpret_u16_f64): Likewise.
(vreinterpretq_u16_f64): Likewise.
(vreinterpret_u32_f64): Likewise.
(vreinterpretq_u32_f64): Likewise.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* config/aarch64/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
* config/aarch64/aarch64/aarch64-simd-builtins.def (REINTERP): Removed.
(vreinterpret_p8_s8): Likewise.
* config/aarch64/aarch64/arm_neon.h (vreinterpret_p8_s8): Uses cast.
(vreinterpret_p8_s16): Likewise.
(vreinterpret_p8_s32): Likewise.
(vreinterpret_p8_s64): Likewise.
(vreinterpret_p8_f32): Likewise.
(vreinterpret_p8_u8): Likewise.
(vreinterpret_p8_u16): Likewise.
(vreinterpret_p8_u32): Likewise.
(vreinterpret_p8_u64): Likewise.
(vreinterpret_p8_p16): Likewise.
(vreinterpretq_p8_s8): Likewise.
(vreinterpretq_p8_s16): Likewise.
(vreinterpretq_p8_s32): Likewise.
(vreinterpretq_p8_s64): Likewise.
(vreinterpretq_p8_f32): Likewise.
(vreinterpretq_p8_u8): Likewise.
(vreinterpretq_p8_u16): Likewise.
(vreinterpretq_p8_u32): Likewise.
(vreinterpretq_p8_u64): Likewise.
(vreinterpretq_p8_p16): Likewise.
(vreinterpret_p16_s8): Likewise.
(vreinterpret_p16_s16): Likewise.
(vreinterpret_p16_s32): Likewise.
(vreinterpret_p16_s64): Likewise.
(vreinterpret_p16_f32): Likewise.
(vreinterpret_p16_u8): Likewise.
(vreinterpret_p16_u16): Likewise.
(vreinterpret_p16_u32): Likewise.
(vreinterpret_p16_u64): Likewise.
(vreinterpret_p16_p8): Likewise.
(vreinterpretq_p16_s8): Likewise.
(vreinterpretq_p16_s16): Likewise.
(vreinterpretq_p16_s32): Likewise.
(vreinterpretq_p16_s64): Likewise.
(vreinterpretq_p16_f32): Likewise.
(vreinterpretq_p16_u8): Likewise.
(vreinterpretq_p16_u16): Likewise.
(vreinterpretq_p16_u32): Likewise.
(vreinterpretq_p16_u64): Likewise.
(vreinterpretq_p16_p8): Likewise.
(vreinterpret_f32_s8): Likewise.
(vreinterpret_f32_s16): Likewise.
(vreinterpret_f32_s32): Likewise.
(vreinterpret_f32_s64): Likewise.
(vreinterpret_f32_u8): Likewise.
(vreinterpret_f32_u16): Likewise.
(vreinterpret_f32_u32): Likewise.
(vreinterpret_f32_u64): Likewise.
(vreinterpret_f32_p8): Likewise.
(vreinterpret_f32_p16): Likewise.
(vreinterpretq_f32_s8): Likewise.
(vreinterpretq_f32_s16): Likewise.
(vreinterpretq_f32_s32): Likewise.
(vreinterpretq_f32_s64): Likewise.
(vreinterpretq_f32_u8): Likewise.
(vreinterpretq_f32_u16): Likewise.
(vreinterpretq_f32_u32): Likewise.
(vreinterpretq_f32_u64): Likewise.
(vreinterpretq_f32_p8): Likewise.
(vreinterpretq_f32_p16): Likewise.
(vreinterpret_s64_s8): Likewise.
(vreinterpret_s64_s16): Likewise.
(vreinterpret_s64_s32): Likewise.
(vreinterpret_s64_f32): Likewise.
(vreinterpret_s64_u8): Likewise.
(vreinterpret_s64_u16): Likewise.
(vreinterpret_s64_u32): Likewise.
(vreinterpret_s64_u64): Likewise.
(vreinterpret_s64_p8): Likewise.
(vreinterpret_s64_p16): Likewise.
(vreinterpretq_s64_s8): Likewise.
(vreinterpretq_s64_s16): Likewise.
(vreinterpretq_s64_s32): Likewise.
(vreinterpretq_s64_f32): Likewise.
(vreinterpretq_s64_u8): Likewise.
(vreinterpretq_s64_u16): Likewise.
(vreinterpretq_s64_u32): Likewise.
(vreinterpretq_s64_u64): Likewise.
(vreinterpretq_s64_p8): Likewise.
(vreinterpretq_s64_p16): Likewise.
(vreinterpret_u64_s8): Likewise.
(vreinterpret_u64_s16): Likewise.
(vreinterpret_u64_s32): Likewise.
(vreinterpret_u64_s64): Likewise.
(vreinterpret_u64_f32): Likewise.
(vreinterpret_u64_u8): Likewise.
(vreinterpret_u64_u16): Likewise.
(vreinterpret_u64_u32): Likewise.
(vreinterpret_u64_p8): Likewise.
(vreinterpret_u64_p16): Likewise.
(vreinterpretq_u64_s8): Likewise.
(vreinterpretq_u64_s16): Likewise.
(vreinterpretq_u64_s32): Likewise.
(vreinterpretq_u64_s64): Likewise.
(vreinterpretq_u64_f32): Likewise.
(vreinterpretq_u64_u8): Likewise.
(vreinterpretq_u64_u16): Likewise.
(vreinterpretq_u64_u32): Likewise.
(vreinterpretq_u64_p8): Likewise.
(vreinterpretq_u64_p16): Likewise.
(vreinterpret_s8_s16): Likewise.
(vreinterpret_s8_s32): Likewise.
(vreinterpret_s8_s64): Likewise.
(vreinterpret_s8_f32): Likewise.
(vreinterpret_s8_u8): Likewise.
(vreinterpret_s8_u16): Likewise.
(vreinterpret_s8_u32): Likewise.
(vreinterpret_s8_u64): Likewise.
(vreinterpret_s8_p8): Likewise.
(vreinterpret_s8_p16): Likewise.
(vreinterpretq_s8_s16): Likewise.
(vreinterpretq_s8_s32): Likewise.
(vreinterpretq_s8_s64): Likewise.
(vreinterpretq_s8_f32): Likewise.
(vreinterpretq_s8_u8): Likewise.
(vreinterpretq_s8_u16): Likewise.
(vreinterpretq_s8_u32): Likewise.
(vreinterpretq_s8_u64): Likewise.
(vreinterpretq_s8_p8): Likewise.
(vreinterpretq_s8_p16): Likewise.
(vreinterpret_s16_s8): Likewise.
(vreinterpret_s16_s32): Likewise.
(vreinterpret_s16_s64): Likewise.
(vreinterpret_s16_f32): Likewise.
(vreinterpret_s16_u8): Likewise.
(vreinterpret_s16_u16): Likewise.
(vreinterpret_s16_u32): Likewise.
(vreinterpret_s16_u64): Likewise.
(vreinterpret_s16_p8): Likewise.
(vreinterpret_s16_p16): Likewise.
(vreinterpretq_s16_s8): Likewise.
(vreinterpretq_s16_s32): Likewise.
(vreinterpretq_s16_s64): Likewise.
(vreinterpretq_s16_f32): Likewise.
(vreinterpretq_s16_u8): Likewise.
(vreinterpretq_s16_u16): Likewise.
(vreinterpretq_s16_u32): Likewise.
(vreinterpretq_s16_u64): Likewise.
(vreinterpretq_s16_p8): Likewise.
(vreinterpretq_s16_p16): Likewise.
(vreinterpret_s32_s8): Likewise.
(vreinterpret_s32_s16): Likewise.
(vreinterpret_s32_s64): Likewise.
(vreinterpret_s32_f32): Likewise.
(vreinterpret_s32_u8): Likewise.
(vreinterpret_s32_u16): Likewise.
(vreinterpret_s32_u32): Likewise.
(vreinterpret_s32_u64): Likewise.
(vreinterpret_s32_p8): Likewise.
(vreinterpret_s32_p16): Likewise.
(vreinterpretq_s32_s8): Likewise.
(vreinterpretq_s32_s16): Likewise.
(vreinterpretq_s32_s64): Likewise.
(vreinterpretq_s32_f32): Likewise.
(vreinterpretq_s32_u8): Likewise.
(vreinterpretq_s32_u16): Likewise.
(vreinterpretq_s32_u32): Likewise.
(vreinterpretq_s32_u64): Likewise.
(vreinterpretq_s32_p8): Likewise.
(vreinterpretq_s32_p16): Likewise.
(vreinterpret_u8_s8): Likewise.
(vreinterpret_u8_s16): Likewise.
(vreinterpret_u8_s32): Likewise.
(vreinterpret_u8_s64): Likewise.
(vreinterpret_u8_f32): Likewise.
(vreinterpret_u8_u16): Likewise.
(vreinterpret_u8_u32): Likewise.
(vreinterpret_u8_u64): Likewise.
(vreinterpret_u8_p8): Likewise.
(vreinterpret_u8_p16): Likewise.
(vreinterpretq_u8_s8): Likewise.
(vreinterpretq_u8_s16): Likewise.
(vreinterpretq_u8_s32): Likewise.
(vreinterpretq_u8_s64): Likewise.
(vreinterpretq_u8_f32): Likewise.
(vreinterpretq_u8_u16): Likewise.
(vreinterpretq_u8_u32): Likewise.
(vreinterpretq_u8_u64): Likewise.
(vreinterpretq_u8_p8): Likewise.
(vreinterpretq_u8_p16): Likewise.
(vreinterpret_u16_s8): Likewise.
(vreinterpret_u16_s16): Likewise.
(vreinterpret_u16_s32): Likewise.
(vreinterpret_u16_s64): Likewise.
(vreinterpret_u16_f32): Likewise.
(vreinterpret_u16_u8): Likewise.
(vreinterpret_u16_u32): Likewise.
(vreinterpret_u16_u64): Likewise.
(vreinterpret_u16_p8): Likewise.
(vreinterpret_u16_p16): Likewise.
(vreinterpretq_u16_s8): Likewise.
(vreinterpretq_u16_s16): Likewise.
(vreinterpretq_u16_s32): Likewise.
(vreinterpretq_u16_s64): Likewise.
(vreinterpretq_u16_f32): Likewise.
(vreinterpretq_u16_u8): Likewise.
(vreinterpretq_u16_u32): Likewise.
(vreinterpretq_u16_u64): Likewise.
(vreinterpretq_u16_p8): Likewise.
(vreinterpretq_u16_p16): Likewise.
(vreinterpret_u32_s8): Likewise.
(vreinterpret_u32_s16): Likewise.
(vreinterpret_u32_s32): Likewise.
(vreinterpret_u32_s64): Likewise.
(vreinterpret_u32_f32): Likewise.
(vreinterpret_u32_u8): Likewise.
(vreinterpret_u32_u16): Likewise.
(vreinterpret_u32_u64): Likewise.
(vreinterpret_u32_p8): Likewise.
(vreinterpret_u32_p16): Likewise.
(vreinterpretq_u32_s8): Likewise.
(vreinterpretq_u32_s16): Likewise.
(vreinterpretq_u32_s32): Likewise.
(vreinterpretq_u32_s64): Likewise.
(vreinterpretq_u32_f32): Likewise.
(vreinterpretq_u32_u8): Likewise.
(vreinterpretq_u32_u16): Likewise.
(vreinterpretq_u32_u64): Likewise.
(vreinterpretq_u32_p8): Likewise.
(vreinterpretq_u32_p16): Likewise.
gcc/testsuite
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209642.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vreinterpret_f64_1.c: New.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211515
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:09:50 +0000 (11:09 +0000)]
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209640.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc/config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>):
Pattern extended.
* config/aarch64/aarch64-simd-builtins.def (sqneg): Iterator
extended.
(sqabs): Likewise.
* config/aarch64/arm_neon.h (vqneg_s64): New intrinsic.
(vqnegd_s64): Likewise.
(vqabs_s64): Likewise.
(vqabsd_s64): Likewise.
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209640.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vqneg_s64_1.c: New testcase.
* gcc.target/aarch64/vqabs_s64_1.c: New testcase.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211514
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:05:18 +0000 (11:05 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209627, 209636.
2014-04-22 Renlin <renlin.li@arm.com>
Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.h (aarch64_frame): Delete "fp_lr_offset".
* config/aarch64/aarch64.c (aarch64_layout_frame)
(aarch64_initial_elimination_offset): Likewise.
2014-04-22 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.c (aarch64_initial_elimination_offset):
Fix indentation.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211512
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:00:42 +0000 (11:00 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209618.
2014-04-22 Renlin Li <Renlin.Li@arm.com>
* config/aarch64/aarch64.c (aarch64_print_operand_address): Adjust
the output asm format.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211511
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 10:57:47 +0000 (10:57 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209617.
2014-04-22 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_cm<optab>di): Always split.
(*aarch64_cm<optab>di): New.
(aarch64_cmtstdi): Always split.
(*aarch64_cmtstdi): New.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211509
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 10:54:12 +0000 (10:54 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209615.
2014-04-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.c (arm_hard_regno_mode_ok): Loosen
restrictions on core registers for DImode values in Thumb2.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211508
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 10:50:18 +0000 (10:50 +0000)]
Backport from trunk r209614 (stacked on r209613).
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209614.
2014-04-22 Ian Bolton <ian.bolton@arm.com>
* config/arm/arm.md (*anddi_notdi_zesidi): New pattern.
* config/arm/thumb2.md (*iordi_notdi_zesidi): New pattern.
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209614.
2014-04-22 Ian Bolton <ian.bolton@arm.com>
* gcc.target/arm/anddi_notdi-1.c: New test.
* gcc.target/arm/iordi_notdi-1.c: New test case.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211507
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 10:38:46 +0000 (10:38 +0000)]
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209613.
2014-04-22 Ian Bolton <ian.bolton@arm.com>
* config/arm/thumb2.md (*iordi_notdi_di): New pattern.
(*iordi_notzesidi_di): Likewise.
(*iordi_notsesidi_di): Likewise.
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209613.
2014-04-22 Ian Bolton <ian.bolton@arm.com>
* gcc.target/arm/iordi_notdi-1.c: New test.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211506
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 10:34:28 +0000 (10:34 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209561.
2014-04-22 Ian Bolton <ian.bolton@arm.com>
* config/arm/arm-protos.h (tune_params): New struct members.
* config/arm/arm.c: Initialise tune_params per processor.
(thumb2_reorg): Suppress conversion from t32 to t16 when optimizing
for speed, based on new tune_params.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211505
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 10:31:10 +0000 (10:31 +0000)]
Add missing testcase in previous backport.
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209559.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vrnd_f64_1.c : New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211504
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 09:17:22 +0000 (09:17 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209559.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* config/aarch64/aarch64-builtins.c (BUILTIN_VDQF_DF): Macro
added.
* config/aarch64/aarch64-simd-builtins.def (frintn): Use added
macro.
* config/aarch64/aarch64-simd.md (<frint_pattern>): Comment
corrected.
* config/aarch64/aarch64.md (<frint_pattern>): Likewise.
* config/aarch64/arm_neon.h (vrnd_f64): Added.
(vrnda_f64): Likewise.
(vrndi_f64): Likewise.
(vrndm_f64): Likewise.
(vrndn_f64): Likewise.
(vrndp_f64): Likewise.
(vrndx_f64): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211498
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 09:13:57 +0000 (09:13 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209419.
2014-04-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR rtl-optimization/60663
* config/arm/arm.c (arm_new_rtx_costs): Improve ASM_OPERANDS case,
avoid 0 cost.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211497
138bc75d-0d04-0410-961f-
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yroux [Thu, 12 Jun 2014 09:09:04 +0000 (09:09 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209457.
2014-04-16 Andrew Pinski <apinski@cavium.com>
* config/host-linux.c (TRY_EMPTY_VM_SPACE): Change aarch64 ilp32
definition.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211496
138bc75d-0d04-0410-961f-
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yroux [Thu, 12 Jun 2014 09:05:08 +0000 (09:05 +0000)]
Merge branches/gcc-4_9-branch rev 211054
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211495
138bc75d-0d04-0410-961f-
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yroux [Mon, 19 May 2014 07:55:48 +0000 (07:55 +0000)]
Bump version number, post release.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@210607
138bc75d-0d04-0410-961f-
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yroux [Mon, 19 May 2014 07:50:29 +0000 (07:50 +0000)]
Make Linaro GCC 4.9-2014.05.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@210605
138bc75d-0d04-0410-961f-
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yroux [Tue, 13 May 2014 13:39:05 +0000 (13:39 +0000)]
gcc/
2014-05-13 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209889.
2014-04-29 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* config/aarch64/aarch64.md (mov<mode>cc): New for GPF.
gcc/testsuite/
2014-05-13 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209889.
2014-04-29 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* gcc.target/aarch64/fcsel_1.c: New test case.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@210376
138bc75d-0d04-0410-961f-
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yroux [Tue, 13 May 2014 13:34:20 +0000 (13:34 +0000)]
gcc/
2014-05-13 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209556.
2014-04-22 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* config/arm/arm.c (arm_print_operand, thumb_exit): Make sure
GET_MODE_SIZE argument is enum machine_mode.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@210373
138bc75d-0d04-0410-961f-
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yroux [Tue, 13 May 2014 13:29:26 +0000 (13:29 +0000)]
gcc/ada/
2014-05-13 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209653,209866,209871.
2014-04-28 Richard Henderson <rth@redhat.com>
* gcc-interface/Makefile.in: Support aarch64-linux.
2014-04-28 Eric Botcazou <ebotcazou@adacore.com>
* exp_dbug.ads (Get_External_Name): Add 'False' default to Has_Suffix,
add 'Suffix' parameter and adjust comment.
(Get_External_Name_With_Suffix): Delete.
* exp_dbug.adb (Get_External_Name_With_Suffix): Merge into...
(Get_External_Name): ...here. Add 'False' default to Has_Suffix, add
'Suffix' parameter.
(Get_Encoded_Name): Remove 2nd argument in call to Get_External_Name.
Call Get_External_Name instead of Get_External_Name_With_Suffix.
(Get_Secondary_DT_External_Name): Likewise.
* exp_cg.adb (Write_Call_Info): Likewise.
* exp_disp.adb (Export_DT): Likewise.
(Import_DT): Likewise.
* comperr.ads (Compiler_Abort): Remove Code parameter and add From_GCC
parameter with False default.
* comperr.adb (Compiler_Abort): Likewise. Adjust accordingly.
* types.h (Fat_Pointer): Rename into...
(String_Pointer): ...this. Add comment on interfacing rules.
* fe.h (Compiler_Abort): Adjust for above renaming.
(Error_Msg_N): Likewise.
(Error_Msg_NE): Likewise.
(Get_External_Name): Likewise. Add third parameter.
(Get_External_Name_With_Suffix): Delete.
* gcc-interface/decl.c (STDCALL_PREFIX): Define.
(create_concat_name): Adjust call to Get_External_Name, remove call to
Get_External_Name_With_Suffix, use STDCALL_PREFIX, adjust for renaming.
* gcc-interface/trans.c (post_error): Likewise.
(post_error_ne): Likewise.
* gcc-interface/misc.c (internal_error_function): Likewise.
2014-04-22 Richard Henderson <rth@redhat.com>
* init.c [__linux__] (HAVE_GNAT_ALTERNATE_STACK): New define.
(__gnat_alternate_stack): Enable for all linux except ia64.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@210372
138bc75d-0d04-0410-961f-
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yroux [Tue, 13 May 2014 13:08:40 +0000 (13:08 +0000)]
Merge branches/gcc-4_9-branch rev 210052
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@210370
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Mon, 28 Apr 2014 11:04:05 +0000 (11:04 +0000)]
Bump version number, post release.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@209855
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Mon, 28 Apr 2014 10:58:06 +0000 (10:58 +0000)]
Make Linaro GCC 4.9-2014.04.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@209853
138bc75d-0d04-0410-961f-
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yroux [Tue, 22 Apr 2014 14:15:34 +0000 (14:15 +0000)]
Merge branches/gcc-4_9-branch up to rev 209633
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@209635
138bc75d-0d04-0410-961f-
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yroux [Tue, 22 Apr 2014 14:00:25 +0000 (14:00 +0000)]
Merge branches/gcc-4_9-branch rev 209611 (FSF GCC 4.9.0 release).
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@209634
138bc75d-0d04-0410-961f-
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yroux [Mon, 14 Apr 2014 12:35:24 +0000 (12:35 +0000)]
Create linaro/gcc-4_9-branch.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@209366
138bc75d-0d04-0410-961f-
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projects / platform / upstream / gcc49.git / log