platform/upstream/mesa.git
3 years agowinsys/amdgpu: move amdgpu_winsys_bo::use_reusable_pool to the u.real union
Marek Olšák [Wed, 3 Feb 2021 05:03:22 +0000 (00:03 -0500)]
winsys/amdgpu: move amdgpu_winsys_bo::use_reusable_pool to the u.real union

It's never true with slab and sparse buffers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

3 years agowinsys/amdgpu: move amdgpu_winsys_bo::is_user_ptr to the u.real union
Marek Olšák [Wed, 3 Feb 2021 05:03:22 +0000 (00:03 -0500)]
winsys/amdgpu: move amdgpu_winsys_bo::is_user_ptr to the u.real union

It's never true with slab and sparse buffers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

3 years agowinsys/amdgpu: move amdgpu_winsys_bo::is_shared to the u.real union
Marek Olšák [Wed, 3 Feb 2021 05:03:22 +0000 (00:03 -0500)]
winsys/amdgpu: move amdgpu_winsys_bo::is_shared to the u.real union

It's never true with slab and sparse buffers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

3 years agowinsys/amdgpu: move amdgpu_winsys_bo::cpu_ptr into the u.real union
Marek Olšák [Wed, 3 Feb 2021 04:57:28 +0000 (23:57 -0500)]
winsys/amdgpu: move amdgpu_winsys_bo::cpu_ptr into the u.real union

It's never used with slab and sparse buffers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

3 years agowinsys/amdgpu: pack amdgpu_winsys_bo::is_shared and protect it by a mutex
Marek Olšák [Wed, 3 Feb 2021 04:52:58 +0000 (23:52 -0500)]
winsys/amdgpu: pack amdgpu_winsys_bo::is_shared and protect it by a mutex

The initialization of abs_timeout fixes a warning that started appearing
with this commit.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

3 years agowinsys/amdgpu: remove amdgpu_winsys_bo::num_cs_references to remove atomics
Marek Olšák [Wed, 3 Feb 2021 03:37:28 +0000 (22:37 -0500)]
winsys/amdgpu: remove amdgpu_winsys_bo::num_cs_references to remove atomics

This decreases the CPU time percentage of amdgpu_cs_add_buffer by 50%
on Ryzen 3900X.

We don't need to call amdgpu_bo_is_referenced_by_any_cs
in amdgpu_bo_can_reclaim. The reclaim function is only called for buffers
that have 0 references.

The only downside is that amdgpu_bo_is_referenced_by_cs might be slower
in some very rare cases. Overall the driver overhead is better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

3 years agowinsys/amdgpu: optimize out conditionals in amdgpu_lookup_buffer
Marek Olšák [Tue, 2 Feb 2021 01:24:07 +0000 (20:24 -0500)]
winsys/amdgpu: optimize out conditionals in amdgpu_lookup_buffer

Move them to a wrapper function.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8849>

3 years agotargets/libgl-xlib: add support for virgl
Chia-I Wu [Fri, 5 Feb 2021 22:57:39 +0000 (14:57 -0800)]
targets/libgl-xlib: add support for virgl

This allows testing virgl over vtest by setting GALLIUM_DRIVER=virpipe
when the X server uses a proprietary driver.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Tested-by: John Bates <jbates@chromium.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8888>

3 years agovirgl: Convert errno to string.
Vinson Lee [Fri, 5 Feb 2021 05:00:14 +0000 (21:00 -0800)]
virgl: Convert errno to string.

Fix defect reported by Coverity Scan.

Invalid type in argument to printf format specifier (PRINTF_ARGS)
invalid_type: Argument *__errno_location() to format specifier %s was expected to have type char * but has type int.

Fixes: d37124b065c ("virgl: add support for VIRGL_CAP_V2_UNTYPED_RESOURCE")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8874>

3 years agoradv: zero the bo descriptor array when allocating a new set
Mike Blumenkrantz [Wed, 3 Feb 2021 12:17:17 +0000 (07:17 -0500)]
radv: zero the bo descriptor array when allocating a new set

this must be reset to avoid issues when using VK_DESCRIPTOR_BINDING_PARTIALLY_BOUND_BIT_EXT
when some descriptors in the set may not have been bound

fixes #4219

Fixes: 126d5adb11e ("radv: Use host memory pool for non-freeable descriptors.")

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8840>

3 years agoradv: null bo list pointer for null descriptors on update
Mike Blumenkrantz [Wed, 3 Feb 2021 00:59:12 +0000 (19:59 -0500)]
radv: null bo list pointer for null descriptors on update

failing to unset any existing pointers here leads to stale bo entries in
the list and then the kernel rejecting the cmdbuf with ENOENT

Fixes: 126d5adb11e ("radv: Use host memory pool for non-freeable descriptors.")

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8840>

3 years agonv50,nvc0: clear internal vbo masks based on the trailing slots
Ilia Mirkin [Fri, 5 Feb 2021 16:08:40 +0000 (11:08 -0500)]
nv50,nvc0: clear internal vbo masks based on the trailing slots

Fixes: 0278d1fa323c (gallium: add unbind_num_trailing_slots to set_vertex_buffers)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8882>

3 years agopan/bi: Implement ACMPXCHG
Alyssa Rosenzweig [Wed, 3 Feb 2021 19:09:46 +0000 (14:09 -0500)]
pan/bi: Implement ACMPXCHG

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>

3 years agopan/bi: Implement AXCHG
Alyssa Rosenzweig [Wed, 3 Feb 2021 18:49:49 +0000 (13:49 -0500)]
pan/bi: Implement AXCHG

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>

3 years agopan/bi: Respect side effects in DCE
Alyssa Rosenzweig [Wed, 3 Feb 2021 19:35:02 +0000 (14:35 -0500)]
pan/bi: Respect side effects in DCE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>

3 years agopan/bi: Add side_effects helper
Alyssa Rosenzweig [Wed, 3 Feb 2021 19:33:48 +0000 (14:33 -0500)]
pan/bi: Add side_effects helper

DCE needs to be tuned for this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>

3 years agopan/bi: Fix NULL deref with empty shader
Alyssa Rosenzweig [Wed, 3 Feb 2021 19:11:44 +0000 (14:11 -0500)]
pan/bi: Fix NULL deref with empty shader

Fixes regression in dEQP-GLES31.functional.compute.basic.empty

Fixes: d0902aa2d4d ("pan/bi: Pass through wait_{6, 7} flags")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>

3 years agopan/bi: Make sure we never branch to an non-existing clause
Boris Brezillon [Mon, 25 Jan 2021 11:08:15 +0000 (12:08 +0100)]
pan/bi: Make sure we never branch to an non-existing clause

Branch instructions can point to the last shader block, which might be
empty. In this case, the branch points to a clause that doesn't exists,
leading to INVALID_ENC faults when the GPU tries to jump to this clause.

Check if the block is a terminal block before updating the branch
offset: jumping/branching to NULL is equivalent to a shader termination,
so the default value of 0 works just fine for terminal branches.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>

3 years agopan/bi: Add an is_terminal_block() helper
Boris Brezillon [Mon, 25 Jan 2021 11:02:21 +0000 (12:02 +0100)]
pan/bi: Add an is_terminal_block() helper

Needed to decide what to do with JUMPs/BRANCHes to such blocks.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8848>

3 years agoci: Update to newer ci-fairy
Michel Dänzer [Mon, 25 Jan 2021 11:01:28 +0000 (12:01 +0100)]
ci: Update to newer ci-fairy

To get the fix for
https://gitlab.freedesktop.org/freedesktop/ci-templates/-/issues/29 .

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8690>

3 years agoci: Fix MESA_TEMPLATES_COMMIT value
Michel Dänzer [Tue, 15 Dec 2020 17:02:04 +0000 (18:02 +0100)]
ci: Fix MESA_TEMPLATES_COMMIT value

The intention was to set it to the commit used for debian.yml, but I
accidentally set it to the ci-fairy.yml commit instead.

v2:
* While we're at it, put two dashes between the base tag and the
  ci-templates commit hash, making them easier to tell apart.
v3:
* While we're at it, fix the year of some recently bumped tags.

Fixes: 48f78dfd1ac1 "ci: Define global variable MESA_TEMPLATES_COMMIT
                     for ci-templates commit"

Reviewed-by: Eric Anholt <eric@anholt.net> # v2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8690>

3 years agoaco: always set exec_live=false
Rhys Perry [Wed, 27 Jan 2021 14:04:10 +0000 (14:04 +0000)]
aco: always set exec_live=false

Register demand calculation for exec masks doesn't always match
get_live_changes() and get_temp_registers(). For now, just set
exec_live=false.

fossil-db (GFX10.3):
Totals from 108230 (77.64% of 139391) affected shaders:
SGPRs: 5759658 -> 5756818 (-0.05%); split: -0.08%, +0.03%
VGPRs: 4061104 -> 4061248 (+0.00%); split: -0.00%, +0.01%
SpillSGPRs: 14114 -> 15198 (+7.68%); split: -0.10%, +7.78%
CodeSize: 266548396 -> 266603288 (+0.02%); split: -0.01%, +0.03%
MaxWaves: 1390885 -> 1390855 (-0.00%); split: +0.00%, -0.00%
Instrs: 50983353 -> 50992972 (+0.02%); split: -0.02%, +0.04%
Cycles: 1733042048 -> 1735443264 (+0.14%); split: -0.02%, +0.16%
VMEM: 41933625 -> 41914722 (-0.05%); split: +0.04%, -0.09%
SMEM: 7197675 -> 7197789 (+0.00%); split: +0.16%, -0.16%
VClause: 1050885 -> 1050978 (+0.01%); split: -0.02%, +0.03%
SClause: 2074913 -> 2071844 (-0.15%); split: -0.23%, +0.08%
Copies: 3181464 -> 3188125 (+0.21%); split: -0.38%, +0.59%
Branches: 1127526 -> 1127716 (+0.02%); split: -0.10%, +0.12%
PreSGPRs: 3376687 -> 3586076 (+6.20%); split: -0.00%, +6.20%
PreVGPRs: 3339740 -> 3339811 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8807>

3 years agozink: support using lavapipe
Erik Faye-Lund [Wed, 2 Dec 2020 16:26:26 +0000 (17:26 +0100)]
zink: support using lavapipe

This is really nasty, and shouldn't really be needed, but we have a
problem where both Zink and Lavapipe checks $GALLIUM_DRIVER, meaning that
Zink tries to use Lavapipe, and Lavapipe tries to use Zink.

This patch side-steps that by temporarily setting $GALLIUM_DRIVER to
"llvmpipe", giving Lavapipe a chance to succeed.

This is not great at all. The most obvious problem is that this is super
thread-unsafe, effectively modifying global state without any care. In
reality, we'd only want the pipe-loader in the *same thread* to ignore
Zink, but it's not so obvious how to do that without introducing lots of
ugly zink-specific cruft.

People shouldn't be using Zink if they don't have a GPU, it's going to
be much better to use LLVMpipe in that case. So let's not worry too much
about this case, and instead guard this dangerous logic with an
ZINK_USE_LAVAPIPE environment variable. This means this behavior only
happens if people opt in to it.

With this in place, we can start using Zink + Lavapipe on CI.

In the longer run, it might be better to use Adam Jackson's copper
loader instead, and drop exposing Zink as a software rasterizer
entirely. But that's something for the great future where we have flying
cars and all.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7881>

3 years agozink: explicitly check for VK_NULL_HANDLE
Erik Faye-Lund [Fri, 5 Feb 2021 11:49:50 +0000 (12:49 +0100)]
zink: explicitly check for VK_NULL_HANDLE

This seems a bit less like magic to me.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7881>

3 years agozink: check for error when calling vkEnumeratePhysicalDevices
Erik Faye-Lund [Fri, 5 Feb 2021 11:48:37 +0000 (12:48 +0100)]
zink: check for error when calling vkEnumeratePhysicalDevices

It seems it's possible for Lavapipe to fail to enumerate the physical
devices, so let's handle that and fail all the way up here.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7881>

3 years agoaco: add fallback algorithm in get_reg()
Rhys Perry [Wed, 9 Dec 2020 12:52:21 +0000 (12:52 +0000)]
aco: add fallback algorithm in get_reg()

The generated code is often terrible, but the situations where this is
needed are rare.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8713>

3 years agoradeon/vcn: enable dynamic dpb Tier1 support
Leo Liu [Wed, 3 Feb 2021 02:41:55 +0000 (21:41 -0500)]
radeon/vcn: enable dynamic dpb Tier1 support

For Raven and Navixx family i.e. VCN1 and VCN2 with VP9 codec

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8851>

3 years agoradeon/vcn: add dynamic dpb buffer Tier1 support
Leo Liu [Wed, 3 Feb 2021 02:24:47 +0000 (21:24 -0500)]
radeon/vcn: add dynamic dpb buffer Tier1 support

Also add its buffer index and fill up messages for the buffer.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8851>

3 years agoradeon/vcn: add dynamic dpb interface
Leo Liu [Sun, 31 Jan 2021 18:34:43 +0000 (13:34 -0500)]
radeon/vcn: add dynamic dpb interface

The new message buffer will save the dpb buffers from previous
allocation based on the max resolution.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8851>

3 years agoradeon/vcn: clean the message buffers and their indexes logic
Leo Liu [Wed, 3 Feb 2021 02:22:00 +0000 (21:22 -0500)]
radeon/vcn: clean the message buffers and their indexes logic

So the new buffer and index can be added sequentially.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8851>

3 years agozink: be a little more precise about query types in one conditional
Mike Blumenkrantz [Mon, 17 Aug 2020 14:58:08 +0000 (10:58 -0400)]
zink: be a little more precise about query types in one conditional

just for readability, no functional changes

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8516>

3 years agozink: unify shader image unbind codepath
Mike Blumenkrantz [Fri, 29 Jan 2021 15:07:06 +0000 (10:07 -0500)]
zink: unify shader image unbind codepath

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8780>

3 years agov3dv: allow a component swizzle in copy_buffer_to_image_shader
Iago Toral Quiroga [Fri, 5 Feb 2021 10:36:42 +0000 (11:36 +0100)]
v3dv: allow a component swizzle in copy_buffer_to_image_shader

This is trivial because this path relies on our blit_shader interface
which supports this already, so it just needs to pass it along.

I don't think this is ever triggered practice, since we should be
able to handle any case that could require this with the texel buffer
path, but at least it allows us to simplify a bit the code.

Tested by  manually disabling the priority paths to ensure we exercise
component swizzles with this path.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8875>

3 years agov3dv: batch copies in the copy_buffer_to_image_blit path
Iago Toral Quiroga [Fri, 5 Feb 2021 07:56:14 +0000 (08:56 +0100)]
v3dv: batch copies in the copy_buffer_to_image_blit path

This path is very memory hungry and batching allows us to reduce
this by allocating memory just once and reuse it for all regions
in the batch instead of allocating once per region.

v2: document return value for this function (apinheiro).

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8875>

3 years agov3dv: handle D/S buffer to image copies with the texel buffer path
Iago Toral Quiroga [Thu, 4 Feb 2021 07:17:43 +0000 (08:17 +0100)]
v3dv: handle D/S buffer to image copies with the texel buffer path

We do this by converting them to a compatible color copy and using a
destination color mask as well as a source component swizzle to handle
D24 format semantics according to the V3D hardware requirements,
similar to what we do with our blit shader interface.

This path is faster than the terrible copy_buffer_to_image_blit,
which requires to copy the source buffer to a tiled image first
and should be avoided as much as possible, since it is slow and
can also quickly increase device memory usage.

This fixes occasional OOM errors when loading traces in renderdoc.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8875>

3 years agopanfrost: Don't add the tiler BO when it's not accessed
Boris Brezillon [Wed, 3 Feb 2021 07:44:03 +0000 (08:44 +0100)]
panfrost: Don't add the tiler BO when it's not accessed

Only batches involving the tiler block need to add the tiler heap to the
list of accessed BOs. While at it, clarify who's accessing this heap.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8822>

3 years agopanfrost: Fix a polygon list corruption in the multi-context case
Boris Brezillon [Tue, 2 Feb 2021 08:32:41 +0000 (09:32 +0100)]
panfrost: Fix a polygon list corruption in the multi-context case

The polygon list is written by tiler jobs and read by fragment ones,
and nothing should re-use the heap until the fragment job is done.
4fec6c944817 ("panfrost: Add the tiler heap to fragment jobs") fixed
this for the !multi-context case by adding the heap BO to fragment job.
But the tiler heap is shared accross contexts, and vertex/tiler+fragment
job submission is done through 2 separate ioctls, meaning that
vertex/tiler and fragment jobs from 2 different context might be
interleaved.

Add a lock at the device level to ensure tiler/vertex+fragment jobs are
submitted sequentially, with no other jobs using the same tiler heap
in-between.

Cc: mesa-stable
Fixes: d8deb1eb6a22 ("panfrost: Share tiler_heap across batches/contexts")
Reported-by: Icecream95 <ixn@disroot.org>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8822>

3 years agospirv: Skip creating unused variables in SPIR-V >= 1.4
Caio Marcelo de Oliveira Filho [Tue, 12 Jan 2021 19:30:52 +0000 (11:30 -0800)]
spirv: Skip creating unused variables in SPIR-V >= 1.4

Newer versions of SPIR-V require that all the global variables used by
the entry point are declared (in contrast to only I/O in previous
versions), so there's no need to remove dead variables or keep track
of the indirectly used variables.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8456>

3 years agospirv: Count variables *after* unused ones are removed
Caio Marcelo de Oliveira Filho [Tue, 12 Jan 2021 18:25:58 +0000 (10:25 -0800)]
spirv: Count variables *after* unused ones are removed

Previous code was counting more variables than those used by the entry
point.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8456>

3 years agospirv: Use OpEntryPoint to identify valid I/O variables
Caio Marcelo de Oliveira Filho [Tue, 12 Jan 2021 17:55:46 +0000 (09:55 -0800)]
spirv: Use OpEntryPoint to identify valid I/O variables

OpEntryPoint declares the list of variables in Input and Output
storage classes that are used.  Use that information to skip creating
other variables from such storage classes that are unused by the entry
point.

After that change, is not necessary to use remove dead variables for
those types of variables; and because of that is also not necessary to
lower initalizers for output variables.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8456>

3 years agonv50/ir: Initialize BindArgumentsPass member sub in constructor.
Vinson Lee [Mon, 19 Oct 2020 23:23:45 +0000 (16:23 -0700)]
nv50/ir: Initialize BindArgumentsPass member sub in constructor.

Fix defect reported by Coverity.

Uninitialized pointer field (UNINIT_CTOR)
uninit_member: Non-static class member sub is not initialized in
this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7229>

3 years agofreedreno/a6xx: Add support for glDrawTransformFeedback().
Eric Anholt [Thu, 4 Feb 2021 22:20:16 +0000 (14:20 -0800)]
freedreno/a6xx: Add support for glDrawTransformFeedback().

It's exposed with ARB_tf2, which we claimed support for.  All the KHR-GL33
TF tests pass for me locally except for no_errors, which I have some
outstanding fixes for with khronos.  Our CI build seems to be having some
issue with exceptions inside of deqp.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8843>

3 years agodocs: Document PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME.
Eric Anholt [Wed, 3 Feb 2021 18:43:42 +0000 (10:43 -0800)]
docs: Document PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME.

It does more than the name suggests!

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8843>

3 years agofreedreno/a6xx: Skip guessing VSC size with indirect TF draw counts.
Eric Anholt [Wed, 3 Feb 2021 18:20:31 +0000 (10:20 -0800)]
freedreno/a6xx: Skip guessing VSC size with indirect TF draw counts.

Fixes an assertion failure when we try to figure out how many bits to
store the "0" draw count.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8843>

3 years agoradv: Pointer arithmetic without void*
James Park [Thu, 4 Feb 2021 20:54:20 +0000 (12:54 -0800)]
radv: Pointer arithmetic without void*

Fixes: 736834931bb ("radv: memset the alignment hole in cache_entry to 0")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8871>

3 years agoanv: Move extension tables to anv_device.c
Jason Ekstrand [Sat, 30 Jan 2021 04:40:39 +0000 (22:40 -0600)]
anv: Move extension tables to anv_device.c

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>

3 years agoanv,vulkan: Move anv_icd.py to a common location
Jason Ekstrand [Sat, 30 Jan 2021 16:08:37 +0000 (10:08 -0600)]
anv,vulkan: Move anv_icd.py to a common location

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>

3 years agoanv: Make anv_icd.py more generic and independent
Jason Ekstrand [Sat, 30 Jan 2021 15:57:27 +0000 (09:57 -0600)]
anv: Make anv_icd.py more generic and independent

Instead of depending on anv_extensions.py, fetch the patch version from
the XML ourselves.  This way it can be moved to common code and used by
other ICDs going forward.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>

3 years agoanv: Pull the patch version from the XML
Jason Ekstrand [Sat, 30 Jan 2021 16:04:00 +0000 (10:04 -0600)]
anv: Pull the patch version from the XML

For years, I've maintained that I like to bump this number manually
because it gives me a point at which to say, "I've looked at most of the
issues and I think we're up to date."  The reality, however, is that I
just bump it every few months and don't really do any thorough checking.
We may as well just bump it on header updates.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>

3 years agovulkan: Rework extension disabling on Android
Jason Ekstrand [Sat, 30 Jan 2021 17:13:33 +0000 (11:13 -0600)]
vulkan: Rework extension disabling on Android

Instead of building it into the auto-generated condition we use for the
per-driver ${driver}_physical_device_get_supported_extensions()
function, generate a table and handle it inside the various common
extension enumeration and verification routines.  This reduces our
reliance on code-gen for extension enables.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>

3 years agovulkan: Add a common helper for enumerating instance extension properties
Jason Ekstrand [Sat, 30 Jan 2021 17:03:27 +0000 (11:03 -0600)]
vulkan: Add a common helper for enumerating instance extension properties

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8792>

3 years agofreedreno/a2xx: fix scissors clamp bounds
Danylo Piliaiev [Thu, 4 Feb 2021 16:52:59 +0000 (18:52 +0200)]
freedreno/a2xx: fix scissors clamp bounds

a2xx has maximum viewport dimensions of 4096

Fixes: 6ae726b79988addc50c1ed149151a351d0343d9d ("freedreno: clamp scissor bounds")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8866>

3 years agofreedreno: Drop pointless clear of used providers.
Eric Anholt [Sat, 30 Jan 2021 00:49:12 +0000 (16:49 -0800)]
freedreno: Drop pointless clear of used providers.

We don't reuse batches, no need to do anything special here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8789>

3 years agofreedreno: Backport a5xx/a6xx fix for active query handling.
Eric Anholt [Thu, 28 Jan 2021 01:19:15 +0000 (17:19 -0800)]
freedreno: Backport a5xx/a6xx fix for active query handling.

The batch might not have stage == FD_STAGE_BLIT set because
fd_blitter_pipe_begin was sticking the stage on some random batch (or none
at all) rather than the one that would be used in the meta operation.

What we actually wanted to be looking at was set_active_query_state(),
which is already called by util_blitter and whose state we just needed to
track.

Fixes these piglit tests on a307:
occlusion_query_meta_fragments
occlusion_query_meta_save

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8789>

3 years agofreedreno: rename batch->active_providers to query_providers_used.
Eric Anholt [Sat, 30 Jan 2021 00:52:26 +0000 (16:52 -0800)]
freedreno: rename batch->active_providers to query_providers_used.

It's not the set of currently active providers, it's what's been used at
all in the current batch (this is used for doing the initialization of
query providers at initial HW setup in a submit).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8789>

3 years agofreedreno: Make sure that queries are disabled during shadow blits.
Eric Anholt [Mon, 1 Feb 2021 19:52:12 +0000 (11:52 -0800)]
freedreno: Make sure that queries are disabled during shadow blits.

They shouldn't count toward occlusion queries.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8789>

3 years agozink: move maintenance2 extension to right file
Mike Blumenkrantz [Wed, 3 Feb 2021 20:29:39 +0000 (15:29 -0500)]
zink: move maintenance2 extension to right file

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8862>

3 years agodrisw: Disable automatic use of layered drivers with LIBGL_ALWAYS_SOFTWARE
Jesse Natalie [Fri, 29 Jan 2021 17:53:23 +0000 (09:53 -0800)]
drisw: Disable automatic use of layered drivers with LIBGL_ALWAYS_SOFTWARE

If LIBGL_ALWAYS_SOFTWARE is set, then drisw is selected, and internally,
drisw should choose one of the actual software drivers. If it's not set,
but drisw is still selected (no hardware DRM driver, like in WSL), then
layered drivers are preferred over pure software.

Fixes: 4a3b42a7 ("drisw: Prefer hardware-layered sw-winsys drivers over pure sw")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4171
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8782>

3 years agofreedreno: clamp scissor bounds
Danylo Piliaiev [Wed, 23 Dec 2020 12:54:22 +0000 (14:54 +0200)]
freedreno: clamp scissor bounds

We don't have negative scissor coords and maximum dimensions are:
 a3xx - 4096
 a4xx+ - 16384

Fixes piglit tests:
 fbo-viewport
 viewport-clamp

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/30
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8209>

3 years agoradv: print image array size in debug mode
Mike Blumenkrantz [Tue, 2 Feb 2021 17:42:49 +0000 (12:42 -0500)]
radv: print image array size in debug mode

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8863>

3 years agodocs: fix invalid rst syntax
Erik Faye-Lund [Wed, 3 Feb 2021 10:16:52 +0000 (11:16 +0100)]
docs: fix invalid rst syntax

We need a newline here to avoid syntax errors while builind the
sphinx-documentation.

The errors don't lead the build fail, so we didn't notice this on CI.
Which is a shame IMO. Instead, the blocks simply fail to render.

Fixes: 2e2edaa89b4 ("docs/ci: Document setting up the http cache for traces.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8839>

3 years agofrontends/va: Update conditional checks for code stability.
SureshGuttula [Fri, 8 Jan 2021 02:09:31 +0000 (07:39 +0530)]
frontends/va: Update conditional checks for code stability.

Added parameter checks and updated returns based on that.

https://github.com/intel/libva-utils/tree/master/test

run test_va_api

Signed-off-by: SureshGuttula <sguttula@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8374>

3 years agonir/lower_io: Fix grammar errors
Alyssa Rosenzweig [Wed, 3 Feb 2021 18:49:39 +0000 (13:49 -0500)]
nir/lower_io: Fix grammar errors

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8846>

3 years agobroadcom/compiler: let QPUs stall on TMU input/config overflows
Iago Toral Quiroga [Wed, 3 Feb 2021 08:14:00 +0000 (09:14 +0100)]
broadcom/compiler: let QPUs stall on TMU input/config overflows

We have been trying to avoid this by tracking fifo usages in the driver and
flushing all outstanding TMU sequences if we overflowed any of these, however,
this is actually not the most efficient strategy. Instead, we would like to
flush only enough operations to get things going again, which is better for
pipelining. Doing that in the driver would require some additional work, but
thankfully, it is not required, since this seems to be what the hardware does
automatically, so we can just remove overflow tracking for these two fifos
and enjoy the benefits.

This also further improves shader-db stats:

total instructions in shared programs: 8975062 -> 8955145 (-0.22%)
instructions in affected programs: 1637624 -> 1617707 (-1.22%)
helped: 4050
HURT: 2241
Instructions are helped.

total threads in shared programs: 236802 -> 237042 (0.10%)
threads in affected programs: 252 -> 492 (95.24%)
helped: 122
HURT: 2
Threads are helped.

total sfu-stalls in shared programs: 19901 -> 19592 (-1.55%)
sfu-stalls in affected programs: 4744 -> 4435 (-6.51%)
helped: 1248
HURT: 1051
Sfu-stalls are helped.

total inst-and-stalls in shared programs: 8994963 -> 8974737 (-0.22%)
inst-and-stalls in affected programs: 1636184 -> 1615958 (-1.24%)
helped: 4050
HURT: 2239
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agobroadcom/compiler: log spilling shaders to perf output
Iago Toral Quiroga [Tue, 2 Feb 2021 09:12:07 +0000 (10:12 +0100)]
broadcom/compiler: log spilling shaders to perf output

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agobroadcom/compiler: disallow spilling if TMU pipelining was enabled
Iago Toral Quiroga [Tue, 2 Feb 2021 08:20:47 +0000 (09:20 +0100)]
broadcom/compiler: disallow spilling if TMU pipelining was enabled

TMU pipelining makes TMU spilling difficult and can easily lead to
doing large amounts of spills to compile a shader. It is best to
only use pipelining if we can compile without spilling.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agobroadcom/compiler: disable TMU pipelining if we fail to register allocate
Iago Toral Quiroga [Mon, 1 Feb 2021 10:01:47 +0000 (11:01 +0100)]
broadcom/compiler: disable TMU pipelining if we fail to register allocate

TMU pipelining can severely reduce our capacity to emit TMU spills,
causing us to fail to compile a shader we may otherwise be able to
compile. This is because pipelining extends the liveness of TMU
sequences by posponing the thread switch and LDTMU until a result
is needed, and we can't emit TMU spills while in the middle of a
TMU sequence.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agobroadcom/compiler: support pipelining of image load/store instructions
Iago Toral Quiroga [Thu, 28 Jan 2021 08:27:09 +0000 (09:27 +0100)]
broadcom/compiler: support pipelining of image load/store instructions

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agobroadcom/compiler: refactor image load/store TMU emission code
Iago Toral Quiroga [Thu, 28 Jan 2021 08:29:11 +0000 (09:29 +0100)]
broadcom/compiler: refactor image load/store TMU emission code

This mostly moves code around to group together the code involved with
actually emitting a TMU sequence. This will make it a bit easier to
then implement pipelining while reusing this code, similar to how we
handled other cases of TMU pipelining.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agobroadcom/compiler: support pipelining of tex instructions
Iago Toral Quiroga [Wed, 27 Jan 2021 08:45:52 +0000 (09:45 +0100)]
broadcom/compiler: support pipelining of tex instructions

This follows the same idea as for TMU general instructions of reusing
the existing infrastructure to first count required register writes and
flush outstanding TMU dependencies, and then emit the actual writes, which
requires that we split the code that decides about register writes to
a helper.

We also need to start using a component mask instead of the number
of components that we need to read with a particular TMU operation.

v2: update tmu_writes for V3D_QPU_WADDR_TMUOFF

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agobroadcom/compiler: implement pipelining for general TMU operations
Iago Toral Quiroga [Tue, 26 Jan 2021 11:18:43 +0000 (12:18 +0100)]
broadcom/compiler: implement pipelining for general TMU operations

This creates the basic infrastructure to implement TMU pipelining and
applies it to general TMU. Follow-up patches will expand this
to texture and image/load store operations.

TMU pipelining means that we don't immediately end TMU sequences,
and instead, we postpone the thread switch and LDTMU (for loads)
or TMUWT (for stores) until we really need to do them.

For loads, we may need to flush them if another instruction reads
the result of a load operation. We can detect this because in that
case ntq_get_src() will not find the definition for that ssa/reg
(since we have not emitted the LDTMU instructions for it yet), so
when that happens, we flush all pending TMU operations and then
try again to find the definition for the source.

We also need to flush pending TMU operations when we reach the end
of a control flow block, to prevent the case where we emit a TMU
operation in a block, but then we read the result in another block
possibly under control flow.

It is also required to flush across barriers and discards to honor
their semantics.

Since this change doesn't implement pipelining for texture and
image load/store, we also need to flush outstanding TMU operations
if we ever have to emit one of these. This will be corrected with
follow-up patches.

Finally, the TMU has 3 fifos where it can queue TMU operations.
These fifos have limited capacity, depending on the number of threads
used to compile the shader, so we also need to ensure that we
don't have too many outstanding TMU requests and flush pending
TMU operations if a new TMU operation would overflow any of these
fifos. While overflowing the Input and Config fifos only leads
to stalls (which we want to avoid anyway), overflowing the Output
fifo is incorrect and would end up with a broken shader. This means
that we need to know how many TMU register writes are required
to emit a TMU operation and use that information to decide if we need
to flush pending TMU operations before we emit any register
writes for the new TMU operation.

v2: fix TMU flushing for NIR registers reads (jasuarez)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agobroadcom/compiler: prepare TMU spilling code to account for TMU pipelining
Iago Toral Quiroga [Wed, 27 Jan 2021 12:00:30 +0000 (13:00 +0100)]
broadcom/compiler: prepare TMU spilling code to account for TMU pipelining

Follow-up patches will implement support for TMU pipelining in the
compiler, which basically means that we will be able to have more
than one outstanding TMU operation.

Our spilling code currently relies on properly identifying the end
of a TMU sequence (since we can't emit a new TMU sequence for a spill
in the middle of an existing TMU sequence), however, that code expects
that only one TMU sequence may be outstanding, which won't be true
once we implement pipelining.

This change fixes the 'end of TMU sequence' checks to account for this
in preparation for upcoming patches.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agobroadcom/compiler: fix indentation with TABs
Iago Toral Quiroga [Tue, 26 Jan 2021 11:19:30 +0000 (12:19 +0100)]
broadcom/compiler: fix indentation with TABs

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>

3 years agoci: Run 'time' in the background and propagate signals to test process
Michel Dänzer [Tue, 2 Feb 2021 10:38:19 +0000 (11:38 +0100)]
ci: Run 'time' in the background and propagate signals to test process

Simply exec'ing time didn't produce any output from it when a test
timed out.

Fixes: 35f59e14f833 "ci: Use GNU time as meson test wrapper"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8830>

3 years agonvc0/ir: Initialize SchedDataCalculator members in constructor.
Vinson Lee [Thu, 21 Jan 2021 00:57:49 +0000 (16:57 -0800)]
nvc0/ir: Initialize SchedDataCalculator members in constructor.

Fix defects reported by Coverity Scan.

uninit_member: Non-static class member score is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member prevData is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member prevOp is not initialized in this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8604>

3 years agonvc0/ir: Initialize NVC0LoweringPass member gpEmitAddress.
Vinson Lee [Thu, 21 Jan 2021 01:15:40 +0000 (17:15 -0800)]
nvc0/ir: Initialize NVC0LoweringPass member gpEmitAddress.

Fix defect reported by Coverity Scan.

Uninitialized pointer field (UNINIT_CTOR)
uninit_member: Non-static class member gpEmitAddress is not initialized
in this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8605>

3 years agoamd: Disable surface modifier test on Windows
James Park [Wed, 3 Feb 2021 19:42:07 +0000 (11:42 -0800)]
amd: Disable surface modifier test on Windows

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8855>

3 years agoradv: Implement VK_KHR_zero_initialize_workgroup_memory.
Bas Nieuwenhuizen [Sat, 19 Sep 2020 12:00:05 +0000 (14:00 +0200)]
radv: Implement VK_KHR_zero_initialize_workgroup_memory.

Reuses the pass that was implemented for ANV.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8751>

3 years agospirv: Fail when parsing invalid Initializers
Caio Marcelo de Oliveira Filho [Tue, 2 Feb 2021 07:19:13 +0000 (23:19 -0800)]
spirv: Fail when parsing invalid Initializers

Fail when parsing Initializers used in Variables with Storage Classes
that doesn't support it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8820>

3 years agozink: don't pick a cpu device ever.
Dave Airlie [Wed, 3 Feb 2021 04:17:46 +0000 (14:17 +1000)]
zink: don't pick a cpu device ever.

This goes down the list and picks the first non-cpu device, when
we merge the CI patch we should add a forcing env var in here.

Fixes: 8d46e35d1 ("zink: introduce opengl over vulkan")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8845>

3 years agowinsys/amdgpu: expand the slab allocation range to [256 B, 1 MB]
Marek Olšák [Sun, 24 Jan 2021 06:14:54 +0000 (01:14 -0500)]
winsys/amdgpu: expand the slab allocation range to [256 B, 1 MB]

This increases the wasted memory to 140 MB for DeusExMD, still below
the original number. The advantage is that we now get 2 MB pages for more
buffers and fewer total buffers allocated by the kernel, enabling faster
GPU page translation and slightly lower kernel overhead.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8683>

3 years agowinsys/amdgpu,pb_slab: add slabs with 3/4 of power of two sizes to save memory
Marek Olšák [Sun, 24 Jan 2021 02:53:30 +0000 (21:53 -0500)]
winsys/amdgpu,pb_slab: add slabs with 3/4 of power of two sizes to save memory

Instead of aligning slab allocations to powers of two (e.g. 129K -> 256K),
implement slab allocations with 3/4 of power of two sizes to reduce
overallocation. (e.g. 129K -> 192K)

The limitation is that the alignment must be 1/3rd of the allocation size.

DeusExMD allocates 2.1 GB of VRAM. Without this, slabs waste 194 MB due
to alignment, i.e. 9.2%. This commit reduces the waste to 102 MB, i.e. 4.9%.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8683>

3 years agowinsys/amdgpu: clean up slab alignment code, handle small buffers better
Marek Olšák [Sun, 24 Jan 2021 02:43:05 +0000 (21:43 -0500)]
winsys/amdgpu: clean up slab alignment code, handle small buffers better

The next commit will build upon this.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8683>

3 years agowinsys/amdgpu,radeonsi: add HUD counters for how much memory is wasted by slabs
Marek Olšák [Sat, 23 Jan 2021 22:21:44 +0000 (17:21 -0500)]
winsys/amdgpu,radeonsi: add HUD counters for how much memory is wasted by slabs

Slabs always allocate the next power of two size from their pools. This
wastes memory if the size is not a power of two.

bo->base.size is overwritten because the default is the allocated power of
two size, but we need the real size to compute the wasted size in
amdgpu_bo_slab_destroy. entry_size is added to the hole in pb_slab_entry
to hold the real entry size.

Like other memory stats, no atomics are used.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8683>

3 years agoradv: fix waiting on the last enabled RB for occlusion queries
Samuel Pitoiset [Tue, 2 Feb 2021 18:52:09 +0000 (19:52 +0100)]
radv: fix waiting on the last enabled RB for occlusion queries

Wait on the last enabled RB, not the last RB. This fixes GPU hangs
because the GPU was waiting forever.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4212
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8836>

3 years agofreedreno: Put an upper limit on VSC size
Rob Clark [Tue, 2 Feb 2021 20:32:22 +0000 (12:32 -0800)]
freedreno: Put an upper limit on VSC size

Left unchecked, an app that just did an endless series of draws could
result in VSC buffer sizes >4GB, which doesn't work out well.

This limit is semi-arbitrary (ie. it is lower than hw limit, but 32*8MB
seems a bit excessive and not a limit that you'd hit in the real world).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8842>

3 years agofreedreno/decode: Fix overflow
Rob Clark [Tue, 2 Feb 2021 20:12:14 +0000 (12:12 -0800)]
freedreno/decode: Fix overflow

CP_SET_DRAW_STATE state-groups count as a 4th level of IB.  Fixes a
crash seen on 32b/arm builds of crashdec.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8842>

3 years agoturnip: fix resolve MSAA D32_SFLOAT_S8_UINT image to S8_UINT
Samuel Iglesias Gonsálvez [Wed, 13 Jan 2021 08:06:51 +0000 (08:06 +0000)]
turnip: fix resolve MSAA D32_SFLOAT_S8_UINT image to S8_UINT

According to VK_KHR_depth_stencil_resolve spec (see
VUID-VkSubpassDescriptionDepthStencilResolve-pDepthStencilResolveAttachment-03182):

"If the VkFormat of pDepthStencilResolveAttachment has a stencil
component, then the VkFormat of pDepthStencilAttachment must have a
stencil component with the same number of bits and numerical
type"

The issue with D32_SFLOAT_S8_UINT format is that it is implemented as
two planes, so we need to execute the separate_stencil path in
tu_emit_blit() to resolve its stencil component into S8_UINT image.

Fixes the following tests:

dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8527>

3 years agoturnip: fix resolve MSAA D24_UNORM_S8_UINT image to S8_UINT
Samuel Iglesias Gonsálvez [Tue, 12 Jan 2021 21:31:33 +0000 (21:31 +0000)]
turnip: fix resolve MSAA D24_UNORM_S8_UINT image to S8_UINT

According to VK_KHR_depth_stencil_resolve spec (see
VUID-VkSubpassDescriptionDepthStencilResolve-pDepthStencilResolveAttachment-03182)

"If the VkFormat of pDepthStencilResolveAttachment has a stencil
component, then the VkFormat of pDepthStencilAttachment must have a
stencil component with the same number of bits and numerical type"

That means that we can resolve MSAA depth/stencil to a stencil only
image only if the stencil component matches with same number of bits
and type.

Although the driver only supports VK_RESOLVE_MODE_SAMPLE_ZERO_BIT
resolve mode, it was doing a sample average when resolving a MSAA
D24_UNORM_S8_UINT image to S8_UINT.

Fixes the following tests:

dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.compatibility_depth_zero_stencil_zero_testing_s
tencil
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.compatibility_depth_zero_stenc
il_zero_testing_stencil

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8527>

3 years agoi965: use aligned malloc for context instead of ralloc
Tapani Pälli [Tue, 2 Feb 2021 09:33:23 +0000 (11:33 +0200)]
i965: use aligned malloc for context instead of ralloc

Fixes: 3175b63a ("mesa: don't allocate matrices with malloc")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4118
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8805>

3 years agointel/perf: introduce additional ralloc context parameter
Tapani Pälli [Tue, 2 Feb 2021 09:26:16 +0000 (11:26 +0200)]
intel/perf: introduce additional ralloc context parameter

This makes it possible to use a separate ralloc context, not gl context
itself which might not be allocated with ralloc.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8805>

3 years agointel/perf: cleanup, remove duplicate function declaration
Tapani Pälli [Tue, 2 Feb 2021 09:21:37 +0000 (11:21 +0200)]
intel/perf: cleanup, remove duplicate function declaration

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8805>

3 years agoradv: Fix assert.
Bas Nieuwenhuizen [Tue, 2 Feb 2021 12:15:20 +0000 (13:15 +0100)]
radv: Fix assert.

Fixes: 7f7da82dbb7 ("radv: Add image layout with drm format modifiers.")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8828>

3 years agoradv: Add modifier fails for CTS bug.
Bas Nieuwenhuizen [Tue, 2 Feb 2021 12:13:29 +0000 (13:13 +0100)]
radv: Add modifier fails for CTS bug.

Fixes: 58e52326254 ("radv: Enable DRM format modifiers on GFX9+.")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8828>

3 years agoradv: memset the alignment hole in cache_entry to 0
Witold Baryluk [Thu, 28 Jan 2021 17:52:06 +0000 (17:52 +0000)]
radv: memset the alignment hole in cache_entry to 0

Detected using valgrind. Otherwise these bytes at the end
will be touched by zstd compression, spamming valgrind output.

Other option is to do full memset(entry, 0, size),
but that is somehow unnecessary and suboptimal.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8229>

3 years agoturnip: fix UINT64_MAX size wrapping in tu_GetBufferMemoryRequirements()
Samuel Iglesias Gonsálvez [Wed, 3 Feb 2021 08:36:52 +0000 (09:36 +0100)]
turnip: fix UINT64_MAX size wrapping in tu_GetBufferMemoryRequirements()

tu_GetBufferMemoryRequirements() ends up wrapping the UINT64_MAX size
to 0 when aligning.

Fixes:

   dEQP-VK.api.buffer.basic.size_max_uint64

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4493>

3 years agoturnip: set sparseAddressSpaceSize to zero
Samuel Iglesias Gonsálvez [Thu, 9 Apr 2020 08:16:51 +0000 (10:16 +0200)]
turnip: set sparseAddressSpaceSize to zero

According to Vulkan spec, "Table 46. Required Limits", as sparse
binding is unsupported, we need to return unsupported limit for
sparseAddressSpaceSize, which is zero.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4493>

3 years agopan/decode: Prefer sizeof to ARRAY_SIZE for char
Alyssa Rosenzweig [Mon, 18 Jan 2021 19:13:32 +0000 (14:13 -0500)]
pan/decode: Prefer sizeof to ARRAY_SIZE for char

One less macro.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>

3 years agopan/decode: Remove tile range validation
Alyssa Rosenzweig [Mon, 18 Jan 2021 19:12:40 +0000 (14:12 -0500)]
pan/decode: Remove tile range validation

Fault pointer works as you expect so it's not terribly useful.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>

3 years agopan/mdg: Drop unused stage parameter to disassembler
Alyssa Rosenzweig [Mon, 18 Jan 2021 19:10:13 +0000 (14:10 -0500)]
pan/mdg: Drop unused stage parameter to disassembler

No longer used but was adding a dependency on compiler/shader_enums.h

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>