Andrea Di Biagio [Mon, 30 Apr 2018 12:13:04 +0000 (12:13 +0000)]
[llvm-mca] Regenerate test Atom/resources-sse3.s. NFC
Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom.
llvm-svn: 331170
Andrea Di Biagio [Mon, 30 Apr 2018 12:05:34 +0000 (12:05 +0000)]
[llvm-mca] Support for in-order CPU for -instruction-tables testing.
Added Intel Atom tests to verify that the tool correctly generates instruction
tables even if the CPU is in-order.
Fixes PR37282.
llvm-svn: 331169
Haojian Wu [Mon, 30 Apr 2018 11:40:02 +0000 (11:40 +0000)]
[clangd] Also use UTF-16 in index position.
Reviewers: sammccall
Subscribers: klimek, ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits
Differential Revision: https://reviews.llvm.org/D46258
llvm-svn: 331168
Simon Pilgrim [Mon, 30 Apr 2018 10:46:35 +0000 (10:46 +0000)]
[X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructions
The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions.
llvm-svn: 331167
Gabor Buella [Mon, 30 Apr 2018 10:18:11 +0000 (10:18 +0000)]
NFC - Typo fixes lib/VMCore -> lib/IR
llvm-svn: 331166
Simon Dardis [Mon, 30 Apr 2018 09:44:44 +0000 (09:44 +0000)]
[mips] Fix microMIPS loads and stores.
Previously these instructions were unselectable and instead were generated
through the instruction mapping tables.
Reviewers: atanasyan, smaksimovic, abeserminji
Differential Revision: https://reviews.llvm.org/D46055
llvm-svn: 331165
Mikhail Maltsev [Mon, 30 Apr 2018 09:11:08 +0000 (09:11 +0000)]
[Targets] Implement getConstraintRegister for ARM and AArch64
Summary:
The getConstraintRegister method is used by semantic checking of
inline assembly statements in order to diagnose conflicts between
clobber list and input/output lists. Currently ARM and AArch64 don't
override getConstraintRegister, so conflicts between registers
assigned to variables in asm labels and clobber lists are not
diagnosed. Such conflicts can cause assertion failures in the back end
and even miscompilations.
This patch implements getConstraintRegister for ARM and AArch64
targets. Since these targets don't have single-register constraints,
the implementation is trivial and just returns the register specified
in an asm label (if any).
Reviewers: eli.friedman, javed.absar, thopre
Reviewed By: thopre
Subscribers: rengolin, eraman, rogfer01, myatsina, kristof.beyls, cfe-commits, chrib
Differential Revision: https://reviews.llvm.org/D45965
llvm-svn: 331164
Dmitry Vyukov [Mon, 30 Apr 2018 07:28:45 +0000 (07:28 +0000)]
tsan: disable trace switching after multithreaded fork
The problem is reported in:
https://github.com/google/sanitizers/issues/945
We already disable as much as possible after multithreaded fork,
trace switching is last place that can hang due to basic
operations (memory accesses, function calls).
Disable it too.
llvm-svn: 331163
Sander de Smalen [Mon, 30 Apr 2018 07:24:38 +0000 (07:24 +0000)]
[AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:
ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
^
shift amount should be '1'
Instead of suggesting the packed, unscaled addressing mode:
expected 'z[0..31].d, (uxtw|sxtw)'
the assembler now suggests using the proper scaling:
expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46124
llvm-svn: 331162
Craig Topper [Mon, 30 Apr 2018 06:21:24 +0000 (06:21 +0000)]
[X86] Add a Requires<[In64BitMode]> to FARJMP64
Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder.
llvm-svn: 331161
Craig Topper [Mon, 30 Apr 2018 06:21:23 +0000 (06:21 +0000)]
[X86] Hide another instruction from the assembly matcher table to avoid a duplicate entry. NFC
llvm-svn: 331160
Craig Topper [Mon, 30 Apr 2018 06:21:22 +0000 (06:21 +0000)]
[X86] Remove some InstAliases aren't needed because a MnemonicAlias makes them unreachable.
llvm-svn: 331159
Craig Topper [Mon, 30 Apr 2018 06:21:21 +0000 (06:21 +0000)]
[X86] Remove some instructions from the Intel assembly matcher table as there are equivalent mode aware InstAliases that conflict.
The instructions have predicates of Not64BitMode, but there are identical strings in InstAliases that have Mode32Bit and Mode16Bit. But the ordering is uncontrolled and the less specific Not64BitMode was ordered first.
This patch hides the Not64BitMode from the table so there is no conflict anymore.
llvm-svn: 331158
Craig Topper [Mon, 30 Apr 2018 06:21:19 +0000 (06:21 +0000)]
[X86] Use a MnemonicAlias instead of an InstAlias.
llvm-svn: 331157
Richard Smith [Mon, 30 Apr 2018 05:26:07 +0000 (05:26 +0000)]
Fix up after clang r331155.
llvm-svn: 331156
Richard Smith [Mon, 30 Apr 2018 05:25:48 +0000 (05:25 +0000)]
PR37189 Fix incorrect end source location and spelling for a split '>>' token.
When a '>>' token is split into two '>' tokens (in C++11 onwards), or (as an
extension) when we do the same for other tokens starting with a '>', we can't
just use a location pointing to the first '>' as the location of the split
token, because that would result in our miscomputing the length and spelling
for the token. As a consequence, for example, a refactoring replacing 'A<X>'
with something else would sometimes replace one character too many, and
similarly diagnostics highlighting a template-id source range would highlight
one character too many.
Fix this by creating an expansion range covering the first character of the
'>>' token, whose spelling is '>'. For this to work, we generalize the
expansion range of a macro FileID to be either a token range (the common case)
or a character range (used in this new case).
llvm-svn: 331155
Craig Topper [Mon, 30 Apr 2018 01:53:12 +0000 (01:53 +0000)]
[X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.
I assume this was done because gas accepted it at one point, but current versions of gas don't.
llvm-svn: 331154
Craig Topper [Mon, 30 Apr 2018 01:53:10 +0000 (01:53 +0000)]
[X86] Mark some more InstAliases as 'att' syntax only.
These aliases are used to default the memory forms of call and jmp to the size of the operating mode. This doesn't work for Intel syntax. We have a different hack in the AsmParser code itself to force a size on unsized memory operands.
llvm-svn: 331153
Fangrui Song [Mon, 30 Apr 2018 00:34:09 +0000 (00:34 +0000)]
Rename DiagnosticClient to DiagnosticConsumer as per issue 5397.
llvm-svn: 331152
Nico Weber [Mon, 30 Apr 2018 00:08:06 +0000 (00:08 +0000)]
Remove a dead #ifdef.
Unix/Threading.inc should never be included on _WIN32. See also
https://reviews.llvm.org/D30526#1082292
llvm-svn: 331151
Nico Weber [Sun, 29 Apr 2018 23:05:11 +0000 (23:05 +0000)]
Move _LIBCPP_ENABLE_CXX17_REMOVED_UNEXPECTED_FUNCTIONS macro to build system
_LIBCPP_ENABLE_CXX17_REMOVED_UNEXPECTED_FUNCTIONS is currently used to
bring back std::unexpected, which is removed in C++17, but still needed
for libc++abi for backward compatibility.
This macro used to define in cxa_exception.cpp only, but actually
needed for all sources that touches exceptions.
So, a build-system-level macro is better fit to define this macro.
https://reviews.llvm.org/D46056
Patch from Taiju Tsuiku <tzik@chromium.org>!
llvm-svn: 331150
Craig Topper [Sun, 29 Apr 2018 22:55:54 +0000 (22:55 +0000)]
[X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.
This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas.
llvm-svn: 331149
Jan Kratochvil [Sun, 29 Apr 2018 19:47:48 +0000 (19:47 +0000)]
Support reading section ".gnu_debugaltlink"
Differential revision: https://reviews.llvm.org/D40468
llvm-svn: 331148
Simon Pilgrim [Sun, 29 Apr 2018 18:18:51 +0000 (18:18 +0000)]
[X86] Remove unnecessary BT InstRW overrides.
llvm-svn: 331147
Sander de Smalen [Sun, 29 Apr 2018 18:18:21 +0000 (18:18 +0000)]
[AArch64][AsmParser] NFC: Cleanup of addOperands functions
Most of the add<operandname>Operands() functions are the same
and can be replaced by using a single 'RenderMethod' in
the AArch64InstrFormats.td file. Since many of the scaled
immediates (with different scaling/bits) are the same, most of
these can reuse the same AsmOperandClass.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D46122
llvm-svn: 331146
Sander de Smalen [Sun, 29 Apr 2018 17:33:38 +0000 (17:33 +0000)]
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46120
llvm-svn: 331145
Simon Pilgrim [Sun, 29 Apr 2018 15:45:31 +0000 (15:45 +0000)]
[llvm-mca][X86] Add BT resource tests to all models
llvm-svn: 331144
Simon Pilgrim [Sun, 29 Apr 2018 15:33:15 +0000 (15:33 +0000)]
[X86] Merge more instregex single matches to reduce InstrRW compile time.
llvm-svn: 331143
Simon Pilgrim [Sun, 29 Apr 2018 14:16:17 +0000 (14:16 +0000)]
[X86] Remove unnecessary add/adc+sub/sbb InstRW overrides.
llvm-svn: 331142
Dean Michael Berris [Sun, 29 Apr 2018 13:46:30 +0000 (13:46 +0000)]
[XRay][profiler] Part 1: XRay Allocator and Array Implementations
Summary:
This change is part of the larger XRay Profiling Mode effort.
Here we implement an arena allocator, for fixed sized buffers used in a
segmented array implementation. This change adds the segmented array
data structure, which relies on the allocator to provide and maintain
the storage for the segmented array.
Key features of the `Allocator` type:
* It uses cache-aligned blocks, intended to host the actual data. These
blocks are cache-line-size multiples of contiguous bytes.
* The `Allocator` has a maximum memory budget, set at construction
time. This allows us to cap the amount of data each specific
`Allocator` instance is responsible for.
* Upon destruction, the `Allocator` will clean up the storage it's
used, handing it back to the internal allocator used in
sanitizer_common.
Key features of the `Array` type:
* Each segmented array is always backed by an `Allocator`, which is
either user-provided or uses a global allocator.
* When an `Array` grows, it grows by appending a segment that's
fixed-sized. The size of each segment is computed by the number of
elements of type `T` that can fit into cache line multiples.
* An `Array` does not return memory to the `Allocator`, but it can keep
track of the current number of "live" objects it stores.
* When an `Array` is destroyed, it will not return memory to the
`Allocator`. Users should clean up the `Allocator` independently of
the `Array`.
* The `Array` type keeps a freelist of the chunks it's used before, so
that trimming and growing will re-use previously allocated chunks.
These basic data structures are used by the XRay Profiling Mode
implementation to implement efficient and cache-aware storage for data
that's typically read-and-write heavy for tracking latency information.
We're relying on the cache line characteristics of the architecture to
provide us good data isolation and cache friendliness, when we're
performing operations like searching for elements and/or updating data
hosted in these cache lines.
Reviewers: echristo, pelikan, kpw
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D45756
llvm-svn: 331141
Simon Pilgrim [Sun, 29 Apr 2018 11:03:25 +0000 (11:03 +0000)]
[llvm-mca][X86] Add add/adc + sub/sbb resource tests to all models
llvm-svn: 331140
Hideki Saito [Sun, 29 Apr 2018 07:26:18 +0000 (07:26 +0000)]
[NFC][LV][LoopUtil] Move LoopVectorizationLegality to its own file
Summary:
This is a follow up to D45420 (included here since it is still under review and this change is dependent on that) and D45072 (committed).
Actual change for this patch is LoopVectorize* and cmakefile. All others are all from D45420.
LoopVectorizationLegality is an analysis and thus really belongs to Analysis tree. It is modular enough and it is reusable enough ---- we can further improve those aspects once uses outside of LV picks up.
Hopefully, this will make it easier for people familiar with vectorization theory, but not necessarily LV itself to contribute, by lowering the volume of code they should deal with. We probably should start adding some code in LV to check its own capability (i.e., vectorization is legal but LV is not ready to handle it) and then bail out.
Reviewers: rengolin, fhahn, hfinkel, mkuper, aemerson, mssimpso, dcaballe, sguggill
Reviewed By: rengolin, dcaballe
Subscribers: egarcia, rogfer01, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D45552
llvm-svn: 331139
Craig Topper [Sun, 29 Apr 2018 06:24:09 +0000 (06:24 +0000)]
[X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add aliases based on 16/32-bit mode to choose the default.
This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size.
This matches gas behavior from what I could tell.
llvm-svn: 331138
Richard Smith [Sun, 29 Apr 2018 05:33:38 +0000 (05:33 +0000)]
Fix printing of reference-to-reference types.
Previously we would sometimes print these as 'T &&&' or even 'T &&&&'.
llvm-svn: 331137
Richard Smith [Sun, 29 Apr 2018 04:55:46 +0000 (04:55 +0000)]
PR37275 packed attribute should not apply to base classes
Clang incorrectly applied the packed attribute to base classes. Per GCC's
documentation and as can be observed from its behavior, packed only applies to
members, not base classes.
This change is conditioned behind -fclang-abi-compat so that an ABI break can
be avoided by users if desired.
Differential Revision: https://reviews.llvm.org/D46218
llvm-svn: 331136
Craig Topper [Sun, 29 Apr 2018 04:50:53 +0000 (04:50 +0000)]
[X86] Remove SLDT64m instruction.
It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything.
While I was touching the encoding tests to remove it, I added some other missing register form test cases.
llvm-svn: 331135
Craig Topper [Sun, 29 Apr 2018 04:06:02 +0000 (04:06 +0000)]
[X86] Remove unnecessary InstAliases. NFCI
These used to disambiguate MOV16ms/MOV16sm from other size instructions that no longer exist.
llvm-svn: 331134
Ed Maste [Sun, 29 Apr 2018 02:18:48 +0000 (02:18 +0000)]
Add -warn-backrefs (r329636) to lld's man page
llvm-svn: 331133
whitequark [Sun, 29 Apr 2018 02:01:34 +0000 (02:01 +0000)]
[LLVM-C] Eliminate an unused variable in a test.
This was introduced in r331123 and broke -Werror bots.
llvm-svn: 331132
Rafael Espindola [Sun, 29 Apr 2018 01:13:57 +0000 (01:13 +0000)]
Update my email address and description.
llvm-svn: 331131
Tobias Grosser [Sun, 29 Apr 2018 00:57:43 +0000 (00:57 +0000)]
Remove keep/take/give from isl C++ bindings
These functions have been legacy leftovers which we used before the
official C++ bindings existed. As all uses of these legacy functions
have been removed, this polly-specific extension can also be dropped.
llvm-svn: 331130
Tobias Grosser [Sun, 29 Apr 2018 00:57:38 +0000 (00:57 +0000)]
Remove another set or release() calls
llvm-svn: 331129
Craig Topper [Sun, 29 Apr 2018 00:53:10 +0000 (00:53 +0000)]
[X86] Use getX86SubSuperRegister in addGR32orGR64Operands in the AsmParser instead of duplicating its functionality. NFC
llvm-svn: 331128
Nico Weber [Sun, 29 Apr 2018 00:45:03 +0000 (00:45 +0000)]
s/LLVM_ON_WIN32/_WIN32/, llvm
LLVM_ON_WIN32 is set exactly with MSVC and MinGW (but not Cygwin) in
HandleLLVMOptions.cmake, which is where _WIN32 defined too. Just use the
default macro instead of a reinvented one.
See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.
No intended behavior change.
This moves over all uses of the macro, but doesn't remove the definition
of it in (llvm-)config.h yet.
llvm-svn: 331127
Tobias Grosser [Sun, 29 Apr 2018 00:28:26 +0000 (00:28 +0000)]
Remove the last uses of isl::give and isl::take
llvm-svn: 331126
Tobias Grosser [Sun, 29 Apr 2018 00:28:14 +0000 (00:28 +0000)]
Fix one unit test
llvm-svn: 331125
Nico Weber [Sat, 28 Apr 2018 23:48:36 +0000 (23:48 +0000)]
Remove unused includes of clang/Config/config.h
Found by opening config.h.cmake in vim, finding all defined macros with
/define\(01\)\? \zs[A-Za-z0-9_]*<cr>
:%s//\=setreg('A', submatch(0), 'V')/gn<cr>
:put A<cr>
and then joining them all with |, and passing that to
git grep -E that_pattern 'clang/*.h' 'clang/*.cpp' 'clang/*.c'
and diffing that output with the result of
git grep Config/config.h 'clang/*.h' 'clang/*.cpp' 'clang/*.c'
No intended behavior change.
llvm-svn: 331124
Robert Widmann [Sat, 28 Apr 2018 22:32:07 +0000 (22:32 +0000)]
[LLVM-C] Add DIBuilder bindings to create import declarations
Summary: Add bindings to create import declarations for modules, functions, types, and other entities. This wraps the conveniences available in the existing DIBuilder API, but these seem C++-specific.
Reviewers: whitequark, harlanhaskins, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46167
llvm-svn: 331123
Tobias Grosser [Sat, 28 Apr 2018 22:11:55 +0000 (22:11 +0000)]
[DeLICM] Remove uses of isl::give
llvm-svn: 331122
Tobias Grosser [Sat, 28 Apr 2018 22:11:48 +0000 (22:11 +0000)]
[ZoneAlgo] Remove uses of isl::give - II
llvm-svn: 331121
Tobias Grosser [Sat, 28 Apr 2018 21:22:17 +0000 (21:22 +0000)]
[ZoneAlgo] Remove uses of isl::give
This moves more of Polly to islpp.
llvm-svn: 331120
Tobias Grosser [Sat, 28 Apr 2018 21:06:14 +0000 (21:06 +0000)]
[islpp] Remove use of isl::give from unittests
We do this mostly by just moving directly to pure C++ code.
llvm-svn: 331119
Tobias Grosser [Sat, 28 Apr 2018 20:42:35 +0000 (20:42 +0000)]
[MaximalStaticExpansion] Replace copied function with version from ISLTools
llvm-svn: 331118
Craig Topper [Sat, 28 Apr 2018 18:46:11 +0000 (18:46 +0000)]
[X86] Restrict many of the InstAliases to either to only att or intel syntax. NFCI
Many of these aliases exist to give one syntax or the other a slightly different mnemonic and the other variant gets a duplicate of its normal mnemonic
This patch restricts a lot of these to only one variant so we don't get the duplication.
This removes a lot of duplicate entries from the matcher table. It also reduces the number of warnings printed when you enable the ambiguous match warning in tablegen.
llvm-svn: 331117
Simon Pilgrim [Sat, 28 Apr 2018 18:45:16 +0000 (18:45 +0000)]
[X86] Remove unnecessary rotate-carry folded InstRW overrides.
Merge some remaining instregex entries.
llvm-svn: 331116
Daniel Sanders [Sat, 28 Apr 2018 18:14:50 +0000 (18:14 +0000)]
[globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them
Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
improve optimization of extends and truncates, this legality requirement
would spread without considerable care w.r.t when certain combines were
permitted.
* The SelectionDAG importer required some ugly and fragile pattern
rewriting to translate patterns into this style.
This patch begins changing the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.
This patch introduces the new generic instructions and new variation on
G_LOAD and adds lowering for them to convert back to the existing
representations.
Depends on D45466
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar
Reviewed By: aemerson
Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D45540
llvm-svn: 331115
Robert Widmann [Sat, 28 Apr 2018 18:13:39 +0000 (18:13 +0000)]
[LLVM-C] Miscellaneous Cleanups in DIBuilder Bindings
Summary:
* rL328953 does not include bindings for LLVMDIBuilderCreateClassType and LLVMDIBuilderCreateBitFieldMemberType despite declaring their prototypes. Provide these bindings now.
* Switch to more precise types with specific numeric limits matching the DIBuilder's C++ API.
Reviewers: harlanhaskins, whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46168
llvm-svn: 331114
Tobias Grosser [Sat, 28 Apr 2018 16:02:30 +0000 (16:02 +0000)]
Update to latest version of the isl c++ bindings
The delta to the previous version is rather small, but a change in brace
placement makes this a rather noisy commit.
llvm-svn: 331113
Roman Lebedev [Sat, 28 Apr 2018 15:45:07 +0000 (15:45 +0000)]
[InstCombine] Canonicalize variable mask in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.
https://rise4fun.com/Alive/Yol
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45664
llvm-svn: 331112
Roman Lebedev [Sat, 28 Apr 2018 15:45:00 +0000 (15:45 +0000)]
[InstCombine][NFC] Add tests for variable mask canonicalization in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.
Differential Revision: https://reviews.llvm.org/D45663
llvm-svn: 331111
Simon Pilgrim [Sat, 28 Apr 2018 15:32:19 +0000 (15:32 +0000)]
[X86] Remove unnecessary shift/rotate folded InstRW overrides.
llvm-svn: 331110
Simon Pilgrim [Sat, 28 Apr 2018 15:18:49 +0000 (15:18 +0000)]
[llvm-mca][X86] Add double shift resource tests to all relevant models
llvm-svn: 331109
Simon Pilgrim [Sat, 28 Apr 2018 14:56:18 +0000 (14:56 +0000)]
[llvm-mca][X86] Add shift/rotate resource tests to all relevant models
I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch
llvm-svn: 331108
Simon Pilgrim [Sat, 28 Apr 2018 14:08:51 +0000 (14:08 +0000)]
[X86][SSE] Stop hard coding some instruction scheduler classes.
Make these arguments to the multiclass to allow easier specialization.
llvm-svn: 331107
Simon Pilgrim [Sat, 28 Apr 2018 14:06:28 +0000 (14:06 +0000)]
[X86][HW] Cleanup Haswell model. NFCI.
Moved LAHF/SAHF to instrs instead of instregex.
Removed some unnecessary instregex entries.
llvm-svn: 331106
Craig Topper [Sat, 28 Apr 2018 06:58:27 +0000 (06:58 +0000)]
[X86] Remove mayLoad flag from BNDMK/BNDCL/BNDCN/BNDCU.
The instruction documentation specifically says that these instruction don't access memory.
llvm-svn: 331105
Craig Topper [Sat, 28 Apr 2018 06:58:26 +0000 (06:58 +0000)]
[X86] Change memory operand of BNDMK/BNDCL/BNDCU/BNDCN/BNDST to anymem.
These instruction don't use their memory operands as normal memory operands. They're just used as addresses. They don't have a size because they aren't directly representing a load or store.
llvm-svn: 331104
Serguei Katkov [Sat, 28 Apr 2018 06:41:35 +0000 (06:41 +0000)]
[SCEV] Touch the unsused stats variables for product build.
This is a fix by elimination compiler warnings considered as errors.
llvm-svn: 331103
Craig Topper [Sat, 28 Apr 2018 06:02:40 +0000 (06:02 +0000)]
[X86] Remove REX.W from 64-bit mode BND instructions.
As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W.
llvm-svn: 331102
Craig Topper [Sat, 28 Apr 2018 06:02:39 +0000 (06:02 +0000)]
[X86] Rename BNDMOV instructions and hide redundant instruction encoding from the assembler.
Favor the 0x1a encoding for register/register move to match gas.
The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV.
Hide the _REV encoding from the assembler but leave it for the disassembler.
llvm-svn: 331101
Max Kazantsev [Sat, 28 Apr 2018 04:38:21 +0000 (04:38 +0000)]
[NFC] Add some tests that demonstrate unrecognized three-way comparison patterns
llvm-svn: 331100
Serguei Katkov [Sat, 28 Apr 2018 03:53:36 +0000 (03:53 +0000)]
[SCEV] Reduce the number of invocation to non trivial getExact function
The invocation of getExact in ScalarEvolution::getBackedgeTakenInfo is used
only for getting statistic and for assert.
Even if statistics is disabled, the code related to it will be eliminated
the invocation to getExact itself will not be eliminated
because it may have side-effects like creation of new SCEVs.
So do invocation only when we collect statistics or executes asserts.
Reviewers: mkazantsev, sanjoy, javed.absar
Reviewed By: javed.absar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46178
llvm-svn: 331099
Erik Pilkington [Sat, 28 Apr 2018 02:40:28 +0000 (02:40 +0000)]
[ItaniumMangle] Undeduced auto type shouldn't be substitutable.
We still support the old mangling if we're trying to be ABI-compatible with
Clang 6.0, though.
Differential revision: https://reviews.llvm.org/D45451
llvm-svn: 331098
Fangrui Song [Sat, 28 Apr 2018 00:12:02 +0000 (00:12 +0000)]
Migrate from std::pointer_to_unary_function as it is removed in C++17
llvm-svn: 331097
Artem Dergachev [Fri, 27 Apr 2018 23:50:55 +0000 (23:50 +0000)]
[analyzer] CStringChecker: Add support for BSD strlcpy() and strlcat().
Patch by David Carlier!
Differential Revision: https://reviews.llvm.org/D45177
llvm-svn: 331096
Jessica Paquette [Fri, 27 Apr 2018 23:36:35 +0000 (23:36 +0000)]
[MachineOutliner] Add defs to calls + don't track liveness on outlined functions
This commit makes it so that if you outline a def of some register, then the
call instruction created by the outliner actually reflects that the register
is defined by the call. It also makes it so that outlined functions don't
have the TracksLiveness property.
Outlined calls shouldn't break liveness assumptions that someone might make.
This also un-XFAILs the noredzone test, and updates the calls test.
llvm-svn: 331095
Philip Reames [Fri, 27 Apr 2018 23:15:56 +0000 (23:15 +0000)]
[LoopGuardWidening] Make PostDomTree optional
The effect of doing so is not disrupting the LoopPassManager when mixing this pass with other loop passes. This should help locality of access substaintially and avoids the cost of computing PostDom.
The assumption here is that the full GuardWidening (which does use PostDom) is run as a canonicalization before loop opts and that this version is just catching cases exposed by other loop passes. (i.e. LoopPredication, IndVarSimplify, LoopUnswitch, etc..)
llvm-svn: 331094
Reid Kleckner [Fri, 27 Apr 2018 22:32:21 +0000 (22:32 +0000)]
Fix diag-format test to not care about what cl.exe is on path
llvm-svn: 331093
Heejin Ahn [Fri, 27 Apr 2018 22:23:11 +0000 (22:23 +0000)]
[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor
Summary:
D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined
(https://github.com/llvm-mirror/llvm/blob/
c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006).
Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.
(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)
Reviewers: RKSimon, jgravelle-google
Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D46161
llvm-svn: 331092
Craig Topper [Fri, 27 Apr 2018 22:15:33 +0000 (22:15 +0000)]
[X86] Make the STTNI flag intrinsics use the flags from pcmpestrm/pcmpistrm if the mask instrinsics are also used in the same basic block.
Summary:
Previously the flag intrinsics always used the index instructions even if a mask instruction also exists.
To fix fix this I've created a single ISD node type that returns index, mask, and flags. The SelectionDAG CSE process will merge all flavors of intrinsics with the same inputs to a s ingle node. Then during isel we just have to look at which results are used to know what instruction to generate. If both mask and index are used we'll need to emit two instructions. But for all other cases we can emit a single instruction.
Since I had to do manual isel anyway, I've removed the pseudo instructions and custom inserter code that was working around tablegen limitations with multiple implicit defs.
I've also renamed the recently added sse42.ll test case to sttni.ll since it focuses on that subset of the sse4.2 instructions.
Reviewers: chandlerc, RKSimon, spatel
Reviewed By: chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46202
llvm-svn: 331091
Adrian Prantl [Fri, 27 Apr 2018 22:05:31 +0000 (22:05 +0000)]
Fix a bug that prevents global variables from having a DW_OP_deref.
For local variables the first DW_OP_deref is consumed by turning the
location kind into a memeory location, but that only makes sense for
values that are in a register to begin with, which cannot happen for
global variables that are attached to a symbol.
rdar://problem/
39741860
This reapplies r330970 after fixing an uncovered bug in r331086 and
working around the situation caused by it.
llvm-svn: 331090
Artem Dergachev [Fri, 27 Apr 2018 22:00:51 +0000 (22:00 +0000)]
[analyzer] ObjCAutoreleaseWrite: Support a few more APIs and fix warning text.
API list and improved warning text composed by Devin Coughlin.
llvm-svn: 331089
Reid Kleckner [Fri, 27 Apr 2018 21:51:25 +0000 (21:51 +0000)]
[FastISel] Actually enable local value sinking by default
llvm-svn: 331088
Reid Kleckner [Fri, 27 Apr 2018 21:48:51 +0000 (21:48 +0000)]
[FastISel] Fix local value sinking algorithmic complexity
Now local value sinking only scans and numbers instructions added
between the current flush point and the last flush point. This ensures
that ISel is overall linear in the size of the BB.
Fixes PR37010 and re-enables local value sinking by default.
llvm-svn: 331087
Adrian Prantl [Fri, 27 Apr 2018 21:41:36 +0000 (21:41 +0000)]
Fix a bug in GlobalOpt's handling of DIExpressions.
This patch adds support for fragment expressions
TryToShrinkGlobalToBoolean() which were previously just dropped.
Thanks to Reid Kleckner for providing me a reproducer!
llvm-svn: 331086
Roman Lebedev [Fri, 27 Apr 2018 21:23:20 +0000 (21:23 +0000)]
[PatternMatch] Stabilize the matching order of commutative matchers
Summary:
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the `LHS` and `RHS` matchers:
1. match `RHS` matcher to the `first` operand of binary operator,
2. and then match `LHS` matcher to the `second` operand of binary operator.
This works ok.
But it complicates writing of commutative matchers, where one would like to match
(`m_Value()`) the value on one side, and use (`m_Specific()`) it on the other side.
This is additionally complicated by the fact that `m_Specific()` stores the `Value *`,
not `Value **`, so it won't work at all out of the box.
The last problem is trivially solved by adding a new `m_c_Specific()` that stores the
`Value **`, not `Value *`. I'm choosing to add a new matcher, not change the existing
one because i guess all the current users are ok with existing behavior,
and this additional pointer indirection may have performance drawbacks.
Also, i'm storing pointer, not reference, because for some mysterious-to-me reason
it did not work with the reference.
The first one appears trivial, too.
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the ~~`LHS` and `RHS` matchers~~ **operands**:
1. match ~~`RHS`~~ **`LHS`** matcher to the ~~`first`~~ **`second`** operand of binary operator,
2. and then match ~~`LHS`~~ **`RHS`** matcher to the ~~`second`~ **`first`** operand of binary operator.
Surprisingly, `$ ninja check-llvm` still passes with this.
But i expect the bots will disagree..
The motivational unittest is included.
I'd like to use this in D45664.
Reviewers: spatel, craig.topper, arsenm, RKSimon
Reviewed By: craig.topper
Subscribers: xbolva00, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D45828
llvm-svn: 331085
Simon Pilgrim [Fri, 27 Apr 2018 21:14:19 +0000 (21:14 +0000)]
[X86] Merge some x87 instruction instregex single matches. NFCI.
llvm-svn: 331084
Sanjay Patel [Fri, 27 Apr 2018 21:14:15 +0000 (21:14 +0000)]
[Reassociate] add a test with debug info; NFC
As suggested in D45842
(although still not sure if we're going to advance that),
we must invalidate references to instructions that have
been recycled (operands were changed, so result is different).
llvm-svn: 331083
Greg Clayton [Fri, 27 Apr 2018 21:10:07 +0000 (21:10 +0000)]
Fix build bots after r331049 broke them.
llvm-svn: 331082
Daniel Sanders [Fri, 27 Apr 2018 21:03:27 +0000 (21:03 +0000)]
Attempt to fix remaining build failures after r331071 by changing the tuple to a struct
Some of the bots were failing in a different way to the others. These were
unable to compare tuples. Fix this by changing to a struct, thereby avoiding
the quirks of tuples.
llvm-svn: 331081
Philip Reames [Fri, 27 Apr 2018 20:58:30 +0000 (20:58 +0000)]
[LICM] Reduce nesting with an early return [NFC]
llvm-svn: 331080
Philip Reames [Fri, 27 Apr 2018 20:44:01 +0000 (20:44 +0000)]
[MustExecute/LICM] Special case first instruction in throwing header
We currently have a hard to solve analysis problem around the order of instructions within a potentially throwing block. We can't cheaply determine whether a given instruction is before the first potential throw in the block. While we're working on that in the background, special case the first instruction within the header.
why this particular special case? Well, headers are guaranteed to execute if the loop does, and it turns out we tend to produce this form in practice.
In a follow on patch, I tend to extend LICM with an alternate approach which works for any instruction in the header before the first throw, but this is the best I can come up with other users of the analysis (such as store promotion.)
Note: I can't show the difference in the analysis result since we're ORing in the expensive instruction walk used by SCEV. Using the full walk is not suitable for a general solution.
llvm-svn: 331079
Vlad Tsyrklevich [Fri, 27 Apr 2018 20:32:34 +0000 (20:32 +0000)]
ELFObjectWriter: Allow one unique symver per symbol
Summary:
Only allow a single unique .symver alias per symbol. This matches the
behavior of gas. I noticed that we ignored multiple mismatched symver
directives looking at https://reviews.llvm.org/D45798
Reviewers: pcc, tejohnson, espindola
Reviewed By: pcc
Subscribers: emaste, arichardson, llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D45845
llvm-svn: 331078
Nico Weber [Fri, 27 Apr 2018 20:29:57 +0000 (20:29 +0000)]
Revert r329698 (and r329702).
Speculative. ClangMoveTests started failing on
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/9958
after this change. I can't reproduce on my machine, let's see
if it was due to this change.
llvm-svn: 331077
Daniel Neilson [Fri, 27 Apr 2018 20:29:18 +0000 (20:29 +0000)]
[LV] Common duplicate vector load/store address calculation (NFC)
Summary:
Commoning some obviously copy/paste code in
InnerLoopVectorizer::vectorizeMemoryInstruction
llvm-svn: 331076
Rafael Espindola [Fri, 27 Apr 2018 20:19:28 +0000 (20:19 +0000)]
Don't create a temporary DenseMap for each input .eh_frame.
These maps are small, but we are creating an destroying one for each
input .eh_frame.
This patch reduces the total memory allocation from 765.54MB to
749.19MB. The peak is still the same: 563.7MB.
llvm-svn: 331075
Daniel Sanders [Fri, 27 Apr 2018 20:17:44 +0000 (20:17 +0000)]
Attempt to fix build failure after r331071 using std::make_tuple
llvm-svn: 331074
Frederic Riss [Fri, 27 Apr 2018 19:59:42 +0000 (19:59 +0000)]
[debugserver] Fix the G packet handling.
Of course r331004 needed a counterpart on the write side.
llvm-svn: 331073
Jun Bum Lim [Fri, 27 Apr 2018 19:59:20 +0000 (19:59 +0000)]
[PostRASink] extend the live-in check for all aliased registers
Extend the live-in check for all aliased registers so that we can
allow sinking Copy instructions when only implicit def is in successor's
live-in.
llvm-svn: 331072
Daniel Sanders [Fri, 27 Apr 2018 19:48:53 +0000 (19:48 +0000)]
[globalisel][legalizerinfo] Add support for legalization based on the MachineMemOperand
Summary:
Currently only the memory size is supported but others can be added as
needed.
narrowScalar for G_LOAD and G_STORE now correctly update the
MachineMemOperand and will refuse to legalize atomics since those need more
careful expansions to maintain atomicity.
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, aemerson, javed.absar
Reviewed By: aemerson
Subscribers: aemerson, rovka, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D45466
llvm-svn: 331071