i965/gen7+: Use NIR for lowering of pack/unpack opcodes.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965/vec4: Implement nir_op_pack_uvec2_to_uint.

And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced
by lowering pack[SU]norm4x8 which the vec4 backend does not need.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir: Add lowering support for unpacking opcodes.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir: Add lowering support for packing opcodes.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965/fs: Implement support for extract_word.

The vec4 backend will lower it.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir: Add opcodes to extract bytes or words.

The uint versions zero extend while the int versions sign extend.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

glsl: Remove 2x16 half-precision pack/unpack opcodes.

i965/fs was the only consumer, and we're now doing the lowering in NIR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir: Add lowering of nir_op_unpack_half_2x16.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Make separate nir_options for scalar/vector stages.

We'll want to have different lowering options set for scalar/vector
stages.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Move brw_compiler_create() to new brw_compiler.c.

A future patch will want to use designated initalizers, which aren't
available in C++, but this is C.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir: Make argument order of unop_convert match binop_convert.

Strangely the return and parameter types were reversed.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

mesa: enable enums for OES_geometry_shader

Enable GL_OES_geometry_shader enums for OpenGL ES 3.1.

V4: EXTRA tokens updated according to comments from Ilia Mirkin.

V5: Account for check_extra does not evaluate "or" lazy. Fix issues
with EXTRA_EXT_FB_NO_ATTACH_CS.

Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallium: Add DragonFly support

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

nv50/ir: get rid of memory stores with nop values

This happens especially with exports and varying packing, where the last
bits aren't always filled in. We end up trying to do quad-wide stores,
which ends up being a lot of register moves that carefully preserve the
nop value. Instead don't do the stores.

total instructions in shared programs : 6131375 -> 6125267 (-0.10%)
total gprs used in shared programs    : 910139 -> 895501 (-1.61%)
total local used in shared programs   : 15328 -> 15328 (0.00%)

                local        gpr       inst
    helped           0        7442        4693
      hurt           0          90        2687

Most of the helped/hurt instruction changes are by one or two ops
because can no longer do quad-wide stores in all cases.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: fix false global CSE on instructions with multiple defs

If an instruction has multiple defs, we have to do a lot more checks to
make sure that we can move it forward. Among other things, various code
likes to do

    a, b = tex()
    if () c = a
    else c = b

which means that a single phi node will have results pointing at the
same instruction. We obviously can't propagate the tex in this case, but
properly accounting for this situation is tricky. Just don't try for
instructions with multiple defs.

This fixes about 20 shaders in shader-db, including the dolphin efb2ram
shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

nv50,nvc0: fix buffer clearing to respect engine alignment requirements

It appears that the nvidia render engine is quite picky when it comes to
linear surfaces. It doesn't like non-256-byte aligned offsets, and
apparently doesn't even do non-256-byte strides.

This makes arb_clear_buffer_object-unaligned pass on both nv50 and nvc0.

As a side-effect this also allows RGB32 clears to work via GPU data
upload instead of synchronizing the buffer to the CPU (nvc0 only).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> # tested on GF108, GT215
Tested-by: Nick Sarnie <commendsarnex@gmail.com> # GK208
Cc: mesa-stable@lists.freedesktop.org

freedreno/ir3: ignore clip-vertex varying

Since we emulate clip-planes, the clip-vertex is used within the VS
itself (thanks to nir_lower_clip).  So just ignore it as a VS output.
Fixes a boatload of piglit tests that were asserting on unknown
varying slot.

(Also unrelated spelling/typo fix.)

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: don't ignore local vars

With glsl_to_nir we end up with local variables, instead of global, for
arrays.

Note that we'll eventually have to do something more clever, I think,
when we support multiple functions, but that will probably take some
work in a few places.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: handle tex instrs w/ const offset

Something we start to see with glsl_to_nir.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: support load_front_face intrinsic

With tgsi_to_nir we get this as a normal input with VARYING_SLOT_FACE.
But glsl_to_nir plus nir_lower_system_values this becomes an intrinsic.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: limit string marker to max packet size

Experimentally derived max size.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

nvc0: avoid crashing when there are holes in vertex array bindings

When using the "shared" vertex array configuration strategy, we bind
each of the buffers as a separate array. However there can be holes in
such vertex buffer lists, so just emit a disable for those.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

nvc0: enable atomic counters and ssbo

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: handle new TGSI MEMBAR opcode

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: fix atomic compare-and-swap arguments

Teach the emitter that the two registers are sequential, and drop the
second arg entirely, in favor of a double-wide first argument.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: add support for indirect buffer loading

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: add SUQ op by reading the info from driver constbuf

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: add support for BUFFER accesses

This largely leaves the existing image logic alone. When image support
is added this will have to be harmonized somehow.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: handle shader buffer memory barrier

Issue a MEM_BARRIER. No idea if this is sufficient. As there are no
tests for this, it'll have to do for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: add state management for shader buffers

(address, length) pairs are uploaded to the driver constbuf as well to
make these values available to the shaders.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: double per-shader stage driver constants area

We need to store a lot more info now with per-buffer address/size.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

trace: add support for set_shader_buffers

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
v1 -> v2: add arg_begin/arg_end around buffer array
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

st/mesa: enable ARB_shader_storage_buffer_object when supported

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: add shader buffer barrier bit

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: add support for memory barrier intrinsics

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
v1 -> v2: use TGSI_MEMBAR defines

st/mesa: use RESQ to find buffer size

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

st/mesa: add support for SSBO binding and GLSL intrinsics

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
v1 -> v2: some 80 char reformatting

st/mesa: add atomic counter support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add PROGRAM_IMMEDIATE, PROGRAM_BUFFER

This makes PROGRAM_IMMEDIATE a first-class gl_register_file type, and
adds PROGRAM_BUFFER to the list. These are used purely inside
glsl_to_tgsi conversion.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: keep track of ssbo variable being accessed, add access params

Currently any access params (coherent/volatile/restrict) are being lost
when lowering to the ssbo load/store intrinsics. Keep track of the
variable being used, and bake its access params in as the last arg of
the load/store intrinsics.

If the variable is accessed via an instance block, then 'variable'
points to the instance block variable and not the field inside the
instance block that we are accessing. In order to check access
parameters for the field itself we need to detect this case and keep
track of the corresponding field struct so we can extract the specific
field access information from there instead.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
v1 -> v2: add tracking of struct field
v2 -> v3: minor adjustments based on Iago's feedback
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

glsl: always initialize image_* fields, copy them on interface init

Interfaces can have image properties set in case they are buffer
interfaces. Make sure not to lose this information.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

tgsi: add MEMBAR opcode to handle memoryBarrier* GLSL intrinsics

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
v1 -> v2: add defines for the various bits
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

winsys/amdgpu: Process RADEON_FLAG_* independently from RADEON_DOMAIN_*

In particular, AMDGPU_GEM_CREATE_CPU_GTT_USWC can affect even BOs created
in VRAM if they get evicted to GTT. In general there's no need to
restrict any of the flags to any particular domains.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

winsys/amdgpu: Handle RADEON_FLAG_NO_CPU_ACCESS

Failing to do this was resulting in the kernel driver unnecessarily
leaving open the possibility of CPU access to tiled BOs.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93862

(This change shouldn't be backported to stable branches, because
released versions of xf86-video-amdgpu unnecessarily try to map the
front buffer)

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

nv50/ir: optimize mad/fma with third argument 0 to mul

Very modest effect, but it's clearly the right thing to do.

total instructions in shared programs : 6131491 -> 6131398 (-0.00%)
total gprs used in shared programs    : 910157 -> 910131 (-0.00%)
total local used in shared programs   : 15328 -> 15328 (0.00%)

                local        gpr       inst      bytes
    helped           0          55          85          85
      hurt           0          26          20          20

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: run DCE backwards

Reduces calls up to 50%

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: optimize shl(shr(a, c), c) to and(a, ~((1 << c) - 1))

Following shader-db results on GK110:

total instructions in shared programs : 6141510 -> 6131491 (-0.16%)
total gprs used in shared programs    : 910187 -> 910157 (-0.00%)
total local used in shared programs   : 15328 -> 15328 (0.00%)

                local        gpr       inst      bytes
    helped           0          18         821         821
      hurt           0           0           0           0

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: disallow implicit conversions in ESSL shaders

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: Add option for SI scheduler

Add a debug option to select the LLVM SI Machine Scheduler.
R600_DEBUG=sisched

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: double-precision values don't support interpolation

ARB_gpu_shader_fp64 spec says:

  "This extension does not support interpolation of double-precision
  values; doubles used as fragment shader inputs must be qualified as
  "flat"."

Fixes the regressions added by commit 781d278:

arb_gpu_shader_fp64-double-gettransformfeedbackvarying
arb_gpu_shader_fp64-tf-interleaved
arb_gpu_shader_fp64-tf-interleaved-aligned
arb_gpu_shader_fp64-tf-separate

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93878
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

vc4: Throttle outstanding rendering after submission.

Just make sure that after we've submitted, we get to at least 5
(global) submits ago before we go on to do more.  Prevents up to
seconds of lag with window movement in X with xcompmgr -c.  There may
be useful tuning to do in the future, but for now this gets us
usability.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

vc4: Don't record the seqno of a failed job submit.

On an error return, the returned seqno will probably be unset, so we'd
lose track of what we've submitted so far for waiting on in the
future.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

i965/skl: Utilize new 5th bit for gateway messages

Modify comment as spotted by Matt, and Chris Forbes

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

glsl: only expose double mod when doubles are available

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nv50/ir: fix memory corruption when spilling and redoing RA

When RA fails, and we spill, we have to clean everything up before doing
RA again. We were forgetting to reset the hi/lo linked lists - at
least the hi list is guaranteed to still have pointers to now-deleted
RIG nodes.

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

glsl: remove old FINISHME

This should have been removed long ago.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

configure.ac: don't require EGL/DRM and GBM if OpenGL is disabled

This allows building VDPAU/OMX/VA drivers without OpenGL and its
dependencies.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600,compute: Plug few memory leaks

v2: drop inline keyword
    drop radeon_llvm_dispose_kernel_module wrapper

v3: move definitions to .c file
    use in radeonsi

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

r600: Typos and whitespace fixes

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix clover crash

caused by ce1e7784d08a14a90e6051915f2622424a54dc6e

Trivial.

radeonsi: fix shader precompilation for shader-db

The addition of spi_shader_col_format killed all color outputs
in precompiled shaders.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
v2: also set the alpha func (trivial)

glsl: add GL_OES_geometry_point_size and conditionalize gl_PointSize

For now this will be enabled in tandem with GL_OES_geometry_shader.
Should a driver come along that wants to separate them out, another
enable can be added.

Also adds the missed GL_OES_geometry_shader define in glcpp.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>

glsl: move to compiler/

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>

nir: move to compiler/

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>

compiler: move the glsl_types C wrapper alongside their C++ brethren

At a later stage we might want to split out the NIR specific [XXX:
which one was it], as to make things move obvious and rename the files
appropriately. This patch aims to split it out of nir.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>

nir: move glsl_types.{cpp,h} to compiler

Allows us to remove the SCons workaround :-)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>

nir: move shader_enums.[ch] to compiler

This way one can reuse it in glsl, nir or other infrastructure without
pulling nir as dependency.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>

compiler: introduce a libcompiler static library

Currently it's an empty library, although it'll be used to store common
code between GLSL and NIR that is compiler specific (rather than generic
as the one in src/util).

XXX: strictly speaking we could add a python/mako parser to generate the
relevant files instead including builtin_type_macros.h in such a manner.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>

gallium/ddebug: add 'verbose' option

This currently just writes out the name of dump files, which can be useful
to easily correlate those files with other log outputs (driver debug output,
apitrace calls, etc.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/ddebug: make 'noflush' also affect 'always' mode

This changes the default behavior of 'always' mode to be consistent with
hang detection mode.

I have used this to more easily compare dumped command streams using diff.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: use llvm.amdgcn.s.barrier instead of llvm.AMDGPU.barrier.local

The new name for the intrinsic was introduced in LLVM r258558.

v2: use ternary operator instead of preprocessor

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965/bxt: Fix conservative wm thread counts.

When setting the conservative thread counts, I halved everything. That isn't
correct for the wm, which has nothing to do with actual thread counts. I suck.

BXT only has 1 slice, and there is some ambiguity about subslices, so just
reserve the max possible for now. It looks like this might fix:
piglit.spec.glsl-1_50.execution.variable-indexing.gs-output-array-vec4-index-wr.bxtm64.
I kind of question why that is, but it is what Jenkins says.

Mark is current running some of the other blacklisted tests on this patch. (it
effects anything requiring scratch space).

Cc: mesa-stable <mesa-stable@lists.freedesktop.org>
Cc: Neil Roberts <neil@linux.intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Mark Janes <mark.a.janes@intel.com>

meta: Use internal functions to set texture parameters

_mesa_texture_parameteriv is used because (the more obvious)
_mesa_texture_parameteri just stuffs the parameter in an array and calls
_mesa_texture_parameteriv.  This just cuts out the middleman.

As a side bonus we no longer need check that ARB_stencil_texturing is
supported.  The test doesn't allow non-supporting implementations to
avoid any work, and it's redundant with the value-changed test.

Fix bug #93717 because the state restore commands at the bottom of
_mesa_meta_GenerateMipmap no longer depend on the bound state.

Fixes  piglit   arb_direct_state_access-generatetexturemipmap  with  the
changes  recently sent  to the  piglit mailing  list.  See  the bugzilla
entry for more info.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93717
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

meta/blit: Restore GL_DEPTH_STENCIL_TEXTURE_MODE state for GL_TEXTURE_RECTANGLE

Commit c246828c added the code to save and restore the stencil
texturing mode.  The restore, however, was erroneously inside the
'target != GL_TEXTURE_RECTANGLE' block.

Fixes piglit test 'arb_stencil_texturing-blit_corrupts_state
GL_TEXTURE_RECTANGLE'.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

meta/copy_image: Fix typo in comment

Trivial.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

mesa: Don't include meta.h

Commit 055093e removed the call to _mesa_meta_in_progress, and meta.h
has not been necessary in src/mesa/main/enable.c since.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

radeonsi: add DCC buffer for sampler views on new CS

This fixes a VM fault and possible lockup in high memory pressure situations.

Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

radeonsi: emit rw_buffers for tes_shader only if tes_shader present

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: do not set the shader->key for gs copy shaders

The key for a geometry shader would be interpreted as the key for a vertex
shader further down the line, which really doesn't make sense.

This does not affect the contents of shader->key because geometry shaders
don't have any key entries anyway.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: si_llvm_emit_vs_epilogue is never used with gs copy shaders

Hence remove the misleading branch on is_gs_copy_shader.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: move is_gs_copy_shader to si_shader_context

It is only used during shader creation now, so no need to keep it around
afterwards.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: replace use of is_gs_copy_shader in si_shader_vs

We now have an explicit parameter that contains the same information, and
this will allow us to get rid of is_gs_copy_shader in the si_shader struct.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: ensure that VGT_GS_MODE is sent when necessary

Specifically, when the API switches from using a GS to not using a GS and then
back to using the same GS again, we do not have to re-send all the GS state,
but we do have to send VGT_GS_MODE. So make VGT_GS_MODE consistently be a part
of the VS state.

This fixes a rendering bug in Dolphin, but surely other applications are
affected as well.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93648
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: extract the VGT_GS_MODE calculation into its own function

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

trace: fix a segfault when tracing indirect draw calls

Like other resources, the indirect draw buffer must be unwrapped.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

Revert "mesa: enable enums for OES_geometry_shader"

This reverts commit 67e30987031d189d606125d4b712a575f619ab44.

It breaks a bunch of geometry shader tests, such as "spec@!opengl 3.2@minmax"
and others depending on the glGet queries.

winsys/amdgpu: optionally use buffer lists with all allocated buffers

Set RADEON_ALL_BOS=1 to use it.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

glsl: Conditionalize atan2 math.

In the old hand-writen implementation of atan2, the calculation of
atan(y/x) was performed conditionally in the "then" block of the
outermost if statement.  I believe I accidentally lifted this out
into unconditional code when converting to IR builder.

For reference, the original hand-written IR is visible in commit
722eff674b832e2321f791c68358ef52d2a1ff25.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: Erik Faye-Lund <kusmabite@gmail.com>

virgl: enable building on Android

This is just a copy-n-paste and rename of vc4 Android makefiles.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

virtio_gpu: Add PCI ID to driver map

Add the virtio-gpu PCI ID so the driver probing works.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: Implement a drirc workaround for broken dual color blending.

OpenGL's dual color blending feature was specified so that an
implementation could support both multiple render targets (MRT) and
dual source blending.  Fragment shader outputs specify both "location"
(the render target number) and "index" (either color 0 or 1).

I believe DirectX only has the notion of "location" - if using dual
color blending, location 0 or 1 will specify the operands.  If not,
then location means the render target index.  The two features can't
be used together.

As such, some applications mistakenly try to use <loc = 0, index = 0>
and <loc = 1, index = 0> in a shader used for dual color blending with
a single render target, rather than the correct <loc = 0, index = 0>
and <loc = 0, index = 1>.

In particular, Unigine Heaven 4.0 and Valley 1.0 suffer from this bug.
Unigine is aware of the problem, and quickly developed a fix, but has
not bothered to change the download link on their website to a working
copy in over a year.  People were still using the broken version and
complaining.  We tried working around this by disabling dual color
blending, but that apparently hurts performance, and people were once
again unhappy.

On i965, dual source blending is achieved by using different framebuffer
write messages than normal rendering.  So, we have to compile different
code for the two cases.  We're not being pedantic: we actually have to
know in order to function.

Normally, dual source blending is detectable in the shader: if a shader
has an output with index = 1, then it's meant for blending, not MRT.
With the broken inputs, they're indistinguishable, so we can only tell
by looking at the current GL state.

This patch implements a new drirc workaround:

   export dual_color_blend_by_location=true

which makes the i965 driver detect when OpenGL state is configured for
dual source blending, and recompile the fragment shader to use the right
messages.  In that case, we allow either location = 1 or index = 1 to
specify the second source for the blending equations.

It also re-enables GL_ARB_blend_func_extended for Unigine.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92233
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

radeonsi: add ETC1 support for Stoney

It's a subset of ETC2. Tested.

For more information, see page 42 and onward:
http://www.graphicshardware.org/previous/www_2007/presentations/strom-etc2-gh07.pdf

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: change LLVM intrinsics for BREV, CLAMP, EX2

Requested by Matt Arsenault.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add max waves / SIMD to shader stats (v2)

v2: account for LDS usage in PS
    the limit is per SIMD, not per CU

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: enable late VS allocation (v3)

v2: take the number of CUs into account
v3: change in LS allocation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: allow using all CUs for tessellation and on-chip GS (v2)

v2: After more discussion with hw teams, the kernel already contains the
    optimal settings allowing us to use all CUs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

Revert "mesa: Deal with size differences between GLuint and GLhandleARB in GetAttachedObjectsARB"

This reverts commit 739ac3d39dacdede853d150b9903001524453330.

This will be done a differnet way.
See http://lists.freedesktop.org/archives/mesa-dev/2016-January/105642.html

i965/fs: Remove unused count from vs urb setup

This was originally removed here:
commit 031d3501322aee0a1474c7f2a9b79f9fa9947430
Author: Kenneth Graunke <kenneth@whitecape.org>
Date:   Tue Aug 25 16:59:12 2015 -0700

    i965/vs: Unify URB entry size/read length calculations between backends.

Then added back:
commit bd198b9f0a292a9ff4ffffec3a29bad23d62caba
Author: Kenneth Graunke <kenneth@whitecape.org>
Date:   Fri Aug 14 16:01:33 2015 -0700

    i965/vs: Simplify fs_visitor's ATTR file.

Note that the authorship dates are out of order, but the above reflects the
order of the commit dates.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Revert "radeonsi: fix discard-only fragment shaders (v2)"

This reverts commit 843855bbf0da2204ce536623ba957bfa83fdbd52.

It became redundant due to Marek's earlier pushed 8667a1ae which achieves
the same thing.